Welcome to mirror list, hosted at ThFree Co, Russian Federation.

github.com/Flipper-Zero/STM32CubeWB.git - Unnamed repository; edit this file 'description' to name the repository.
summaryrefslogtreecommitdiff
path: root/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/Core/Src/app_debug.c
diff options
context:
space:
mode:
Diffstat (limited to 'Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/Core/Src/app_debug.c')
-rw-r--r--Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/Core/Src/app_debug.c109
1 files changed, 50 insertions, 59 deletions
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/Core/Src/app_debug.c b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/Core/Src/app_debug.c
index 9a5d338a0..246173ae6 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/Core/Src/app_debug.c
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_MeshLightingDemo/Core/Src/app_debug.c
@@ -36,23 +36,9 @@ typedef PACKED_STRUCT
uint8_t reserved;
} APPD_GpioConfig_t;
-typedef PACKED_STRUCT
-{
- uint8_t thread_config;
- uint8_t ble_config;
- uint8_t mac_802_15_4;
- uint8_t reserved;
-} APPD_TracesConfig_t;
-
-typedef PACKED_STRUCT
-{
- uint8_t ble_dtb_cfg;
- uint8_t reserved[3];
-} APPD_GeneralConfig_t;
-
/* Private defines -----------------------------------------------------------*/
#define GPIO_NBR_OF_RF_SIGNALS 9
-#define GPIO_CFG_NBR_OF_FEATURES 32
+#define GPIO_CFG_NBR_OF_FEATURES 34
#define NBR_OF_TRACES_CONFIG_PARAMETERS 4
#define NBR_OF_GENERAL_CONFIG_PARAMETERS 4
@@ -63,8 +49,8 @@ typedef PACKED_STRUCT
/* Private macros ------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
-PLACE_IN_SECTION("MB_MEM2") ALIGN(4) static APPD_TracesConfig_t APPD_TracesConfig={0, 0, 0, 0};
-PLACE_IN_SECTION("MB_MEM2") ALIGN(4) static APPD_GeneralConfig_t APPD_GeneralConfig={BLE_DTB_CFG, {0, 0, 0}};
+PLACE_IN_SECTION("MB_MEM2") ALIGN(4) static SHCI_C2_DEBUG_TracesConfig_t APPD_TracesConfig={0, 0, 0, 0};
+PLACE_IN_SECTION("MB_MEM2") ALIGN(4) static SHCI_C2_DEBUG_GeneralConfig_t APPD_GeneralConfig={BLE_DTB_CFG, {0, 0, 0}};
/**
* THE DEBUG ON GPIO FOR CPU2 IS INTENDED TO BE USED ONLY ON REQUEST FROM ST SUPPORT
@@ -74,39 +60,44 @@ PLACE_IN_SECTION("MB_MEM2") ALIGN(4) static APPD_GeneralConfig_t APPD_GeneralCon
*/
static const APPD_GpioConfig_t aGpioConfigList[GPIO_CFG_NBR_OF_FEATURES] =
{
- { GPIOA, LL_GPIO_PIN_0, 0, 0},
- { GPIOA, LL_GPIO_PIN_0, 0, 0},
- { GPIOA, LL_GPIO_PIN_0, 0, 0},
- { GPIOA, LL_GPIO_PIN_0, 0, 0},
- { GPIOA, LL_GPIO_PIN_0, 0, 0},
- { GPIOA, LL_GPIO_PIN_0, 0, 0},
- { GPIOA, LL_GPIO_PIN_0, 0, 0},
- { GPIOA, LL_GPIO_PIN_0, 0, 0},
- { GPIOA, LL_GPIO_PIN_0, 0, 0},
- { GPIOA, LL_GPIO_PIN_0, 0, 0},
- { GPIOA, LL_GPIO_PIN_0, 0, 0},
- { GPIOA, LL_GPIO_PIN_0, 0, 0},
- { GPIOA, LL_GPIO_PIN_0, 0, 0},
- { GPIOA, LL_GPIO_PIN_0, 0, 0},
- { GPIOA, LL_GPIO_PIN_0, 0, 0},
- { GPIOA, LL_GPIO_PIN_0, 0, 0},
- { GPIOA, LL_GPIO_PIN_0, 0, 0},
- { GPIOA, LL_GPIO_PIN_0, 0, 0},
- { GPIOA, LL_GPIO_PIN_0, 0, 0},
- { GPIOA, LL_GPIO_PIN_0, 0, 0},
-/* USER DEFINED IN M0 */
- { GPIOA, LL_GPIO_PIN_0, 0, 0},
- { GPIOA, LL_GPIO_PIN_0, 0, 0},
- { GPIOA, LL_GPIO_PIN_0, 0, 0},
- { GPIOA, LL_GPIO_PIN_0, 0, 0},
- { GPIOA, LL_GPIO_PIN_0, 0, 0},
- { GPIOA, LL_GPIO_PIN_0, 0, 0},
- { GPIOA, LL_GPIO_PIN_0, 0, 0},
- { GPIOA, LL_GPIO_PIN_0, 0, 0},
- { GPIOA, LL_GPIO_PIN_0, 0, 0},
- { GPIOA, LL_GPIO_PIN_0, 0, 0},
- { GPIOA, LL_GPIO_PIN_0, 0, 0},
- { GPIOA, LL_GPIO_PIN_0, 0, 0},
+ { GPIOA, LL_GPIO_PIN_0, 0, 0}, /* BLE_ISR - Set on Entry / Reset on Exit */
+ { GPIOA, LL_GPIO_PIN_0, 0, 0}, /* BLE_STACK_TICK - Set on Entry / Reset on Exit */
+ { GPIOA, LL_GPIO_PIN_0, 0, 0}, /* BLE_CMD_PROCESS - Set on Entry / Reset on Exit */
+ { GPIOA, LL_GPIO_PIN_0, 0, 0}, /* BLE_ACL_DATA_PROCESS - Set on Entry / Reset on Exit */
+ { GPIOA, LL_GPIO_PIN_0, 0, 0}, /* SYS_CMD_PROCESS - Set on Entry / Reset on Exit */
+ { GPIOA, LL_GPIO_PIN_0, 0, 0}, /* RNG_PROCESS - Set on Entry / Reset on Exit */
+ { GPIOA, LL_GPIO_PIN_0, 0, 0}, /* NVM_PROCESS - Set on Entry / Reset on Exit */
+ { GPIOA, LL_GPIO_PIN_0, 0, 0}, /* IPCC_GENERAL - Set on Entry / Reset on Exit */
+ { GPIOA, LL_GPIO_PIN_0, 0, 0}, /* IPCC_BLE_CMD_RX - Set on Entry / Reset on Exit */
+ { GPIOA, LL_GPIO_PIN_0, 0, 0}, /* IPCC_BLE_EVT_TX - Set on Entry / Reset on Exit */
+ { GPIOA, LL_GPIO_PIN_0, 0, 0}, /* IPCC_BLE_ACL_DATA_RX - Set on Entry / Reset on Exit */
+ { GPIOA, LL_GPIO_PIN_0, 0, 0}, /* IPCC_SYS_CMD_RX - Set on Entry / Reset on Exit */
+ { GPIOA, LL_GPIO_PIN_0, 0, 0}, /* IPCC_SYS_EVT_TX - Set on Entry / Reset on Exit */
+ { GPIOA, LL_GPIO_PIN_0, 0, 0}, /* IPCC_CLI_CMD_RX - Set on Entry / Reset on Exit */
+ { GPIOA, LL_GPIO_PIN_0, 0, 0}, /* IPCC_OT_CMD_RX - Set on Entry / Reset on Exit */
+ { GPIOA, LL_GPIO_PIN_0, 0, 0}, /* IPCC_OT_ACK_TX - Set on Entry / Reset on Exit */
+ { GPIOA, LL_GPIO_PIN_0, 0, 0}, /* IPCC_CLI_ACK_TX - Set on Entry / Reset on Exit */
+ { GPIOA, LL_GPIO_PIN_0, 0, 0}, /* IPCC_MEM_MANAGER_RX - Set on Entry / Reset on Exit */
+ { GPIOA, LL_GPIO_PIN_0, 0, 0}, /* IPCC_TRACES_TX - Set on Entry / Reset on Exit */
+ { GPIOA, LL_GPIO_PIN_0, 0, 0}, /* HARD_FAULT - Set on Entry / Reset on Exit */
+/* From v1.1.1 */
+ { GPIOA, LL_GPIO_PIN_0, 0, 0}, /* IP_CORE_LP_STATUS - Set on Entry / Reset on Exit */
+/* From v1.2.0 */
+ { GPIOA, LL_GPIO_PIN_0, 0, 0}, /* END_OF_CONNECTION_EVENT - Set on Entry / Reset on Exit */
+ { GPIOA, LL_GPIO_PIN_0, 0, 0}, /* TIMER_SERVER_CALLBACK - Toggle on Entry */
+ { GPIOA, LL_GPIO_PIN_0, 0, 0}, /* PES_ACTIVITY - Set on Entry / Reset on Exit */
+ { GPIOA, LL_GPIO_PIN_0, 0, 0}, /* MB_BLE_SEND_EVT - Set on Entry / Reset on Exit */
+/* From v1.3.0 */
+ { GPIOA, LL_GPIO_PIN_0, 0, 0}, /* BLE_NO_DELAY - Set on Entry / Reset on Exit */
+ { GPIOA, LL_GPIO_PIN_0, 0, 0}, /* BLE_STACK_STORE_NVM_CB - Set on Entry / Reset on Exit */
+ { GPIOA, LL_GPIO_PIN_0, 0, 0}, /* NVMA_WRITE_ONGOING - Set on Entry / Reset on Exit */
+ { GPIOA, LL_GPIO_PIN_0, 0, 0}, /* NVMA_WRITE_COMPLETE - Set on Entry / Reset on Exit */
+ { GPIOA, LL_GPIO_PIN_0, 0, 0}, /* NVMA_CLEANUP - Set on Entry / Reset on Exit */
+/* From v1.4.0 */
+ { GPIOA, LL_GPIO_PIN_0, 0, 0}, /* NVMA_START - Set on Entry / Reset on Exit */
+ { GPIOA, LL_GPIO_PIN_0, 0, 0}, /* FLASH_EOP - Set on Entry / Reset on Exit */
+ { GPIOA, LL_GPIO_PIN_0, 0, 0}, /* FLASH_WRITE - Set on Entry / Reset on Exit */
+ { GPIOA, LL_GPIO_PIN_0, 0, 0}, /* FLASH_ERASE - Set on Entry / Reset on Exit */
};
/**
@@ -119,15 +110,15 @@ static const APPD_GpioConfig_t aGpioConfigList[GPIO_CFG_NBR_OF_FEATURES] =
#if( BLE_DTB_CFG == 7)
static const APPD_GpioConfig_t aRfConfigList[GPIO_NBR_OF_RF_SIGNALS] =
{
- { GPIOB, LL_GPIO_PIN_2, 0, 0}, /* DTB10 */
- { GPIOB, LL_GPIO_PIN_7, 0, 0}, /* DTB11 */
- { GPIOA, LL_GPIO_PIN_8, 0, 0}, /* DTB12 */
- { GPIOA, LL_GPIO_PIN_9, 0, 0}, /* DTB13 */
- { GPIOA, LL_GPIO_PIN_10, 0, 0}, /* DTB14 */
- { GPIOA, LL_GPIO_PIN_11, 0, 0}, /* DTB15 */
- { GPIOB, LL_GPIO_PIN_8, 0, 0}, /* DTB16 */
- { GPIOB, LL_GPIO_PIN_11, 0, 0}, /* DTB17 */
- { GPIOB, LL_GPIO_PIN_10, 0, 0}, /* DTB18 */
+ { GPIOB, LL_GPIO_PIN_2, 0, 0}, /* DTB10 - Tx/Rx SPI */
+ { GPIOB, LL_GPIO_PIN_7, 0, 0}, /* DTB11 - Tx/Tx SPI Clk */
+ { GPIOA, LL_GPIO_PIN_8, 0, 0}, /* DTB12 - Tx/Rx Ready & SPI Select */
+ { GPIOA, LL_GPIO_PIN_9, 0, 0}, /* DTB13 - Tx/Rx Start */
+ { GPIOA, LL_GPIO_PIN_10, 0, 0}, /* DTB14 - FSM0 */
+ { GPIOA, LL_GPIO_PIN_11, 0, 0}, /* DTB15 - FSM1 */
+ { GPIOB, LL_GPIO_PIN_8, 0, 0}, /* DTB16 - FSM2 */
+ { GPIOB, LL_GPIO_PIN_11, 0, 0}, /* DTB17 - FSM3 */
+ { GPIOB, LL_GPIO_PIN_10, 0, 0}, /* DTB18 - FSM4 */
};
#endif
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-05 12:37:24 +0300