Welcome to mirror list, hosted at ThFree Co, Russian Federation.

github.com/Flipper-Zero/STM32CubeWB.git - Unnamed repository; edit this file 'description' to name the repository.
summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
Diffstat (limited to 'Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_p2pClient/BLE_p2pClient.ioc')
-rw-r--r--Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_p2pClient/BLE_p2pClient.ioc13
1 files changed, 8 insertions, 5 deletions
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_p2pClient/BLE_p2pClient.ioc b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_p2pClient/BLE_p2pClient.ioc
index 9163b7c63..796dde506 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_p2pClient/BLE_p2pClient.ioc
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_p2pClient/BLE_p2pClient.ioc
@@ -94,12 +94,13 @@ Mcu.PinsNb=17
Mcu.ThirdPartyNb=0
Mcu.UserConstants=
Mcu.UserName=STM32WB55RGVx
-MxCube.Version=5.4.0
-MxDb.Version=DB.5.0.40
+MxCube.Version=5.5.0
+MxDb.Version=DB.5.0.50
NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
NVIC.DMA1_Channel4_IRQn=true\:15\:0\:true\:false\:true\:false\:true
NVIC.DMA2_Channel4_IRQn=true\:15\:0\:true\:false\:true\:false\:true
NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.ForceEnableDMAVector=true
NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
NVIC.LPUART1_IRQn=true\:0\:0\:false\:false\:true\:true\:true
NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false
@@ -210,7 +211,7 @@ RCC.HSI48_VALUE=48000000
RCC.HSI_VALUE=16000000
RCC.I2C1Freq_Value=32000000
RCC.I2C3Freq_Value=32000000
-RCC.IPParameters=ADCFreq_Value,AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,APB3Freq_Value,Cortex2Freq_Value,CortexFreq_Value,FCLK2Freq_Value,FCLKCortexFreq_Value,FamilyName,HCLK2Freq_Value,HCLK3Freq_Value,HCLKFreq_Value,HCLKRFFreq_Value,HSE_VALUE,HSI48_VALUE,HSI_VALUE,I2C1Freq_Value,I2C3Freq_Value,LCDFreq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSI_VALUE,MCO1PinFreq_Value,PLLPoutputFreq_Value,PLLQoutputFreq_Value,PLLRCLKFreq_Value,PLLSAI1PoutputFreq_Value,PLLSAI1QoutputFreq_Value,PLLSAI1RoutputFreq_Value,PLLSourceVirtual,PWRFreq_Value,RFWKPClockSelection,RFWKPFreq_Value,RNGFreq_Value,RTCClockSelection,RTCFreq_Value,SAI1Freq_Value,SMPS1Freq_Value,SYSCLKFreq_VALUE,SYSCLKSource,USART1Freq_Value,USBFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value,VCOSAI1OutputFreq_Value
+RCC.IPParameters=ADCFreq_Value,AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,APB3Freq_Value,Cortex2Freq_Value,CortexFreq_Value,FCLK2Freq_Value,FCLKCortexFreq_Value,FamilyName,HCLK2Freq_Value,HCLK3Freq_Value,HCLKFreq_Value,HCLKRFFreq_Value,HSE_VALUE,HSI48_VALUE,HSI_VALUE,I2C1Freq_Value,I2C3Freq_Value,LCDFreq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSI_VALUE,MCO1PinFreq_Value,PLLPoutputFreq_Value,PLLQoutputFreq_Value,PLLRCLKFreq_Value,PLLSAI1PoutputFreq_Value,PLLSAI1QoutputFreq_Value,PLLSAI1RoutputFreq_Value,PLLSourceVirtual,PWRFreq_Value,RFWKPClockSelection,RFWKPFreq_Value,RNGFreq_Value,RTCClockSelection,RTCFreq_Value,SAI1Freq_Value,SMPS1Freq_Value,SMPSDivider,SMPSFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,USART1Freq_Value,USBFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value,VCOSAI1OutputFreq_Value
RCC.LCDFreq_Value=32768
RCC.LPTIM1Freq_Value=32000000
RCC.LPTIM2Freq_Value=32000000
@@ -232,7 +233,9 @@ RCC.RNGFreq_Value=32000
RCC.RTCClockSelection=RCC_RTCCLKSOURCE_LSE
RCC.RTCFreq_Value=32768
RCC.SAI1Freq_Value=64000000
-RCC.SMPS1Freq_Value=16000000
+RCC.SMPS1Freq_Value=8000000
+RCC.SMPSDivider=4
+RCC.SMPSFreq_Value=4000000
RCC.SYSCLKFreq_VALUE=32000000
RCC.SYSCLKSource=RCC_SYSCLKSOURCE_HSE
RCC.USART1Freq_Value=32000000
@@ -260,7 +263,7 @@ STM32_WPAN.CFG_HW_TS_NVIC_RTC_WAKEUP_IT_PREEMPTPRIO=3
STM32_WPAN.CFG_HW_TS_NVIC_RTC_WAKEUP_IT_SUBPRIO=0
STM32_WPAN.CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION=1
STM32_WPAN.CFG_HW_USART1_ENABLED=1
-STM32_WPAN.CFG_IO_CAPABILITY=CFG_IO_CAPABILITY_DISPLAY_ONLY
+STM32_WPAN.CFG_IO_CAPABILITY=\ CFG_IO_CAPABILITY_NO_INPUT_NO_OUTPUT
STM32_WPAN.CFG_LPM_SUPPORTED=1
STM32_WPAN.CFG_LP_CONN_ADV_INTERVAL_MAX=0xFA0
STM32_WPAN.CFG_LP_CONN_ADV_INTERVAL_MAX_HEXA=0xfa0