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Diffstat (limited to 'Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_p2pServer_ota/Core/Inc/app_conf.h')
-rw-r--r--Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_p2pServer_ota/Core/Inc/app_conf.h15
1 files changed, 8 insertions, 7 deletions
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_p2pServer_ota/Core/Inc/app_conf.h b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_p2pServer_ota/Core/Inc/app_conf.h
index 4a60494e4..7016925da 100644
--- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_p2pServer_ota/Core/Inc/app_conf.h
+++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_p2pServer_ota/Core/Inc/app_conf.h
@@ -25,6 +25,7 @@
#include "hw.h"
#include "hw_conf.h"
#include "hw_if.h"
+#include "ble_bufsize.h"
/******************************************************************************
* Application Config
@@ -130,7 +131,7 @@
* SMPS not used when Set to 0
* SMPS used when Set to 1
*/
-#define CFG_USE_SMPS 1
+#define CFG_USE_SMPS 0
/* USER CODE END Generic_Parameters */
/**< specific parameters */
@@ -255,10 +256,10 @@
#define CFG_BLE_MASTER_SCA 0
/**
- * Source for the 32 kHz slow speed clock
- * 1 : internal RO
- * 0 : external crystal ( no calibration )
- */
+ * Source for the low speed clock for RF wake-up
+ * 1 : external high speed crystal HSE/32/32
+ * 0 : external low speed crystal ( no calibration )
+ */
#define CFG_BLE_LSE_SOURCE 0
/**
@@ -346,8 +347,8 @@
******************************************************************************/
/**
* CFG_RTC_WUCKSEL_DIVIDER: This sets the RTCCLK divider to the wakeup timer.
- * The higher is the value, the better is the power consumption and the accuracy of the timerserver
- * The lower is the value, the finest is the granularity
+ * The lower is the value, the better is the power consumption and the accuracy of the timerserver
+ * The higher is the value, the finest is the granularity
*
* CFG_RTC_ASYNCH_PRESCALER: This sets the asynchronous prescaler of the RTC. It should as high as possible ( to ouput
* clock as low as possible) but the output clock should be equal or higher frequency compare to the clock feeding