diff options
Diffstat (limited to 'Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE_LLD/BLE_LLD_Lowpower/Core/Inc/gpio_lld.h')
| -rw-r--r-- | Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE_LLD/BLE_LLD_Lowpower/Core/Inc/gpio_lld.h | 152 |
1 files changed, 120 insertions, 32 deletions
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE_LLD/BLE_LLD_Lowpower/Core/Inc/gpio_lld.h b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE_LLD/BLE_LLD_Lowpower/Core/Inc/gpio_lld.h index 71678202a..e9ceb78c0 100644 --- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE_LLD/BLE_LLD_Lowpower/Core/Inc/gpio_lld.h +++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE_LLD/BLE_LLD_Lowpower/Core/Inc/gpio_lld.h @@ -6,41 +6,9 @@ #ifndef GPIO_LLD_H_ #define GPIO_LLD_H_ -#if defined (USE_SIMU) || defined (USE_FPGA) -/* Be carefull with GPIO used on SIMU plateform */ -// GPIOA port is used for CRC management on MASTER only -// GPIOC ad GPIOD ports are used to send messages between the 2 DORYs -#define GPIO_TX_PIN GPIO_PIN_8 -#define GPIO_TX_PORT GPIOB - -#define GPIO_1_PIN GPIO_PIN_9 -#define GPIO_1_PORT GPIOB -#else /* on Nucleo boards */ -/* Use GPIO PB.8 to monitor TX time during valid on Boards */ -#define GPIO_TX_PIN GPIO_PIN_8 -#define GPIO_TX_PORT GPIOB - #define GPIO_HARD_FAULT_PIN GPIO_PIN_4 #define GPIO_HARD_FAULT_PORT GPIOA -#define GPIO_MCO_PIN GPIO_PIN_15 -#define GPIO_MCO_PORT GPIOA - -#ifdef STM32WB35xx -#define GPIO_1_PIN GPIO_PIN_3 -#define GPIO_1_PORT GPIOB - -#define GPIO_2_PIN GPIO_PIN_4 -#define GPIO_2_PORT GPIOB -#else -#define GPIO_1_PIN GPIO_PIN_2 -#define GPIO_1_PORT GPIOC - -#define GPIO_2_PIN GPIO_PIN_3 -#define GPIO_2_PORT GPIOC -#endif -#endif - // External PA TX/RX pin is fixed by the chip #define GPIO_EXT_PA_TX_PIN GPIO_PIN_0 #define GPIO_EXT_PA_TX_PORT GPIOB @@ -88,4 +56,124 @@ void gpio_lld_led1_toggle(void); void gpio_lld_led2_toggle(void); void gpio_lld_led3_toggle(void); +#ifdef STM32WB15xx +#define BUTTON_SW1_EXTI_IRQHandler EXTI0_IRQHandler +#define BUTTON_SW2_EXTI_IRQHandler EXTI4_IRQHandler +#define BUTTON_SW3_EXTI_IRQHandler EXTI9_5_IRQHandler + +/** + * @brief USART pins + */ +#define USART_CLK_ENABLE() __HAL_RCC_USART1_CLK_ENABLE() + +#define USART_TX_AF GPIO_AF7_USART1 +#define USART_TX_GPIO_PORT GPIOA +#define USART_TX_PIN GPIO_PIN_9 +#define USART_TX_GPIO_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE() +#define USART_TX_GPIO_CLK_DISABLE() __HAL_RCC_GPIOA_CLK_DISABLE() + +#define USART_RX_AF GPIO_AF7_USART1 +#define USART_RX_GPIO_PORT GPIOA +#define USART_RX_PIN GPIO_PIN_10 +#define USART_RX_GPIO_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE() +#define USART_RX_GPIO_CLK_DISABLE() __HAL_RCC_GPIOA_CLK_DISABLE() + +/** + * @brief LPUART pins + */ +#define LPUART_CLK_ENABLE() __HAL_RCC_LPUART1_CLK_ENABLE() + +#define LPUART_TX_AF GPIO_AF8_LPUART1 +#define LPUART_TX_GPIO_PORT GPIOA +#define LPUART_TX_PIN GPIO_PIN_2 +#define LPUART_TX_GPIO_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE() +#define LPUART_TX_GPIO_CLK_DISABLE() __HAL_RCC_GPIOA_CLK_DISABLE() + +#define LPUART_RX_AF GPIO_AF8_LPUART1 +#define LPUART_RX_GPIO_PORT GPIOA +#define LPUART_RX_PIN GPIO_PIN_3 +#define LPUART_RX_GPIO_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE() +#define LPUART_RX_GPIO_CLK_DISABLE() __HAL_RCC_GPIOA_CLK_DISABLE() +#endif + +#ifdef STM32WB35xx +#define BUTTON_SW1_EXTI_IRQHandler EXTI0_IRQHandler +#define BUTTON_SW2_EXTI_IRQHandler EXTI4_IRQHandler +#define BUTTON_SW3_EXTI_IRQHandler EXTI9_5_IRQHandler + +/** + * @brief USART pins + */ +#define USART_CLK_ENABLE() __HAL_RCC_USART1_CLK_ENABLE() + +#define USART_TX_AF GPIO_AF7_USART1 +#define USART_TX_GPIO_PORT GPIOB +#define USART_TX_PIN GPIO_PIN_6 +#define USART_TX_GPIO_CLK_ENABLE() __HAL_RCC_GPIOB_CLK_ENABLE() +#define USART_TX_GPIO_CLK_DISABLE() __HAL_RCC_GPIOB_CLK_DISABLE() + +#define USART_RX_AF GPIO_AF7_USART1 +#define USART_RX_GPIO_PORT GPIOB +#define USART_RX_PIN GPIO_PIN_7 +#define USART_RX_GPIO_CLK_ENABLE() __HAL_RCC_GPIOB_CLK_ENABLE() +#define USART_RX_GPIO_CLK_DISABLE() __HAL_RCC_GPIOB_CLK_DISABLE() + +/** + * @brief LPUART pins + */ +#define LPUART_CLK_ENABLE() __HAL_RCC_LPUART1_CLK_ENABLE() + +#define LPUART_TX_AF GPIO_AF8_LPUART1 +#define LPUART_TX_GPIO_PORT GPIOB +#define LPUART_TX_PIN GPIO_PIN_5 +#define LPUART_TX_GPIO_CLK_ENABLE() __HAL_RCC_GPIOB_CLK_ENABLE() +#define LPUART_TX_GPIO_CLK_DISABLE() __HAL_RCC_GPIOB_CLK_DISABLE() + +#define LPUART_RX_AF GPIO_AF8_LPUART1 +#define LPUART_RX_GPIO_PORT GPIOA +#define LPUART_RX_PIN GPIO_PIN_3 +#define LPUART_RX_GPIO_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE() +#define LPUART_RX_GPIO_CLK_DISABLE() __HAL_RCC_GPIOA_CLK_DISABLE() +#endif + +#ifdef STM32WB55xx +#define BUTTON_SW1_EXTI_IRQHandler EXTI4_IRQHandler +#define BUTTON_SW2_EXTI_IRQHandler EXTI0_IRQHandler +#define BUTTON_SW3_EXTI_IRQHandler EXTI1_IRQHandler + +/** + * @brief USART pins + */ +#define USART_CLK_ENABLE() __HAL_RCC_USART1_CLK_ENABLE() + +#define USART_TX_AF GPIO_AF7_USART1 +#define USART_TX_GPIO_PORT GPIOB +#define USART_TX_PIN GPIO_PIN_6 +#define USART_TX_GPIO_CLK_ENABLE() __HAL_RCC_GPIOB_CLK_ENABLE() +#define USART_TX_GPIO_CLK_DISABLE() __HAL_RCC_GPIOB_CLK_DISABLE() + +#define USART_RX_AF GPIO_AF7_USART1 +#define USART_RX_GPIO_PORT GPIOB +#define USART_RX_PIN GPIO_PIN_7 +#define USART_RX_GPIO_CLK_ENABLE() __HAL_RCC_GPIOB_CLK_ENABLE() +#define USART_RX_GPIO_CLK_DISABLE() __HAL_RCC_GPIOB_CLK_DISABLE() + +/** + * @brief LPUART pins + */ +#define LPUART_CLK_ENABLE() __HAL_RCC_LPUART1_CLK_ENABLE() + +#define LPUART_TX_AF GPIO_AF8_LPUART1 +#define LPUART_TX_GPIO_PORT GPIOC +#define LPUART_TX_PIN GPIO_PIN_1 +#define LPUART_TX_GPIO_CLK_ENABLE() __HAL_RCC_GPIOC_CLK_ENABLE() +#define LPUART_TX_GPIO_CLK_DISABLE() __HAL_RCC_GPIOC_CLK_DISABLE() + +#define LPUART_RX_AF GPIO_AF8_LPUART1 +#define LPUART_RX_GPIO_PORT GPIOC +#define LPUART_RX_PIN GPIO_PIN_0 +#define LPUART_RX_GPIO_CLK_ENABLE() __HAL_RCC_GPIOC_CLK_ENABLE() +#define LPUART_RX_GPIO_CLK_DISABLE() __HAL_RCC_GPIOC_CLK_DISABLE() +#endif + #endif /* GPIO_LLD_H_ */ |