diff options
Diffstat (limited to 'Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE_Thread/Ble_Thread_Static/Core/Inc/hw_conf.h')
| -rw-r--r-- | Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE_Thread/Ble_Thread_Static/Core/Inc/hw_conf.h | 34 |
1 files changed, 31 insertions, 3 deletions
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE_Thread/Ble_Thread_Static/Core/Inc/hw_conf.h b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE_Thread/Ble_Thread_Static/Core/Inc/hw_conf.h index b76dd2494..3a86a4e83 100644 --- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE_Thread/Ble_Thread_Static/Core/Inc/hw_conf.h +++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE_Thread/Ble_Thread_Static/Core/Inc/hw_conf.h @@ -23,9 +23,37 @@ #define __HW_CONF_H /****************************************************************************** - * Semaphores - * THIS SHALL NO BE CHANGED AS THESE SEMAPHORES ARE USED AS WELL ON THE CM0+ - *****************************************************************************/ +* Semaphores +* THIS SHALL NO BE CHANGED AS THESE SEMAPHORES ARE USED AS WELL ON THE CM0+ +*****************************************************************************/ +/** +* Index of the semaphore used by CPU2 to prevent the CPU1 to either write or erase data in flash +* The CPU1 shall not either write or erase in flash when this semaphore is taken by the CPU2 +* When the CPU1 needs to either write or erase in flash, it shall first get the semaphore and release it just +* after writing a raw (64bits data) or erasing one sector. +* On v1.4.0 and older CPU2 wireless firmware, this semaphore is unused and CPU2 is using PES bit. +* By default, CPU2 is using the PES bit to protect its timing. The CPU1 may request the CPU2 to use the semaphore +* instead of the PES bit by sending the system command SHCI_C2_SetFlashActivityControl() +*/ +#define CFG_HW_BLOCK_FLASH_REQ_BY_CPU2_SEMID 7 + +/** +* Index of the semaphore used by CPU1 to prevent the CPU2 to either write or erase data in flash +* In order to protect its timing, the CPU1 may get this semaphore to prevent the CPU2 to either +* write or erase in flash (as this will stall both CPUs) +* The PES bit shall not be used as this may stall the CPU2 in some cases. +*/ +#define CFG_HW_BLOCK_FLASH_REQ_BY_CPU1_SEMID 6 + +/** +* Index of the semaphore used to manage the CLK48 clock configuration +* When the USB is required, this semaphore shall be taken before configuring te CLK48 for USB +* and should be released after the application switch OFF the clock when the USB is not used anymore +* When using the RNG, it is good enough to use CFG_HW_RNG_SEMID to control CLK48. +* More details in AN5289 +*/ +#define CFG_HW_CLK48_CONFIG_SEMID 5 + /* Index of the semaphore used to manage the entry Stop Mode procedure */ #define CFG_HW_ENTRY_STOP_MODE_SEMID 4 |