diff options
Diffstat (limited to 'Projects/P-NUCLEO-WB55.Nucleo/Applications/CKS/CKS_Crypt/Core/Inc/hw_conf.h')
| -rw-r--r-- | Projects/P-NUCLEO-WB55.Nucleo/Applications/CKS/CKS_Crypt/Core/Inc/hw_conf.h | 97 |
1 files changed, 89 insertions, 8 deletions
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/CKS/CKS_Crypt/Core/Inc/hw_conf.h b/Projects/P-NUCLEO-WB55.Nucleo/Applications/CKS/CKS_Crypt/Core/Inc/hw_conf.h index 6733a683f..b703e7393 100644 --- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/CKS/CKS_Crypt/Core/Inc/hw_conf.h +++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/CKS/CKS_Crypt/Core/Inc/hw_conf.h @@ -1,13 +1,13 @@ /* USER CODE BEGIN Header */ /** ****************************************************************************** - * File Name : hw_conf.h - * Description : Hardware configuration file for BLE - * middleWare. + * @file hw_conf.h + * @author MCD Application Team + * @brief Configuration of hardware interface ****************************************************************************** * @attention * - * <h2><center>© Copyright (c) 2019 STMicroelectronics. + * <h2><center>© Copyright (c) 2019 STMicroelectronics. * All rights reserved.</center></h2> * * This software component is licensed by ST under Ultimate Liberty license @@ -27,6 +27,36 @@ * Semaphores * THIS SHALL NO BE CHANGED AS THESE SEMAPHORES ARE USED AS WELL ON THE CM0+ *****************************************************************************/ +/** +* Index of the semaphore used by CPU2 to prevent the CPU1 to either write or erase data in flash +* The CPU1 shall not either write or erase in flash when this semaphore is taken by the CPU2 +* When the CPU1 needs to either write or erase in flash, it shall first get the semaphore and release it just +* after writing a raw (64bits data) or erasing one sector. +* Once the Semaphore has been released, there shall be at least 1us before it can be taken again. This is required +* to give the opportunity to CPU2 to take it. +* On v1.4.0 and older CPU2 wireless firmware, this semaphore is unused and CPU2 is using PES bit. +* By default, CPU2 is using the PES bit to protect its timing. The CPU1 may request the CPU2 to use the semaphore +* instead of the PES bit by sending the system command SHCI_C2_SetFlashActivityControl() +*/ +#define CFG_HW_BLOCK_FLASH_REQ_BY_CPU2_SEMID 7 + +/** +* Index of the semaphore used by CPU1 to prevent the CPU2 to either write or erase data in flash +* In order to protect its timing, the CPU1 may get this semaphore to prevent the CPU2 to either +* write or erase in flash (as this will stall both CPUs) +* The PES bit shall not be used as this may stall the CPU2 in some cases. +*/ +#define CFG_HW_BLOCK_FLASH_REQ_BY_CPU1_SEMID 6 + +/** +* Index of the semaphore used to manage the CLK48 clock configuration +* When the USB is required, this semaphore shall be taken before configuring te CLK48 for USB +* and should be released after the application switch OFF the clock when the USB is not used anymore +* When using the RNG, it is good enough to use CFG_HW_RNG_SEMID to control CLK48. +* More details in AN5289 +*/ +#define CFG_HW_CLK48_CONFIG_SEMID 5 + /* Index of the semaphore used to manage the entry Stop Mode procedure */ #define CFG_HW_ENTRY_STOP_MODE_SEMID 4 @@ -104,7 +134,6 @@ /****************************************************************************** * HW UART *****************************************************************************/ - #define CFG_HW_LPUART1_ENABLED 0 #define CFG_HW_LPUART1_DMA_TX_SUPPORTED 0 @@ -112,6 +141,58 @@ #define CFG_HW_USART1_DMA_TX_SUPPORTED 1 /** + * LPUART1 + */ +#define CFG_HW_LPUART1_PREEMPTPRIORITY 0x0F +#define CFG_HW_LPUART1_SUBPRIORITY 0 + +/** < The application shall check the selected source clock is enable */ +#define CFG_HW_LPUART1_SOURCE_CLOCK RCC_LPUART1CLKSOURCE_SYSCLK + +#define CFG_HW_LPUART1_BAUDRATE 115200 +#define CFG_HW_LPUART1_WORDLENGTH UART_WORDLENGTH_8B +#define CFG_HW_LPUART1_STOPBITS UART_STOPBITS_1 +#define CFG_HW_LPUART1_PARITY UART_PARITY_NONE +#define CFG_HW_LPUART1_HWFLOWCTL UART_HWCONTROL_NONE +#define CFG_HW_LPUART1_MODE UART_MODE_TX_RX +#define CFG_HW_LPUART1_ADVFEATUREINIT UART_ADVFEATURE_NO_INIT +#define CFG_HW_LPUART1_OVERSAMPLING UART_OVERSAMPLING_8 + +#define CFG_HW_LPUART1_TX_PORT_CLK_ENABLE __HAL_RCC_GPIOA_CLK_ENABLE +#define CFG_HW_LPUART1_TX_PORT GPIOA +#define CFG_HW_LPUART1_TX_PIN GPIO_PIN_2 +#define CFG_HW_LPUART1_TX_MODE GPIO_MODE_AF_PP +#define CFG_HW_LPUART1_TX_PULL GPIO_NOPULL +#define CFG_HW_LPUART1_TX_SPEED GPIO_SPEED_FREQ_VERY_HIGH +#define CFG_HW_LPUART1_TX_ALTERNATE GPIO_AF8_LPUART1 + +#define CFG_HW_LPUART1_RX_PORT_CLK_ENABLE __HAL_RCC_GPIOA_CLK_ENABLE +#define CFG_HW_LPUART1_RX_PORT GPIOA +#define CFG_HW_LPUART1_RX_PIN GPIO_PIN_3 +#define CFG_HW_LPUART1_RX_MODE GPIO_MODE_AF_PP +#define CFG_HW_LPUART1_RX_PULL GPIO_NOPULL +#define CFG_HW_LPUART1_RX_SPEED GPIO_SPEED_FREQ_VERY_HIGH +#define CFG_HW_LPUART1_RX_ALTERNATE GPIO_AF8_LPUART1 + +#define CFG_HW_LPUART1_CTS_PORT_CLK_ENABLE __HAL_RCC_GPIOA_CLK_ENABLE +#define CFG_HW_LPUART1_CTS_PORT GPIOA +#define CFG_HW_LPUART1_CTS_PIN GPIO_PIN_6 +#define CFG_HW_LPUART1_CTS_MODE GPIO_MODE_AF_PP +#define CFG_HW_LPUART1_CTS_PULL GPIO_PULLDOWN +#define CFG_HW_LPUART1_CTS_SPEED GPIO_SPEED_FREQ_VERY_HIGH +#define CFG_HW_LPUART1_CTS_ALTERNATE GPIO_AF8_LPUART1 + +#define CFG_HW_LPUART1_DMA_TX_PREEMPTPRIORITY 0x0F +#define CFG_HW_LPUART1_DMA_TX_SUBPRIORITY 0 + +#define CFG_HW_LPUART1_DMAMUX_CLK_ENABLE __HAL_RCC_DMAMUX1_CLK_ENABLE +#define CFG_HW_LPUART1_DMA_CLK_ENABLE __HAL_RCC_DMA1_CLK_ENABLE +#define CFG_HW_LPUART1_TX_DMA_REQ DMA_REQUEST_LPUART1_TX +#define CFG_HW_LPUART1_TX_DMA_CHANNEL DMA1_Channel4 +#define CFG_HW_LPUART1_TX_DMA_IRQn DMA1_Channel4_IRQn +#define CFG_HW_LPUART1_DMA_TX_IRQHandler DMA1_Channel4_IRQHandler + +/** * UART1 */ #define CFG_HW_USART1_PREEMPTPRIORITY 0x0F @@ -159,9 +240,9 @@ #define CFG_HW_USART1_DMAMUX_CLK_ENABLE __HAL_RCC_DMAMUX1_CLK_ENABLE #define CFG_HW_USART1_DMA_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE #define CFG_HW_USART1_TX_DMA_REQ DMA_REQUEST_USART1_TX -#define CFG_HW_USART1_TX_DMA_CHANNEL DMA2_CHANNEL_4 -#define CFG_HW_USART1_TX_DMA_IRQn DMA2_CHANNEL_4_IRQn -#define CFG_HW_USART1_DMA_TX_IRQHandler DMA2_CHANNEL_4_IRQHandler +#define CFG_HW_USART1_TX_DMA_CHANNEL DMA2_Channel4 +#define CFG_HW_USART1_TX_DMA_IRQn DMA2_Channel4_IRQn +#define CFG_HW_USART1_DMA_TX_IRQHandler DMA2_Channel4_IRQHandler #endif /*HW_CONF_H */ |