diff options
Diffstat (limited to 'Projects/P-NUCLEO-WB55.Nucleo/Applications/Thread/Thread_SED_Coap_Multicast/Core/Src/main.c')
| -rw-r--r-- | Projects/P-NUCLEO-WB55.Nucleo/Applications/Thread/Thread_SED_Coap_Multicast/Core/Src/main.c | 217 |
1 files changed, 15 insertions, 202 deletions
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/Thread/Thread_SED_Coap_Multicast/Core/Src/main.c b/Projects/P-NUCLEO-WB55.Nucleo/Applications/Thread/Thread_SED_Coap_Multicast/Core/Src/main.c index abe0d5d9f..cc77d87dc 100644 --- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/Thread/Thread_SED_Coap_Multicast/Core/Src/main.c +++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/Thread/Thread_SED_Coap_Multicast/Core/Src/main.c @@ -42,11 +42,7 @@ /* Private includes ----------------------------------------------------------*/ /* USER CODE BEGIN Includes */ -#include "stm32_lpm.h" -#include "stm32_seq.h" -#include "dbg_trace.h" -#include "hw_conf.h" -#include "otp.h" + /* USER CODE END Includes */ /* Private typedef -----------------------------------------------------------*/ @@ -86,12 +82,7 @@ static void MX_RF_Init(void); static void MX_RTC_Init(void); static void MX_IPCC_Init(void); /* USER CODE BEGIN PFP */ -void PeriphClock_Config(void); -static void Reset_Device( void ); -static void Reset_IPCC( void ); -static void Reset_BackupDomain( void ); -static void Init_Exti( void ); -static void Config_HSE(void); + /* USER CODE END PFP */ /* Private user code ---------------------------------------------------------*/ @@ -107,22 +98,17 @@ int main(void) { /* USER CODE BEGIN 1 */ - /** - * The OPTVERR flag is wrongly set at power on - * It shall be cleared before using any HAL_FLASH_xxx() api - */ - __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_OPTVERR); - /* USER CODE END 1 */ /* MCU Configuration--------------------------------------------------------*/ /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ HAL_Init(); + /* Config code for STM32_WPAN (HSE Tuning must be done before system clock configuration) */ + MX_APPE_Config(); /* USER CODE BEGIN Init */ - Reset_Device(); - Config_HSE(); + /* USER CODE END Init */ /* Configure the system clock */ @@ -132,8 +118,7 @@ int main(void) MX_IPCC_Init(); /* USER CODE BEGIN SysInit */ - PeriphClock_Config(); - Init_Exti(); /**< Configure the system Power Mode */ + /* USER CODE END SysInit */ /* Initialize all configured peripherals */ @@ -146,13 +131,13 @@ int main(void) /* USER CODE END 2 */ /* Init code for STM32_WPAN */ - APPE_Init(); + MX_APPE_Init(); /* Infinite loop */ /* USER CODE BEGIN WHILE */ while (1) { - UTIL_SEQ_Run( UTIL_SEQ_DEFAULT ); /* USER CODE END WHILE */ + MX_APPE_Process(); /* USER CODE BEGIN 3 */ } @@ -398,6 +383,12 @@ static void MX_RTC_Init(void) { Error_Handler(); } + /** Enable the WakeUp + */ + if (HAL_RTCEx_SetWakeUpTimer_IT(&hrtc, 0, RTC_WAKEUPCLOCK_RTCCLK_DIV16) != HAL_OK) + { + Error_Handler(); + } /* USER CODE BEGIN RTC_Init 2 */ /* USER CODE END RTC_Init 2 */ @@ -440,185 +431,7 @@ static void MX_GPIO_Init(void) } /* USER CODE BEGIN 4 */ -void PeriphClock_Config(void) -{ - #if (CFG_USB_INTERFACE_ENABLE != 0) - RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = { 0 }; - RCC_CRSInitTypeDef RCC_CRSInitStruct = { 0 }; - - /** - * This prevents the CPU2 to disable the HSI48 oscillator when - * it does not use anymore the RNG IP - */ - LL_HSEM_1StepLock( HSEM, 5 ); - - LL_RCC_HSI48_Enable(); - - while(!LL_RCC_HSI48_IsReady()); - - /* Select HSI48 as USB clock source */ - PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB; - PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48; - HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct); - - /*Configure the clock recovery system (CRS)**********************************/ - /* Enable CRS Clock */ - __HAL_RCC_CRS_CLK_ENABLE(); - - /* Default Synchro Signal division factor (not divided) */ - RCC_CRSInitStruct.Prescaler = RCC_CRS_SYNC_DIV1; - - /* Set the SYNCSRC[1:0] bits according to CRS_Source value */ - RCC_CRSInitStruct.Source = RCC_CRS_SYNC_SOURCE_USB; - - /* HSI48 is synchronized with USB SOF at 1KHz rate */ - RCC_CRSInitStruct.ReloadValue = RCC_CRS_RELOADVALUE_DEFAULT; - RCC_CRSInitStruct.ErrorLimitValue = RCC_CRS_ERRORLIMIT_DEFAULT; - - RCC_CRSInitStruct.Polarity = RCC_CRS_SYNC_POLARITY_RISING; - - /* Set the TRIM[5:0] to the default value*/ - RCC_CRSInitStruct.HSI48CalibrationValue = RCC_CRS_HSI48CALIBRATION_DEFAULT; - - /* Start automatic synchronization */ - HAL_RCCEx_CRSConfig(&RCC_CRSInitStruct); -#endif - - return; -} -/************************************************************* - * - * LOCAL FUNCTIONS - * - *************************************************************/ - -static void Config_HSE(void) -{ - OTP_ID0_t * p_otp; - - /** - * Read HSE_Tuning from OTP - */ - p_otp = (OTP_ID0_t *) OTP_Read(0); - if (p_otp) - { - LL_RCC_HSE_SetCapacitorTuning(p_otp->hse_tuning); - } - - return; -} - - -static void Reset_Device( void ) -{ -#if ( CFG_HW_RESET_BY_FW == 1 ) - Reset_BackupDomain(); - - Reset_IPCC(); -#endif - - return; -} - -static void Reset_IPCC( void ) -{ - LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_IPCC); - - LL_C1_IPCC_ClearFlag_CHx( - IPCC, - LL_IPCC_CHANNEL_1 | LL_IPCC_CHANNEL_2 | LL_IPCC_CHANNEL_3 | LL_IPCC_CHANNEL_4 - | LL_IPCC_CHANNEL_5 | LL_IPCC_CHANNEL_6); - - LL_C2_IPCC_ClearFlag_CHx( - IPCC, - LL_IPCC_CHANNEL_1 | LL_IPCC_CHANNEL_2 | LL_IPCC_CHANNEL_3 | LL_IPCC_CHANNEL_4 - | LL_IPCC_CHANNEL_5 | LL_IPCC_CHANNEL_6); - - LL_C1_IPCC_DisableTransmitChannel( - IPCC, - LL_IPCC_CHANNEL_1 | LL_IPCC_CHANNEL_2 | LL_IPCC_CHANNEL_3 | LL_IPCC_CHANNEL_4 - | LL_IPCC_CHANNEL_5 | LL_IPCC_CHANNEL_6); - - LL_C2_IPCC_DisableTransmitChannel( - IPCC, - LL_IPCC_CHANNEL_1 | LL_IPCC_CHANNEL_2 | LL_IPCC_CHANNEL_3 | LL_IPCC_CHANNEL_4 - | LL_IPCC_CHANNEL_5 | LL_IPCC_CHANNEL_6); - - LL_C1_IPCC_DisableReceiveChannel( - IPCC, - LL_IPCC_CHANNEL_1 | LL_IPCC_CHANNEL_2 | LL_IPCC_CHANNEL_3 | LL_IPCC_CHANNEL_4 - | LL_IPCC_CHANNEL_5 | LL_IPCC_CHANNEL_6); - - LL_C2_IPCC_DisableReceiveChannel( - IPCC, - LL_IPCC_CHANNEL_1 | LL_IPCC_CHANNEL_2 | LL_IPCC_CHANNEL_3 | LL_IPCC_CHANNEL_4 - | LL_IPCC_CHANNEL_5 | LL_IPCC_CHANNEL_6); - - return; -} - -static void Reset_BackupDomain( void ) -{ - if ((LL_RCC_IsActiveFlag_PINRST() != FALSE) && (LL_RCC_IsActiveFlag_SFTRST() == FALSE)) - { - HAL_PWR_EnableBkUpAccess(); /**< Enable access to the RTC registers */ - - /** - * Write twice the value to flush the APB-AHB bridge - * This bit shall be written in the register before writing the next one - */ - HAL_PWR_EnableBkUpAccess(); - - __HAL_RCC_BACKUPRESET_FORCE(); - __HAL_RCC_BACKUPRESET_RELEASE(); - } - - return; -} - -static void Init_Exti( void ) -{ - /**< Disable all wakeup interrupt on CPU1 except LPUART(25), IPCC(36), HSEM(38) */ - LL_EXTI_DisableIT_0_31( (~0) & (~(LL_EXTI_LINE_25)) ); - LL_EXTI_DisableIT_32_63( (~0) & (~(LL_EXTI_LINE_36 | LL_EXTI_LINE_38)) ); - - return; -} - -/************************************************************* - * - * WRAP FUNCTIONS - * - *************************************************************/ -void HAL_Delay(uint32_t Delay) -{ - uint32_t tickstart = HAL_GetTick(); - uint32_t wait = Delay; - - /* Add a freq to guarantee minimum wait */ - if (wait < HAL_MAX_DELAY) - { - wait += HAL_GetTickFreq(); - } - - while ((HAL_GetTick() - tickstart) < wait) - { - /************************************************************************************ - * ENTER SLEEP MODE - ***********************************************************************************/ - LL_LPM_EnableSleep( ); /**< Clear SLEEPDEEP bit of Cortex System Control Register */ - - /** - * This option is used to ensure that store operations are completed - */ - #if defined ( __CC_ARM) - __force_stores(); - #endif - - __WFI( ); - } -} /* USER CODE END 4 */ /** @@ -645,7 +458,7 @@ void assert_failed(uint8_t *file, uint32_t line) { /* USER CODE BEGIN 6 */ /* User can add his own implementation to report the file name and line number, - tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ /* USER CODE END 6 */ } #endif /* USE_FULL_ASSERT */ |