diff options
Diffstat (limited to 'Projects/P-NUCLEO-WB55.Nucleo/Examples/QSPI/QSPI_MemoryMapped/Src/main.c')
-rw-r--r-- | Projects/P-NUCLEO-WB55.Nucleo/Examples/QSPI/QSPI_MemoryMapped/Src/main.c | 47 |
1 files changed, 25 insertions, 22 deletions
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Examples/QSPI/QSPI_MemoryMapped/Src/main.c b/Projects/P-NUCLEO-WB55.Nucleo/Examples/QSPI/QSPI_MemoryMapped/Src/main.c index 3ac3f2a3a..3f0454735 100644 --- a/Projects/P-NUCLEO-WB55.Nucleo/Examples/QSPI/QSPI_MemoryMapped/Src/main.c +++ b/Projects/P-NUCLEO-WB55.Nucleo/Examples/QSPI/QSPI_MemoryMapped/Src/main.c @@ -8,13 +8,12 @@ ****************************************************************************** * @attention * - * <h2><center>© Copyright (c) 2019 STMicroelectronics. - * All rights reserved.</center></h2> + * Copyright (c) 2019-2021 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -59,6 +58,7 @@ uint8_t aTxBuffer[] = " ****Memory-mapped QSPI communication**** ****Memory-map /* Private function prototypes -----------------------------------------------*/ void SystemClock_Config(void); +void PeriphCommonClock_Config(void); static void MX_GPIO_Init(void); static void MX_DMA_Init(void); static void MX_QUADSPI_Init(void); @@ -103,6 +103,9 @@ int main(void) /* Configure the system clock */ SystemClock_Config(); +/* Configure the peripherals common clocks */ + PeriphCommonClock_Config(); + /* USER CODE BEGIN SysInit */ BSP_LED_Init(LED_GREEN); BSP_LED_Init(LED_RED); @@ -273,7 +276,6 @@ void SystemClock_Config(void) { RCC_OscInitTypeDef RCC_OscInitStruct = {0}; RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; - RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; /** Configure LSE Drive Capability */ @@ -321,19 +323,25 @@ void SystemClock_Config(void) { Error_Handler(); } - /** Initializes the peripherals clocks + /** Enable MSI Auto calibration + */ + HAL_RCCEx_EnableMSIPLLMode(); +} + +/** + * @brief Peripherals Common Clock Configuration + * @retval None */ - PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_SMPS|RCC_PERIPHCLK_USART1 - |RCC_PERIPHCLK_USB; - PeriphClkInitStruct.PLLSAI1.PLLN = 24; - PeriphClkInitStruct.PLLSAI1.PLLP = RCC_PLLP_DIV2; - PeriphClkInitStruct.PLLSAI1.PLLQ = RCC_PLLQ_DIV2; - PeriphClkInitStruct.PLLSAI1.PLLR = RCC_PLLR_DIV2; - PeriphClkInitStruct.PLLSAI1.PLLSAI1ClockOut = RCC_PLLSAI1_USBCLK; - PeriphClkInitStruct.Usart1ClockSelection = RCC_USART1CLKSOURCE_PCLK2; - PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1; +void PeriphCommonClock_Config(void) +{ + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; + + /** Initializes the peripherals clock + */ + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_SMPS; PeriphClkInitStruct.SmpsClockSelection = RCC_SMPSCLKSOURCE_HSI; PeriphClkInitStruct.SmpsDivSelection = RCC_SMPSCLKDIV_RANGE1; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) { Error_Handler(); @@ -341,9 +349,6 @@ void SystemClock_Config(void) /* USER CODE BEGIN Smps */ /* USER CODE END Smps */ - /** Enable MSI Auto calibration - */ - HAL_RCCEx_EnableMSIPLLMode(); } /** @@ -719,5 +724,3 @@ void assert_failed(uint8_t *file, uint32_t line) /* USER CODE END 6 */ } #endif /* USE_FULL_ASSERT */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |