diff options
Diffstat (limited to 'Projects/P-NUCLEO-WB55.USBDongle/Applications/Thread/Thread_FTD_Coap_Multicast/Core/Src/main.c')
| -rw-r--r-- | Projects/P-NUCLEO-WB55.USBDongle/Applications/Thread/Thread_FTD_Coap_Multicast/Core/Src/main.c | 63 |
1 files changed, 38 insertions, 25 deletions
diff --git a/Projects/P-NUCLEO-WB55.USBDongle/Applications/Thread/Thread_FTD_Coap_Multicast/Core/Src/main.c b/Projects/P-NUCLEO-WB55.USBDongle/Applications/Thread/Thread_FTD_Coap_Multicast/Core/Src/main.c index 7a144f6d2..9f1faa6ad 100644 --- a/Projects/P-NUCLEO-WB55.USBDongle/Applications/Thread/Thread_FTD_Coap_Multicast/Core/Src/main.c +++ b/Projects/P-NUCLEO-WB55.USBDongle/Applications/Thread/Thread_FTD_Coap_Multicast/Core/Src/main.c @@ -91,15 +91,6 @@ int main( void ) * LOCAL FUNCTIONS * *************************************************************/ -static void Init_Exti( void ) -{ - /**< Disable all wakeup interrupt on CPU1 except IPCC(36), HSEM(38) */ - LL_EXTI_DisableIT_0_31(~0); - LL_EXTI_DisableIT_32_63( (~0) & (~(LL_EXTI_LINE_36 | LL_EXTI_LINE_38)) ); - - return; -} - static void Reset_Device( void ) { #if ( CFG_HW_RESET_BY_FW == 1 ) @@ -206,7 +197,13 @@ static void Init_RTC( void ) hrtc.Init.SynchPrediv = CFG_RTC_SYNCH_PRESCALER; HAL_RTC_Init(&hrtc); - MODIFY_REG(RTC->CR, RTC_CR_WUCKSEL, CFG_RTC_WUCKSEL_DIVIDER); + /* Disable RTC registers write protection */ + LL_RTC_DisableWriteProtection(RTC); + + LL_RTC_WAKEUP_SetClock(RTC, CFG_RTC_WUCKSEL_DIVIDER); + + /* Enable RTC registers write protection */ + LL_RTC_EnableWriteProtection(RTC); return; } @@ -230,6 +227,12 @@ static void SystemClock_Config( void ) RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = { 0 }; RCC_CRSInitTypeDef RCC_CRSInitStruct = { 0 }; + /** + * This prevents the CPU2 to disable the HSI48 oscillator when + * it does not use anymore the RNG IP + */ + LL_HSEM_1StepLock( HSEM, 5 ); + LL_RCC_HSI48_Enable(); while(!LL_RCC_HSI48_IsReady()); @@ -280,17 +283,14 @@ static void SystemClock_Config( void ) */ LL_RCC_SetRFWKPClockSource(LL_RCC_RFWKP_CLKSOURCE_LSE); - /** - * Switch OFF LSI - */ - LL_RCC_LSI1_Disable(); + return; +} - /** - * Set RNG on HSI48 - */ - LL_RCC_HSI48_Enable(); - while(!LL_RCC_HSI48_IsReady()); - LL_RCC_SetCLK48ClockSource(LL_RCC_CLK48_CLKSOURCE_HSI48); +static void Init_Exti( void ) +{ + /**< Disable all wakeup interrupt on CPU1 except IPCC(36), HSEM(38) */ + LL_EXTI_DisableIT_0_31(~0); + LL_EXTI_DisableIT_32_63( (~0) & (~(LL_EXTI_LINE_36 | LL_EXTI_LINE_38)) ); return; } @@ -300,21 +300,34 @@ static void SystemClock_Config( void ) * WRAP FUNCTIONS * *************************************************************/ - -void HAL_Delay(uint32_t delay) +void HAL_Delay(uint32_t Delay) { uint32_t tickstart = HAL_GetTick(); - uint32_t wait = delay; + uint32_t wait = Delay; + /* Add a freq to guarantee minimum wait */ if (wait < HAL_MAX_DELAY) { - wait ++; + wait += HAL_GetTickFreq(); } while ((HAL_GetTick() - tickstart) < wait) { - UTIL_SEQ_Run( UTIL_SEQ_DEFAULT ); + /************************************************************************************ + * ENTER SLEEP MODE + ***********************************************************************************/ + LL_LPM_EnableSleep( ); /**< Clear SLEEPDEEP bit of Cortex System Control Register */ + + /** + * This option is used to ensure that store operations are completed + */ + #if defined ( __CC_ARM) + __force_stores(); + #endif + + __WFI( ); } } + /******************* (C) COPYRIGHT 2019 STMicroelectronics *****END OF FILE****/ |