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path: root/Projects/STM32WB5MM-DK/Applications/BLE/BLE_Mesh_Model_Sensor/Core/Src/main.c
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diff --git a/Projects/STM32WB5MM-DK/Applications/BLE/BLE_Mesh_Model_Sensor/Core/Src/main.c b/Projects/STM32WB5MM-DK/Applications/BLE/BLE_Mesh_Model_Sensor/Core/Src/main.c
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+/**
+ ******************************************************************************
+ * @file main.c
+ * @author MCD Application Team
+ * @brief BLE application with BLE core
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2019-2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ @verbatim
+ ==============================================================================
+ ##### IMPORTANT NOTE #####
+ ==============================================================================
+
+ This application requests having the stm32wb5x_BLE_Stack_fw.bin binary
+ flashed on the Wireless Coprocessor.
+ If it is not the case, you need to use STM32CubeProgrammer to load the appropriate
+ binary.
+
+ All available binaries are located under following directory:
+ /Projects/STM32_Copro_Wireless_Binaries
+
+ Refer to UM2237 to learn how to use/install STM32CubeProgrammer.
+ Refer to /Projects/STM32_Copro_Wireless_Binaries/ReleaseNote.html for the
+ detailed procedure to change the Wireless Coprocessor binary.
+
+ @endverbatim
+ ******************************************************************************
+ */
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "app_common.h"
+
+#include "app_entry.h"
+#include "stm32_lpm.h"
+#include "stm32_seq.h"
+#include "dbg_trace.h"
+
+#include "types.h"
+#include "ble_mesh.h"
+#include "appli_mesh.h"
+#include "models_if.h"
+#include "mesh_cfg.h"
+#include "otp.h"
+#include "stm32wbxx_hal_rcc.h"
+
+#include "stm32_lcd.h"
+#include "stm32wb5mm_dk_lcd.h"
+
+/** @addtogroup ST_BLE_Mesh
+ * @{
+ */
+
+/** @addtogroup Application
+* @{
+*/
+/* Private typedef -----------------------------------------------------------*/
+/* Private defines -----------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Global variables ---------------------------------------------------------*/
+RTC_HandleTypeDef hrtc = { 0 }; /**< RTC handler declaration */
+TIM_HandleTypeDef htim1 = { 0 };
+TIM_HandleTypeDef htim2 = { 0 };
+
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+static void Reset_BackupDomain( void );
+static void Init_RTC( void );
+static void SystemClock_Config( void );
+static void Reset_Device( void );
+static void Reset_IPCC( void );
+static void Init_Exti( void );
+void Error_Handler(void);
+void PeriphClock_Config(void);
+static void Config_HSE(void);
+
+/* Functions Definition ------------------------------------------------------*/
+
+/**
+ * @brief Main program
+ * @param None
+ * @retval None
+ */
+int main( void )
+{
+ HAL_Init();
+
+ Reset_Device();
+ Config_HSE();
+
+ /**
+ * When the application is expected to run at higher speed, it should be better to set the correct system clock
+ * in system_stm32yyxx.c so that the initialization phase is running at max speed.
+ */
+ SystemClock_Config(); /**< Configure the system clock */
+
+ PeriphClock_Config();
+
+// HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_16);
+
+ Init_Exti( );
+
+ Init_RTC();
+
+ /* Enable CRC clock */
+ __HAL_RCC_CRC_CLK_ENABLE();
+
+ /* BSP init LCD*/
+ BSP_LCD_Init(0, LCD_ORIENTATION_LANDSCAPE);
+
+// /* Set LCD Foreground Layer */
+ UTIL_LCD_SetFuncDriver(&LCD_Driver); /* SetFunc before setting device */
+ UTIL_LCD_SetDevice(0); /* SetDevice after funcDriver is set */
+
+ BSP_LCD_Clear(0,SSD1315_COLOR_BLACK);
+ BSP_LCD_DisplayOn(0);
+ BSP_LCD_SetBrightness(0, 50);
+ BSP_LCD_Refresh(0);
+
+ /* Set the LCD Text Color */
+ UTIL_LCD_SetTextColor(SSD1315_COLOR_WHITE);
+ UTIL_LCD_SetBackColor(SSD1315_COLOR_BLACK);
+ UTIL_LCD_SetFont(&Font12);
+
+#ifdef ENABLE_SENSOR_MODEL_SERVER
+ UTIL_LCD_DisplayStringAtLine(0, (uint8_t *)"Sensor Server");
+#elif ENABLE_SENSOR_MODEL_CLIENT
+ UTIL_LCD_DisplayStringAtLine(0, (uint8_t *)"Sensor Client");
+#else
+ UTIL_LCD_DisplayStringAtLine(0, (uint8_t *)"BLE Mesh ");
+#endif
+ BSP_LCD_Refresh(0);
+
+ APPE_Init( );
+
+#if ( CFG_LPM_SUPPORTED == 1)
+// BSP_LED_On(LED_GREEN);
+#endif
+
+ while(1)
+ {
+ UTIL_SEQ_Run( UTIL_SEQ_DEFAULT );
+ }
+}
+
+/*************************************************************
+ *
+ * LOCAL FUNCTIONS
+ *
+ *************************************************************/
+static void Init_Exti( void )
+{
+ /**< Disable all wakeup interrupt on CPU1 except IPCC(36), HSEM(38) */
+ LL_EXTI_DisableIT_0_31(~0);
+ LL_EXTI_DisableIT_32_63( (~0) & (~(LL_EXTI_LINE_36 | LL_EXTI_LINE_38)) );
+
+ return;
+}
+
+static void Reset_Device( void )
+{
+#if ( CFG_HW_RESET_BY_FW == 1 )
+ Reset_BackupDomain();
+
+ Reset_IPCC();
+#endif
+
+ return;
+}
+
+static void Reset_IPCC( void )
+{
+ LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_IPCC);
+
+ LL_C1_IPCC_ClearFlag_CHx(
+ IPCC,
+ LL_IPCC_CHANNEL_1 | LL_IPCC_CHANNEL_2 | LL_IPCC_CHANNEL_3 | LL_IPCC_CHANNEL_4
+ | LL_IPCC_CHANNEL_5 | LL_IPCC_CHANNEL_6);
+
+ LL_C2_IPCC_ClearFlag_CHx(
+ IPCC,
+ LL_IPCC_CHANNEL_1 | LL_IPCC_CHANNEL_2 | LL_IPCC_CHANNEL_3 | LL_IPCC_CHANNEL_4
+ | LL_IPCC_CHANNEL_5 | LL_IPCC_CHANNEL_6);
+
+ LL_C1_IPCC_DisableTransmitChannel(
+ IPCC,
+ LL_IPCC_CHANNEL_1 | LL_IPCC_CHANNEL_2 | LL_IPCC_CHANNEL_3 | LL_IPCC_CHANNEL_4
+ | LL_IPCC_CHANNEL_5 | LL_IPCC_CHANNEL_6);
+
+ LL_C2_IPCC_DisableTransmitChannel(
+ IPCC,
+ LL_IPCC_CHANNEL_1 | LL_IPCC_CHANNEL_2 | LL_IPCC_CHANNEL_3 | LL_IPCC_CHANNEL_4
+ | LL_IPCC_CHANNEL_5 | LL_IPCC_CHANNEL_6);
+
+ LL_C1_IPCC_DisableReceiveChannel(
+ IPCC,
+ LL_IPCC_CHANNEL_1 | LL_IPCC_CHANNEL_2 | LL_IPCC_CHANNEL_3 | LL_IPCC_CHANNEL_4
+ | LL_IPCC_CHANNEL_5 | LL_IPCC_CHANNEL_6);
+
+ LL_C2_IPCC_DisableReceiveChannel(
+ IPCC,
+ LL_IPCC_CHANNEL_1 | LL_IPCC_CHANNEL_2 | LL_IPCC_CHANNEL_3 | LL_IPCC_CHANNEL_4
+ | LL_IPCC_CHANNEL_5 | LL_IPCC_CHANNEL_6);
+
+ return;
+}
+
+static void Reset_BackupDomain( void )
+{
+ if ((LL_RCC_IsActiveFlag_PINRST() != FALSE) && (LL_RCC_IsActiveFlag_SFTRST() == FALSE))
+ {
+ HAL_PWR_EnableBkUpAccess(); /**< Enable access to the RTC registers */
+
+ /**
+ * Write twice the value to flush the APB-AHB bridge
+ * This bit shall be written in the register before writing the next one
+ */
+ HAL_PWR_EnableBkUpAccess();
+
+ __HAL_RCC_BACKUPRESET_FORCE();
+ __HAL_RCC_BACKUPRESET_RELEASE();
+ }
+
+ return;
+}
+
+static void Init_RTC( void )
+{
+ HAL_PWR_EnableBkUpAccess(); /**< Enable access to the RTC registers */
+
+ /**
+ * Write twice the value to flush the APB-AHB bridge
+ * This bit shall be written in the register before writing the next one
+ */
+ HAL_PWR_EnableBkUpAccess();
+
+ __HAL_RCC_RTC_CONFIG(RCC_RTCCLKSOURCE_LSE); /**< Select LSI as RTC Input */
+
+ __HAL_RCC_RTC_ENABLE(); /**< Enable RTC */
+
+ hrtc.Instance = RTC;
+ hrtc.Init.HourFormat = RTC_HOURFORMAT_24;
+ hrtc.Init.AsynchPrediv = CFG_RTC_ASYNCH_PRESCALER;
+ hrtc.Init.SynchPrediv = CFG_RTC_SYNCH_PRESCALER;
+ hrtc.Init.OutPut = RTC_OUTPUT_DISABLE;
+ hrtc.Init.OutPutPolarity = RTC_OUTPUT_POLARITY_HIGH;
+ hrtc.Init.OutPutType = RTC_OUTPUT_TYPE_OPENDRAIN;
+ if (HAL_RTC_Init(&hrtc) != HAL_OK)
+ {
+ Error_Handler();
+ }
+
+ /* Disable RTC registers write protection */
+ LL_RTC_DisableWriteProtection(RTC);
+
+ LL_RTC_WAKEUP_SetClock(RTC, CFG_RTC_WUCKSEL_DIVIDER);
+
+ /* Enable RTC registers write protection */
+ LL_RTC_EnableWriteProtection(RTC);
+
+ return;
+}
+
+void PeriphClock_Config(void)
+{
+#if (CFG_USB_INTERFACE_ENABLE != 0)
+ RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = { 0 };
+ RCC_CRSInitTypeDef RCC_CRSInitStruct = { 0 };
+
+ /**
+ * This prevents the CPU2 to disable the HSI48 oscillator when
+ * it does not use anymore the RNG IP
+ */
+ LL_HSEM_1StepLock( HSEM, 5 );
+
+ LL_RCC_HSI48_Enable();
+
+ while(!LL_RCC_HSI48_IsReady());
+
+ /* Select HSI48 as USB clock source */
+ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB;
+ PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48;
+ HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
+
+ /*Configure the clock recovery system (CRS)**********************************/
+
+ /* Enable CRS Clock */
+ __HAL_RCC_CRS_CLK_ENABLE();
+
+ /* Default Synchro Signal division factor (not divided) */
+ RCC_CRSInitStruct.Prescaler = RCC_CRS_SYNC_DIV1;
+
+ /* Set the SYNCSRC[1:0] bits according to CRS_Source value */
+ RCC_CRSInitStruct.Source = RCC_CRS_SYNC_SOURCE_USB;
+
+ /* HSI48 is synchronized with USB SOF at 1KHz rate */
+ RCC_CRSInitStruct.ReloadValue = RCC_CRS_RELOADVALUE_DEFAULT;
+ RCC_CRSInitStruct.ErrorLimitValue = RCC_CRS_ERRORLIMIT_DEFAULT;
+
+ RCC_CRSInitStruct.Polarity = RCC_CRS_SYNC_POLARITY_RISING;
+
+ /* Set the TRIM[5:0] to the default value*/
+ RCC_CRSInitStruct.HSI48CalibrationValue = RCC_CRS_HSI48CALIBRATION_DEFAULT;
+
+ /* Start automatic synchronization */
+ HAL_RCCEx_CRSConfig(&RCC_CRSInitStruct);
+#endif
+
+ return;
+}
+
+static void Config_HSE(void)
+{
+ OTP_ID0_t * p_otp;
+
+ /**
+ * Read HSE_Tuning from OTP
+ */
+ p_otp = (OTP_ID0_t *) OTP_Read(0);
+ if (p_otp)
+ {
+ LL_RCC_HSE_SetCapacitorTuning(p_otp->hse_tuning);
+ }
+
+ return;
+}
+
+ /**
+ * @brief This function is executed in case of error occurrence.
+ * @retval None
+ */
+void Error_Handler(void)
+{
+ /* USER CODE BEGIN Error_Handler_Debug */
+ /* User can add his own implementation to report the HAL error return state */
+
+ /* USER CODE END Error_Handler_Debug */
+ while(1); /* ERROR */
+}
+
+void SystemClock_Config(void)
+{
+ RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+ RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+ RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
+
+ /** Configure LSE Drive Capability
+ */
+ __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW);
+ /** Configure the main internal regulator output voltage
+ */
+ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+ /** Initializes the CPU, AHB and APB busses clocks
+ */
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI|RCC_OSCILLATORTYPE_HSE
+ |RCC_OSCILLATORTYPE_LSE;
+ RCC_OscInitStruct.HSEState = RCC_HSE_ON;
+ RCC_OscInitStruct.LSEState = RCC_LSE_ON;
+ RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+ RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+ {
+ Error_Handler();
+ }
+ /** Configure the SYSCLKSource, HCLK, PCLK1 and PCLK2 clocks dividers
+ */
+ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK4|RCC_CLOCKTYPE_HCLK2
+ |RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
+ |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSE;
+#if ( CFG_LPM_SUPPORTED == 1)
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV2;
+#else
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+#endif
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+ RCC_ClkInitStruct.AHBCLK2Divider = RCC_SYSCLK_DIV1;
+ RCC_ClkInitStruct.AHBCLK4Divider = RCC_SYSCLK_DIV1;
+
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)
+ {
+ Error_Handler();
+ }
+ /** Initializes the peripherals clocks
+ */
+ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_SMPS|RCC_PERIPHCLK_RFWAKEUP
+ |RCC_PERIPHCLK_RTC|RCC_PERIPHCLK_USART1
+ |RCC_PERIPHCLK_LPUART1;
+ PeriphClkInitStruct.Usart1ClockSelection = RCC_USART1CLKSOURCE_PCLK2;
+ PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_PCLK1;
+ PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSE;
+ PeriphClkInitStruct.RFWakeUpClockSelection = RCC_RFWKPCLKSOURCE_LSE;
+ PeriphClkInitStruct.SmpsClockSelection = RCC_SMPSCLKSOURCE_HSE;
+ PeriphClkInitStruct.SmpsDivSelection = RCC_SMPSCLKDIV_RANGE1;
+
+ if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
+ {
+ Error_Handler();
+ }
+ /* USER CODE BEGIN Smps */
+
+#if (CFG_USE_SMPS != 0)
+ /**
+ * Configure and enable SMPS
+ *
+ * The SMPS configuration is not yet supported by CubeMx
+ */
+ LL_PWR_SMPS_SetStartupCurrent(LL_PWR_SMPS_STARTUP_CURRENT_80MA);
+ LL_PWR_SMPS_SetOutputVoltageLevel(LL_PWR_SMPS_OUTPUT_VOLTAGE_1V40);
+ LL_PWR_SMPS_Enable();
+#endif
+ /* USER CODE END Smps */
+}
+
+
+/*************************************************************
+ *
+ * WRAP FUNCTIONS
+ *
+ *************************************************************/
+void HAL_Delay(uint32_t Delay)
+{
+ uint32_t tickstart = HAL_GetTick();
+ uint32_t wait = Delay;
+
+ /* Add a freq to guarantee minimum wait */
+ if (wait < HAL_MAX_DELAY)
+ {
+ wait += HAL_GetTickFreq();
+ }
+
+ while ((HAL_GetTick() - tickstart) < wait)
+ {
+ /************************************************************************************
+ * ENTER SLEEP MODE
+ ***********************************************************************************/
+ LL_LPM_EnableSleep( ); /**< Clear SLEEPDEEP bit of Cortex System Control Register */
+
+ /**
+ * This option is used to ensure that store operations are completed
+ */
+ #if defined ( __CC_ARM)
+ __force_stores();
+ #endif
+
+ __WFI( );
+ }
+}
+
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