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<title>CMSIS-Core (Cortex-M): Revision History of CMSIS-Core (Cortex-M)</title>
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<div id="projectname">CMSIS-Core (Cortex-M)
 <span id="projectnumber">Version 5.1.2</span>
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<div id="projectbrief">CMSIS-Core support for Cortex-M processor-based devices</div>
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<div class="title">Revision History of CMSIS-Core (Cortex-M) </div> </div>
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<div class="textblock"><table class="cmtable" summary="Revision History">
<tr>
<th>Version </th><th>Description </th></tr>
<tr>
<td>V5.1.2 </td><td>Removed using get/set built-ins FPSCR in GCC >= 7.2 due to shortcomings.<br/>
Added __NO_RETURN to __NVIC_SystemReset() to silence compiler warnings.<br/>
Added support for Cortex-M1 (beta). <br/>
Removed usage of register keyword. <br/>
Added defines for EXC_RETURN, FNC_RETURN and integrity signature values. <br/>
Enhanced MPUv7 API with defines for memory access attributes.<br/>
</td></tr>
<tr>
<td>V5.1.1 </td><td>Aligned MSPLIM and PSPLIM access functions along supported compilers.<br/>
</td></tr>
<tr>
<td>V5.1.0 </td><td>Added MPU Functions for ARMv8-M for Cortex-M23/M33.<br/>
Moved __SSAT and __USAT intrinsics to CMSIS-Core.<br/>
Aligned __REV, __REV16 and __REVSH intrinsics along supported compilers.<br/>
</td></tr>
<tr>
<td>V5.0.2 </td><td>Added macros <a class="el" href="group__compiler__conntrol__gr.html#gabe8693a7200e573101551d49a1772fb9">__UNALIGNED_UINT16_READ</a>, <a class="el" href="group__compiler__conntrol__gr.html#gadb9cd73446f7e11e92383cd327a23407">__UNALIGNED_UINT16_WRITE</a>.<br/>
Added macros <a class="el" href="group__compiler__conntrol__gr.html#ga254322c344d954c9f829719a50a88e87">__UNALIGNED_UINT32_READ</a>, <a class="el" href="group__compiler__conntrol__gr.html#gabb2180285c417aa9120a360c51f64b4b">__UNALIGNED_UINT32_WRITE</a>.<br/>
Deprecated macro <a class="el" href="group__compiler__conntrol__gr.html#ga27fd2ec6767ca1ab66d36b5cc0103268">__UNALIGNED_UINT32</a>.<br/>
Changed <a class="el" href="group__version__control__gr.html">Version Control</a> macros to be core agnostic. <br/>
Added <a class="el" href="group__mpu__functions.html">MPU Functions for Armv7-M</a> for Cortex-M0+/M3/M4/M7. </td></tr>
<tr>
<td>V5.0.1 </td><td>Added: macro <a class="el" href="group__compiler__conntrol__gr.html#ga4dbb70fab85207c27b581ecb6532b314">__PACKED_STRUCT</a>. <br/>
Added: uVisor support. <br/>
</td></tr>
<tr>
<td>V5.00 </td><td>Added: Cortex-M23, Cortex-M33 support.<br/>
Added: macro __SAU_PRESENT with __SAU_REGION_PRESENT. <br/>
Replaced: macro __SAU_PRESENT with __SAU_REGION_PRESENT. <br/>
Reworked: SAU register and functions. <br/>
Added: macro <a class="el" href="group__compiler__conntrol__gr.html#ga0c58caa5a273e2c21924509a45f8b849">__ALIGNED</a>. <br/>
Updated: function <a class="el" href="group__Icache__functions__m7.html#gaf9e7c6c8e16ada1f95e5bf5a03505b68">SCB_EnableICache</a>. <br/>
Added: cmsis_compiler.h with compiler specific CMSIS macros, functions, instructions. <br/>
Added: macro <a class="el" href="group__compiler__conntrol__gr.html#gabe8996d3d985ee1529475443cc635bf1">__PACKED</a>. <br/>
Updated: compiler specific include files. <br/>
Updated: core dependant include files. <br/>
Removed: deprecated files core_cmfunc.h, core_cminstr.h, core_cmsimd.h. </td></tr>
<tr>
<td>V5.00<br/>
Beta 6 </td><td>Added: SCB_CFSR register bit definitions. <br/>
Added: function <a class="el" href="group__NVIC__gr.html#ga72f102d31af0ee4aa7a6fb7a180840f3">NVIC_GetEnableIRQ</a>. <br/>
Updated: core instruction macros <a class="el" href="group__intrinsic__CPU__gr.html#gac71fad9f0a91980fecafcb450ee0a63e">__NOP</a>, <a class="el" href="group__intrinsic__CPU__gr.html#gaed91dfbf3d7d7b7fba8d912fcbeaad88">__WFI</a>, <a class="el" href="group__intrinsic__CPU__gr.html#gad3efec76c3bfa2b8528ded530386c563">__WFE</a>, <a class="el" href="group__intrinsic__CPU__gr.html#ga3c34da7eb16496ae2668a5b95fa441e7">__SEV</a> for toolchain GCC. </td></tr>
<tr>
<td>V5.00<br/>
Beta 5 </td><td>Moved: DSP libraries from CMSIS/DSP/Lib to CMSIS/Lib. <br/>
Added: DSP libraries build projects to CMSIS pack. </td></tr>
<tr>
<td>V5.00<br/>
Beta 4 </td><td>Updated: ARMv8M device files. <br/>
Corrected: ARMv8MBL interrupts. <br/>
Reworked: NVIC functions. </td></tr>
<tr>
<td>V5.00<br/>
Beta 2 </td><td>Changed: ARMv8M SAU regions to 8. <br/>
Changed: moved function <a class="el" href="group__sau__trustzone__functions.html#ga6093bc5939ea8924fbcfdffb8f0553f1">TZ_SAU_Setup</a> to file partition_<device>.h. <br/>
Changed: license under Apache-2.0. <br/>
Added: check if macro is defined before use. <br/>
Corrected: function <a class="el" href="group__Dcache__functions__m7.html#ga6468170f90d270caab8116e7a4f0b5fe">SCB_DisableDCache</a>. <br/>
Corrected: macros <a class="el" href="group__peripheral__gr.html#ga286e3b913dbd236c7f48ea70c8821f4e">_VAL2FLD</a>, <a class="el" href="group__peripheral__gr.html#ga139b6e261c981f014f386927ca4a8444">_FLD2VAL</a>. <br/>
Added: NVIC function virtualization with macros <a class="el" href="group__NVIC__gr.html#gadc48b4ed09386aab48fa6b9c96d9034c">CMSIS_NVIC_VIRTUAL</a> and <a class="el" href="group__NVIC__gr.html#gad01d3aa220b50ef141b06c93888b268d">CMSIS_VECTAB_VIRTUAL</a>. </td></tr>
<tr>
<td>V5.00<br/>
Beta 1 </td><td>Renamed: cmsis_armcc_V6.h to cmsis_armclang.h.<br/>
Renamed: core_*.h to lower case.<br/>
Added: function <a class="el" href="group__fpu__functions.html#ga6bcad99ce80a0e7e4ddc6f2379081756">SCB_GetFPUType</a> to all CMSIS cores.<br/>
Added: ARMv8-M support. </td></tr>
<tr>
<td>V4.30 </td><td>Corrected: DoxyGen function parameter comments.<br/>
Corrected: IAR toolchain: removed for <a class="el" href="group__NVIC__gr.html#ga1b47d17e90b6a03e7bd1ec6a0d549b46">NVIC_SystemReset</a> the attribute(noreturn).<br/>
Corrected: GCC toolchain: suppressed irrelevant compiler warnings.<br/>
Added: Support files for Arm Compiler v6 (cmsis_armcc_v6.h). </td></tr>
<tr>
<td>V4.20 </td><td>Corrected: MISRA-C:2004 violations. <br/>
Corrected: predefined macro for TI CCS Compiler. <br/>
Corrected: function <a class="el" href="group__intrinsic__SIMD__gr.html#ga15d8899a173effb8ad8c7268da32b60e">__SHADD16</a> in arm_math.h. <br/>
Updated: cache functions for Cortex-M7. <br/>
Added: macros <a class="el" href="group__peripheral__gr.html#ga286e3b913dbd236c7f48ea70c8821f4e">_VAL2FLD</a>, <a class="el" href="group__peripheral__gr.html#ga139b6e261c981f014f386927ca4a8444">_FLD2VAL</a> to core_*.h. <br/>
Updated: functions <a class="el" href="group__intrinsic__SIMD__gr.html#ga87618799672e1511e33964bc71467eb3">__QASX</a>, <a class="el" href="group__intrinsic__SIMD__gr.html#gab41eb2b17512ab01d476fc9d5bd19520">__QSAX</a>, <a class="el" href="group__intrinsic__SIMD__gr.html#gae0a649035f67627464fd80e7218c89d5">__SHASX</a>, <a class="el" href="group__intrinsic__SIMD__gr.html#gafadbd89c36b5addcf1ca10dd392db3e9">__SHSAX</a>. <br/>
Corrected: potential bug in function <a class="el" href="group__intrinsic__SIMD__gr.html#ga15d8899a173effb8ad8c7268da32b60e">__SHADD16</a>. </td></tr>
<tr>
<td>V4.10 </td><td>Corrected: MISRA-C:2004 violations. <br/>
Corrected: intrinsic functions <a class="el" href="group__intrinsic__CPU__gr.html#gacb2a8ca6eae1ba4b31161578b720c199">__DSB</a>, <a class="el" href="group__intrinsic__CPU__gr.html#gab1c9b393641dc2d397b3408fdbe72b96">__DMB</a>, <a class="el" href="group__intrinsic__CPU__gr.html#ga93c09b4709394d81977300d5f84950e5">__ISB</a>. <br/>
Corrected: register definitions for ITCMCR register. <br/>
Corrected: register definitions for <a class="el" href="unionCONTROL__Type.html">CONTROL_Type</a> register. <br/>
Added: functions <a class="el" href="group__fpu__functions.html#ga6bcad99ce80a0e7e4ddc6f2379081756">SCB_GetFPUType</a>, <a class="el" href="group__Dcache__functions__m7.html#ga503ef7ef58c0773defd15a82f6336c09">SCB_InvalidateDCache_by_Addr</a> to core_cm7.h. <br/>
Added: register definitions for <a class="el" href="unionAPSR__Type.html">APSR_Type</a>, <a class="el" href="unionIPSR__Type.html">IPSR_Type</a>, <a class="el" href="unionxPSR__Type.html">xPSR_Type</a> register. <br/>
Added: <a class="el" href="group__Core__Register__gr.html#ga62fa63d39cf22df348857d5f44ab64d9">__set_BASEPRI_MAX</a> function to core_cmFunc.h. <br/>
Added: intrinsic functions <a class="el" href="group__intrinsic__CPU__gr.html#gad6f9f297f6b91a995ee199fbc796b863">__RBIT</a>, <a class="el" href="group__intrinsic__CPU__gr.html#ga90884c591ac5d73d6069334eba9d6c02">__CLZ</a> for Cortex-M0/CortexM0+. <br/>
</td></tr>
<tr>
<td>V4.00 </td><td>Added: Cortex-M7 support.<br/>
Added: intrinsic functions for <a class="el" href="group__intrinsic__CPU__gr.html#gac09134f1bf9c49db07282001afcc9380">__RRX</a>, <a class="el" href="group__intrinsic__CPU__gr.html#ga9464d75db32846aa8295c3c3adfacb41">__LDRBT</a>, <a class="el" href="group__intrinsic__CPU__gr.html#gaa762b8bc5634ce38cb14d62a6b2aee32">__LDRHT</a>, <a class="el" href="group__intrinsic__CPU__gr.html#ga616504f5da979ba8a073d428d6e8d5c7">__LDRT</a>, <a class="el" href="group__intrinsic__CPU__gr.html#gad41aa59c92c0a165b7f98428d3320cd5">__STRBT</a>, <a class="el" href="group__intrinsic__CPU__gr.html#ga2b5d93b8e461755b1072a03df3f1722e">__STRHT</a>, and <a class="el" href="group__intrinsic__CPU__gr.html#ga625bc4ac0b1d50de9bcd13d9f050030e">__STRT</a> <br/>
</td></tr>
<tr>
<td>V3.40 </td><td>Corrected: C++ include guard settings.<br/>
</td></tr>
<tr>
<td>V3.30 </td><td>Added: COSMIC tool chain support.<br/>
Corrected: GCC __SMLALDX instruction intrinsic for Cortex-M4.<br/>
Corrected: GCC __SMLALD instruction intrinsic for Cortex-M4.<br/>
Corrected: GCC/CLang warnings.<br/>
</td></tr>
<tr>
<td>V3.20 </td><td>Added: <a class="el" href="group__intrinsic__CPU__gr.html#ga92f5621626711931da71eaa8bf301af7">__BKPT</a> instruction intrinsic.<br/>
Added: <a class="el" href="group__intrinsic__SIMD__gr.html#gaea60757232f740ec6b09980eebb614ff">__SMMLA</a> instruction intrinsic for Cortex-M4.<br/>
Corrected: <a class="el" href="group__ITM__Debug__gr.html#gaaa7c716331f74d644bf6bf25cd3392d1">ITM_SendChar</a>.<br/>
Corrected: <a class="el" href="group__Core__Register__gr.html#ga0f98dfbd252b89d12564472dbeba9c27">__enable_irq</a>, <a class="el" href="group__Core__Register__gr.html#gaeb8e5f7564a8ea23678fe3c987b04013">__disable_irq</a> and inline assembly for GCC Compiler.<br/>
Corrected: <a class="el" href="group__NVIC__gr.html#gab18fb9f6c5f4c70fdd73047f0f7c8395">NVIC_GetPriority</a> and VTOR_TBLOFF for Cortex-M0/M0+, SC000. <br/>
Corrected: rework of in-line assembly functions to remove potential compiler warnings.<br/>
</td></tr>
<tr>
<td>V3.01 </td><td>Added support for Cortex-M0+ processor.<br/>
</td></tr>
<tr>
<td>V3.00 </td><td>Added support for GNU GCC ARM Embedded Compiler. <br/>
Added function <a class="el" href="group__intrinsic__CPU__gr.html#gaf66beb577bb9d90424c3d1d7f684c024">__ROR</a>.<br/>
Added <a class="el" href="regMap_pg.html">Register Mapping</a> for TPIU, DWT. <br/>
Added support for <a class="el" href="device_h_pg.html#core_config_sect">SC000 and SC300 processors</a>.<br/>
Corrected <a class="el" href="group__ITM__Debug__gr.html#gaaa7c716331f74d644bf6bf25cd3392d1">ITM_SendChar</a> function. <br/>
Corrected the functions <a class="el" href="group__intrinsic__CPU__gr.html#gaab6482d1f59f59e2b6b7efc1af391c99">__STREXB</a>, <a class="el" href="group__intrinsic__CPU__gr.html#ga0a354bdf71caa52f081a4a54e84c8d2a">__STREXH</a>, <a class="el" href="group__intrinsic__CPU__gr.html#ga335deaaa7991490e1450cb7d1e4c5197">__STREXW</a> for the GNU GCC compiler section. <br/>
Documentation restructured. </td></tr>
<tr>
<td>V2.10 </td><td>Updated documentation.<br/>
Updated CMSIS core include files.<br/>
Changed CMSIS/Device folder structure.<br/>
Added support for Cortex-M0, Cortex-M4 w/o FPU to CMSIS DSP library.<br/>
Reworked CMSIS DSP library examples. </td></tr>
<tr>
<td>V2.00 </td><td>Added support for Cortex-M4 processor. </td></tr>
<tr>
<td>V1.30 </td><td>Reworked Startup Concept.<br/>
Added additional Debug Functionality.<br/>
Changed folder structure.<br/>
Added doxygen comments.<br/>
Added definitions for bit. </td></tr>
<tr>
<td>V1.01 </td><td>Added support for Cortex-M0 processor. </td></tr>
<tr>
<td>V1.01 </td><td>Added intrinsic functions for <a class="el" href="group__intrinsic__CPU__gr.html#ga9e3ac13d8dcf4331176b624cf6234a7e">__LDREXB</a>, <a class="el" href="group__intrinsic__CPU__gr.html#ga9feffc093d6f68b120d592a7a0d45a15">__LDREXH</a>, <a class="el" href="group__intrinsic__CPU__gr.html#gabd78840a0f2464905b7cec791ebc6a4c">__LDREXW</a>, <a class="el" href="group__intrinsic__CPU__gr.html#gaab6482d1f59f59e2b6b7efc1af391c99">__STREXB</a>, <a class="el" href="group__intrinsic__CPU__gr.html#ga0a354bdf71caa52f081a4a54e84c8d2a">__STREXH</a>, <a class="el" href="group__intrinsic__CPU__gr.html#ga335deaaa7991490e1450cb7d1e4c5197">__STREXW</a>, and <a class="el" href="group__intrinsic__CPU__gr.html#ga354c5ac8870cc3dfb823367af9c4b412">__CLREX</a> </td></tr>
<tr>
<td>V1.00 </td><td>Initial Release for Cortex-M3 processor. </td></tr>
</table>
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