Drivers/CMSIS/docs/Core_A/html/group__CMSIS__SCTLR.html


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<div class="title">System Control Register (SCTLR)<div class="ingroups"><a class="el" href="group__CMSIS__core__register.html">Core Register Access</a></div></div>  </div>
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<p>The SCTLR provides the top level control of the system, including its memory system.  
<a href="#details">More...</a></p>
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Content</h2></td></tr>
<tr class="memitem:group__CMSIS__SCTLR__BITS"><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html">SCTLR Bits</a></td></tr>
<tr class="memdesc:group__CMSIS__SCTLR__BITS"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bit position and mask macros. <br/></td></tr>
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Data Structures</h2></td></tr>
<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="unionSCTLR__Type.html">SCTLR_Type</a></td></tr>
<tr class="memdesc:"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bit field declaration for SCTLR layout.  <a href="unionSCTLR__Type.html#details">More...</a><br/></td></tr>
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Functions</h2></td></tr>
<tr class="memitem:gaf9b8e96ddd2e76c4475cf957600fd57a"><td class="memItemLeft" align="right" valign="top"><a class="el" href="cmsis__armcc_8h.html#ab904513442afdf77d4f8c74f23cbb040">__STATIC_FORCEINLINE</a> void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR.html#gaf9b8e96ddd2e76c4475cf957600fd57a">__set_SCTLR</a> (uint32_t sctlr)</td></tr>
<tr class="memdesc:gaf9b8e96ddd2e76c4475cf957600fd57a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Set SCTLR.  <a href="#gaf9b8e96ddd2e76c4475cf957600fd57a">More...</a><br/></td></tr>
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<tr class="memitem:ga3070304d6180433c91c4e6daef3f3c73"><td class="memItemLeft" align="right" valign="top"><a class="el" href="cmsis__armcc_8h.html#ab904513442afdf77d4f8c74f23cbb040">__STATIC_FORCEINLINE</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR.html#ga3070304d6180433c91c4e6daef3f3c73">__get_SCTLR</a> (void)</td></tr>
<tr class="memdesc:ga3070304d6180433c91c4e6daef3f3c73"><td class="mdescLeft">&#160;</td><td class="mdescRight">Get SCTLR.  <a href="#ga3070304d6180433c91c4e6daef3f3c73">More...</a><br/></td></tr>
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<a name="details" id="details"></a><h2 class="groupheader">Description</h2>
<p>In a VMSAv7 implementation, the SCTLR bit assignments are:</p>
<table class="doxtable">
<tr>
<th align="left">Bits </th><th align="left">Name </th><th align="left">Function  </th></tr>
<tr>
<td align="left">[31] </td><td align="left">- </td><td align="left">Reserved. </td></tr>
<tr>
<td align="left">[30] </td><td align="left">TE </td><td align="left">Thumb Exception enable. </td></tr>
<tr>
<td align="left">[29] </td><td align="left">AFE </td><td align="left">Access flag enable bit. </td></tr>
<tr>
<td align="left">[28] </td><td align="left">TRE </td><td align="left">TEX remap enable bit. </td></tr>
<tr>
<td align="left">[27:26] </td><td align="left">- </td><td align="left">Reserved. </td></tr>
<tr>
<td align="left">[25] </td><td align="left">EE </td><td align="left">Exception Endianness bit. </td></tr>
<tr>
<td align="left">[24:21] </td><td align="left">- </td><td align="left">Reserved. </td></tr>
<tr>
<td align="left">[20] </td><td align="left">UWXN </td><td align="left">Unprivileged write permission implies PL1 Execute Never (XN). </td></tr>
<tr>
<td align="left">[19] </td><td align="left">WXN </td><td align="left">Write permission implies Execute Never (XN). </td></tr>
<tr>
<td align="left">[18:14] </td><td align="left">- </td><td align="left">Reserved. </td></tr>
<tr>
<td align="left">[13] </td><td align="left">V </td><td align="left">Vectors bit. </td></tr>
<tr>
<td align="left">[12] </td><td align="left">I </td><td align="left">Instruction cache enable bit. </td></tr>
<tr>
<td align="left">[11] </td><td align="left">Z </td><td align="left">Branch prediction enable bit. </td></tr>
<tr>
<td align="left">[10] </td><td align="left">SW </td><td align="left">SWP and SWPB enable bit. </td></tr>
<tr>
<td align="left">[9:3] </td><td align="left">- </td><td align="left">Reserved. </td></tr>
<tr>
<td align="left">[2] </td><td align="left">C </td><td align="left">Cache enable bit. </td></tr>
<tr>
<td align="left">[1] </td><td align="left">A </td><td align="left">Alignment bit. </td></tr>
<tr>
<td align="left">[0] </td><td align="left">M </td><td align="left">Address translation enable bit. </td></tr>
</table>
<p>Consider using <a class="el" href="group__CMSIS__SCTLR.html#ga3070304d6180433c91c4e6daef3f3c73">__get_SCTLR</a> and <a class="el" href="group__CMSIS__SCTLR.html#gaf9b8e96ddd2e76c4475cf957600fd57a">__set_SCTLR</a> for accessing this register. </p>
<h2 class="groupheader">Function Documentation</h2>
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          <td class="memname"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> uint32_t __get_SCTLR </td>
          <td>(</td>
          <td class="paramtype">void&#160;</td>
          <td class="paramname"></td><td>)</td>
          <td></td>
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<dl class="section return"><dt>Returns</dt><dd>System Control Register value</dd></dl>
<p>This function returns the value of the <a class="el" href="group__CMSIS__SCTLR.html">System Control Register (SCTLR)</a>. </p>

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          <td class="memname"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void __set_SCTLR </td>
          <td>(</td>
          <td class="paramtype">uint32_t&#160;</td>
          <td class="paramname"><em>sctlr</em></td><td>)</td>
          <td></td>
        </tr>
      </table>
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<p>This function assigns the given value to the System Control Register.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">sctlr</td><td>System Control Register value to set</td></tr>
  </table>
  </dd>
</dl>
<p>This function assigns the given value to the <a class="el" href="group__CMSIS__SCTLR.html">System Control Register (SCTLR)</a>. </p>

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