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<p>Generic functions to access the Interrupt Controller.
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<table class="memberdecls">
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Content</h2></td></tr>
<tr class="memitem:group__irq__mode__defs"><td class="memItemLeft" align="right" valign="top"> </td><td class="memItemRight" valign="bottom"><a class="el" href="group__irq__mode__defs.html">IRQ Mode Bit-Masks</a></td></tr>
<tr class="memdesc:group__irq__mode__defs"><td class="mdescLeft"> </td><td class="mdescRight">Configure interrupt line mode. <br/></td></tr>
<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:group__irq__priority__defs"><td class="memItemLeft" align="right" valign="top"> </td><td class="memItemRight" valign="bottom"><a class="el" href="group__irq__priority__defs.html">IRQ Priority Bit-Masks</a></td></tr>
<tr class="memdesc:group__irq__priority__defs"><td class="mdescLeft"> </td><td class="mdescRight">Definitions used by interrupt priority functions. <br/></td></tr>
<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
</table><table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="func-members"></a>
Functions</h2></td></tr>
<tr class="memitem:ga03ea5d5d67a89acff8a5b02286795a99"><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__irq__ctrl__gr.html#ga03ea5d5d67a89acff8a5b02286795a99">IRQ_Initialize</a> (void)</td></tr>
<tr class="memdesc:ga03ea5d5d67a89acff8a5b02286795a99"><td class="mdescLeft"> </td><td class="mdescRight">Initialize interrupt controller. <a href="#ga03ea5d5d67a89acff8a5b02286795a99">More...</a><br/></td></tr>
<tr class="separator:ga03ea5d5d67a89acff8a5b02286795a99"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gac1fcc16fb8e488d315cfa496f1d71db3"><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__irq__ctrl__gr.html#gac1fcc16fb8e488d315cfa496f1d71db3">IRQ_SetHandler</a> (<a class="el" href="irq__ctrl_8h.html#ac62964c04a7fed2c84aeea9e34f415e2">IRQn_ID_t</a> irqn, <a class="el" href="irq__ctrl_8h.html#afbfa2180a9b6208f34891d539e9e2d52">IRQHandler_t</a> handler)</td></tr>
<tr class="memdesc:gac1fcc16fb8e488d315cfa496f1d71db3"><td class="mdescLeft"> </td><td class="mdescRight">Register interrupt handler. <a href="#gac1fcc16fb8e488d315cfa496f1d71db3">More...</a><br/></td></tr>
<tr class="separator:gac1fcc16fb8e488d315cfa496f1d71db3"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gaa2a2df8fbc7bad465ada49bd690f65d5"><td class="memItemLeft" align="right" valign="top"><a class="el" href="irq__ctrl_8h.html#afbfa2180a9b6208f34891d539e9e2d52">IRQHandler_t</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="group__irq__ctrl__gr.html#gaa2a2df8fbc7bad465ada49bd690f65d5">IRQ_GetHandler</a> (<a class="el" href="irq__ctrl_8h.html#ac62964c04a7fed2c84aeea9e34f415e2">IRQn_ID_t</a> irqn)</td></tr>
<tr class="memdesc:gaa2a2df8fbc7bad465ada49bd690f65d5"><td class="mdescLeft"> </td><td class="mdescRight">Get the registered interrupt handler. <a href="#gaa2a2df8fbc7bad465ada49bd690f65d5">More...</a><br/></td></tr>
<tr class="separator:gaa2a2df8fbc7bad465ada49bd690f65d5"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga4ad780a3dc23a1b6222de8adcd7c20a7"><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__irq__ctrl__gr.html#ga4ad780a3dc23a1b6222de8adcd7c20a7">IRQ_Enable</a> (<a class="el" href="irq__ctrl_8h.html#ac62964c04a7fed2c84aeea9e34f415e2">IRQn_ID_t</a> irqn)</td></tr>
<tr class="memdesc:ga4ad780a3dc23a1b6222de8adcd7c20a7"><td class="mdescLeft"> </td><td class="mdescRight">Enable interrupt. <a href="#ga4ad780a3dc23a1b6222de8adcd7c20a7">More...</a><br/></td></tr>
<tr class="separator:ga4ad780a3dc23a1b6222de8adcd7c20a7"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga544cf4ae0159cc17e259d55898528248"><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__irq__ctrl__gr.html#ga544cf4ae0159cc17e259d55898528248">IRQ_Disable</a> (<a class="el" href="irq__ctrl_8h.html#ac62964c04a7fed2c84aeea9e34f415e2">IRQn_ID_t</a> irqn)</td></tr>
<tr class="memdesc:ga544cf4ae0159cc17e259d55898528248"><td class="mdescLeft"> </td><td class="mdescRight">Disable interrupt. <a href="#ga544cf4ae0159cc17e259d55898528248">More...</a><br/></td></tr>
<tr class="separator:ga544cf4ae0159cc17e259d55898528248"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga8913613a9075a35410af0eb7b275d9e2"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__irq__ctrl__gr.html#ga8913613a9075a35410af0eb7b275d9e2">IRQ_GetEnableState</a> (<a class="el" href="irq__ctrl_8h.html#ac62964c04a7fed2c84aeea9e34f415e2">IRQn_ID_t</a> irqn)</td></tr>
<tr class="memdesc:ga8913613a9075a35410af0eb7b275d9e2"><td class="mdescLeft"> </td><td class="mdescRight">Get interrupt enable state. <a href="#ga8913613a9075a35410af0eb7b275d9e2">More...</a><br/></td></tr>
<tr class="separator:ga8913613a9075a35410af0eb7b275d9e2"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gab35da69354d2e515931580a1308a3a85"><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__irq__ctrl__gr.html#gab35da69354d2e515931580a1308a3a85">IRQ_SetMode</a> (<a class="el" href="irq__ctrl_8h.html#ac62964c04a7fed2c84aeea9e34f415e2">IRQn_ID_t</a> irqn, uint32_t mode)</td></tr>
<tr class="memdesc:gab35da69354d2e515931580a1308a3a85"><td class="mdescLeft"> </td><td class="mdescRight">Configure interrupt request mode. <a href="#gab35da69354d2e515931580a1308a3a85">More...</a><br/></td></tr>
<tr class="separator:gab35da69354d2e515931580a1308a3a85"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gadba142ee49ae8f52f76b603c926ad711"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__irq__ctrl__gr.html#gadba142ee49ae8f52f76b603c926ad711">IRQ_GetMode</a> (<a class="el" href="irq__ctrl_8h.html#ac62964c04a7fed2c84aeea9e34f415e2">IRQn_ID_t</a> irqn)</td></tr>
<tr class="memdesc:gadba142ee49ae8f52f76b603c926ad711"><td class="mdescLeft"> </td><td class="mdescRight">Get interrupt mode configuration. <a href="#gadba142ee49ae8f52f76b603c926ad711">More...</a><br/></td></tr>
<tr class="separator:gadba142ee49ae8f52f76b603c926ad711"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga1664e9fc682c3ace4b721906d6ce2b3d"><td class="memItemLeft" align="right" valign="top"><a class="el" href="irq__ctrl_8h.html#ac62964c04a7fed2c84aeea9e34f415e2">IRQn_ID_t</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="group__irq__ctrl__gr.html#ga1664e9fc682c3ace4b721906d6ce2b3d">IRQ_GetActiveIRQ</a> (void)</td></tr>
<tr class="memdesc:ga1664e9fc682c3ace4b721906d6ce2b3d"><td class="mdescLeft"> </td><td class="mdescRight">Get ID number of current interrupt request (IRQ). <a href="#ga1664e9fc682c3ace4b721906d6ce2b3d">More...</a><br/></td></tr>
<tr class="separator:ga1664e9fc682c3ace4b721906d6ce2b3d"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga1376a5cf6ff38344a9bbbae080af5a0f"><td class="memItemLeft" align="right" valign="top"><a class="el" href="irq__ctrl_8h.html#ac62964c04a7fed2c84aeea9e34f415e2">IRQn_ID_t</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="group__irq__ctrl__gr.html#ga1376a5cf6ff38344a9bbbae080af5a0f">IRQ_GetActiveFIQ</a> (void)</td></tr>
<tr class="memdesc:ga1376a5cf6ff38344a9bbbae080af5a0f"><td class="mdescLeft"> </td><td class="mdescRight">Get ID number of current fast interrupt request (FIQ). <a href="#ga1376a5cf6ff38344a9bbbae080af5a0f">More...</a><br/></td></tr>
<tr class="separator:ga1376a5cf6ff38344a9bbbae080af5a0f"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga55638c35efdc7a197b51165929ef0c10"><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__irq__ctrl__gr.html#ga55638c35efdc7a197b51165929ef0c10">IRQ_EndOfInterrupt</a> (<a class="el" href="irq__ctrl_8h.html#ac62964c04a7fed2c84aeea9e34f415e2">IRQn_ID_t</a> irqn)</td></tr>
<tr class="memdesc:ga55638c35efdc7a197b51165929ef0c10"><td class="mdescLeft"> </td><td class="mdescRight">Signal end of interrupt processing. <a href="#ga55638c35efdc7a197b51165929ef0c10">More...</a><br/></td></tr>
<tr class="separator:ga55638c35efdc7a197b51165929ef0c10"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga88aedf1dee1061783e6c05c535e7b6c4"><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__irq__ctrl__gr.html#ga88aedf1dee1061783e6c05c535e7b6c4">IRQ_SetPending</a> (<a class="el" href="irq__ctrl_8h.html#ac62964c04a7fed2c84aeea9e34f415e2">IRQn_ID_t</a> irqn)</td></tr>
<tr class="memdesc:ga88aedf1dee1061783e6c05c535e7b6c4"><td class="mdescLeft"> </td><td class="mdescRight">Set interrupt pending flag. <a href="#ga88aedf1dee1061783e6c05c535e7b6c4">More...</a><br/></td></tr>
<tr class="separator:ga88aedf1dee1061783e6c05c535e7b6c4"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gaa399f9169f136b3930f0d50247aa22fc"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__irq__ctrl__gr.html#gaa399f9169f136b3930f0d50247aa22fc">IRQ_GetPending</a> (<a class="el" href="irq__ctrl_8h.html#ac62964c04a7fed2c84aeea9e34f415e2">IRQn_ID_t</a> irqn)</td></tr>
<tr class="memdesc:gaa399f9169f136b3930f0d50247aa22fc"><td class="mdescLeft"> </td><td class="mdescRight">Get interrupt pending flag. <a href="#gaa399f9169f136b3930f0d50247aa22fc">More...</a><br/></td></tr>
<tr class="separator:gaa399f9169f136b3930f0d50247aa22fc"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gaad6b03f73b3d3ea2ccbb122484e8bd36"><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__irq__ctrl__gr.html#gaad6b03f73b3d3ea2ccbb122484e8bd36">IRQ_ClearPending</a> (<a class="el" href="irq__ctrl_8h.html#ac62964c04a7fed2c84aeea9e34f415e2">IRQn_ID_t</a> irqn)</td></tr>
<tr class="memdesc:gaad6b03f73b3d3ea2ccbb122484e8bd36"><td class="mdescLeft"> </td><td class="mdescRight">Clear interrupt pending flag. <a href="#gaad6b03f73b3d3ea2ccbb122484e8bd36">More...</a><br/></td></tr>
<tr class="separator:gaad6b03f73b3d3ea2ccbb122484e8bd36"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gaa90aed20ac94420fff4bbbf55c12d4c2"><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__irq__ctrl__gr.html#gaa90aed20ac94420fff4bbbf55c12d4c2">IRQ_SetPriority</a> (<a class="el" href="irq__ctrl_8h.html#ac62964c04a7fed2c84aeea9e34f415e2">IRQn_ID_t</a> irqn, uint32_t priority)</td></tr>
<tr class="memdesc:gaa90aed20ac94420fff4bbbf55c12d4c2"><td class="mdescLeft"> </td><td class="mdescRight">Set interrupt priority value. <a href="#gaa90aed20ac94420fff4bbbf55c12d4c2">More...</a><br/></td></tr>
<tr class="separator:gaa90aed20ac94420fff4bbbf55c12d4c2"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga0a6a18c8fa2bc3183598439b56c507c3"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__irq__ctrl__gr.html#ga0a6a18c8fa2bc3183598439b56c507c3">IRQ_GetPriority</a> (<a class="el" href="irq__ctrl_8h.html#ac62964c04a7fed2c84aeea9e34f415e2">IRQn_ID_t</a> irqn)</td></tr>
<tr class="memdesc:ga0a6a18c8fa2bc3183598439b56c507c3"><td class="mdescLeft"> </td><td class="mdescRight">Get interrupt priority. <a href="#ga0a6a18c8fa2bc3183598439b56c507c3">More...</a><br/></td></tr>
<tr class="separator:ga0a6a18c8fa2bc3183598439b56c507c3"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga3a79888f72bd1db45f0b9a59dbaa2337"><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__irq__ctrl__gr.html#ga3a79888f72bd1db45f0b9a59dbaa2337">IRQ_SetPriorityMask</a> (uint32_t priority)</td></tr>
<tr class="memdesc:ga3a79888f72bd1db45f0b9a59dbaa2337"><td class="mdescLeft"> </td><td class="mdescRight">Set priority masking threshold. <a href="#ga3a79888f72bd1db45f0b9a59dbaa2337">More...</a><br/></td></tr>
<tr class="separator:ga3a79888f72bd1db45f0b9a59dbaa2337"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga77632ae73f1ba46c4a9a0c12e6bc4869"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__irq__ctrl__gr.html#ga77632ae73f1ba46c4a9a0c12e6bc4869">IRQ_GetPriorityMask</a> (void)</td></tr>
<tr class="memdesc:ga77632ae73f1ba46c4a9a0c12e6bc4869"><td class="mdescLeft"> </td><td class="mdescRight">Get priority masking threshold. <a href="#ga77632ae73f1ba46c4a9a0c12e6bc4869">More...</a><br/></td></tr>
<tr class="separator:ga77632ae73f1ba46c4a9a0c12e6bc4869"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gabaa4074988ea9e30523f7ed5a86953c2"><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__irq__ctrl__gr.html#gabaa4074988ea9e30523f7ed5a86953c2">IRQ_SetPriorityGroupBits</a> (uint32_t bits)</td></tr>
<tr class="memdesc:gabaa4074988ea9e30523f7ed5a86953c2"><td class="mdescLeft"> </td><td class="mdescRight">Set priority grouping field split point. <a href="#gabaa4074988ea9e30523f7ed5a86953c2">More...</a><br/></td></tr>
<tr class="separator:gabaa4074988ea9e30523f7ed5a86953c2"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga061da812739bdba1e32765ed6501b83c"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__irq__ctrl__gr.html#ga061da812739bdba1e32765ed6501b83c">IRQ_GetPriorityGroupBits</a> (void)</td></tr>
<tr class="memdesc:ga061da812739bdba1e32765ed6501b83c"><td class="mdescLeft"> </td><td class="mdescRight">Get priority grouping field split point. <a href="#ga061da812739bdba1e32765ed6501b83c">More...</a><br/></td></tr>
<tr class="separator:ga061da812739bdba1e32765ed6501b83c"><td class="memSeparator" colspan="2"> </td></tr>
</table>
<a name="details" id="details"></a><h2 class="groupheader">Description</h2>
<p>This section describes the device agnostic interrupt API viable for a wide range of specific interrupt controllers. The IRQ Controller API allows interrupt dependend applications to be easily portable across a wide range of controllers.</p>
<dl class="section note"><dt>Note</dt><dd>The default implementation for <a class="el" href="group__GIC__functions.html">Arm GIC (Generic Interrupt Controller)</a> can be found in <a class="el" href="irq__ctrl__gic_8c.html">irq_ctrl_gic.c</a>. It uses <code>weak</code> functions thus it can easily be overwritten by an alternative user implementation if needed.</dd></dl>
<p>The Armv7-A architecture defines a common set of first level exceptions, see table below.</p>
<table class="doxtable">
<tr>
<th>Exception </th><th>CMSIS Handler </th><th>Offset </th><th>Description </th></tr>
<tr>
<td>Reset </td><td>Reset_Handler </td><td>0x0000 </td><td>First instruction executed after reset. </td></tr>
<tr>
<td>Undefined Instruction (Undef) </td><td>Undef_Handler </td><td>0x0004 </td><td>Signals usage of an illegal instructions. </td></tr>
<tr>
<td>Supervisor Call (SVC) </td><td>SVC_Handler </td><td>0x0008 </td><td>Issued by software using SVC instruction. </td></tr>
<tr>
<td>Prefetch Abort (PAbt) </td><td>PAbt_Handler </td><td>0x000C </td><td>Signals a memory abort on istruction fetch. </td></tr>
<tr>
<td>Data Abort (DAbt) </td><td>DAbt_Handler </td><td>0x0010 </td><td>Signals a memory abort on data read or write. </td></tr>
<tr>
<td>Hyp Trap </td><td>(NOP) </td><td>0x0014 </td><td>Hypervisor instruction trap, only available with Virtualization Extensions. </td></tr>
<tr>
<td>IRQ interrupt </td><td>IRQ_Handler </td><td>0x0018 </td><td>Interrupt Request (typically from Interrupt Controller) </td></tr>
<tr>
<td>FIQ interrupt </td><td>FIQ_Handler </td><td>0x001C </td><td>Fast Interrupt Request (typically from Interrupt Controller) </td></tr>
</table>
<p>By default those handlers are defined as weak empty functions by the <a class="el" href="startup_c_pg.html#startup_c_sec">device specific startup code</a>. Software and peripheral interrupts are all handled by one of the both central interrupt handlers (IRQ and FIQ). These needs to be implemented application specific. If an RTOS is used the interrupt handlers are typically provided by the RTOS, e.g. when using <a href="../../RTOS2/html/rtx5_impl.html">RTX5</a>.</p>
<p>The interrupts available depends on the actual device in use. According to CMSIS specification the interrupts are defined as <a class="el" href="ARMCA9_8h.html#a7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> in <a class="el" href="device_h_pg.html">Device Header File <device.h></a>. Using the generic IRQ API one can easily enable and disable interrupts, set up priorities, modes and preemption rules, and register interrupt callbacks.</p>
<p><b>Example:</b> </p>
<div class="fragment"><div class="line"><span class="keywordtype">void</span> SGI0_Handler() {</div>
<div class="line"> <span class="comment">/* </span></div>
<div class="line"><span class="comment"> * Handle Interrupt </span></div>
<div class="line"><span class="comment"> */</span></div>
<div class="line"> </div>
<div class="line"> <a class="code" href="group__irq__ctrl__gr.html#gaad6b03f73b3d3ea2ccbb122484e8bd36">IRQ_ClearPending</a>((<a class="code" href="irq__ctrl_8h.html#ac62964c04a7fed2c84aeea9e34f415e2">IRQn_ID_t</a>)<a class="code" href="ARMCA9_8h.html#a7e1129cd8a196f4284d41db3e82ad5c8a056f32088a9c8bdb9309b005dfeb648e">SGI0_IRQn</a>);</div>
<div class="line">}</div>
<div class="line"> </div>
<div class="line"><span class="keywordtype">void</span> main() {</div>
<div class="line"> <span class="comment">/* Initialize the Interrupt Controller */</span></div>
<div class="line"> <a class="code" href="group__irq__ctrl__gr.html#ga03ea5d5d67a89acff8a5b02286795a99">IRQ_Initialize</a>();</div>
<div class="line"> </div>
<div class="line"> <span class="comment">/* Register the user defined handler function */</span></div>
<div class="line"> <a class="code" href="group__irq__ctrl__gr.html#gac1fcc16fb8e488d315cfa496f1d71db3">IRQ_SetHandler</a>((<a class="code" href="irq__ctrl_8h.html#ac62964c04a7fed2c84aeea9e34f415e2">IRQn_ID_t</a>)<a class="code" href="ARMCA9_8h.html#a7e1129cd8a196f4284d41db3e82ad5c8a056f32088a9c8bdb9309b005dfeb648e">SGI0_IRQn</a>, SGI0_Handler); </div>
<div class="line"> </div>
<div class="line"> <span class="comment">/* Set the priority considering the priority grouping */</span></div>
<div class="line"> <span class="keyword">const</span> uint32_t subprio = <a class="code" href="group__irq__ctrl__gr.html#ga061da812739bdba1e32765ed6501b83c">IRQ_GetPriorityGroupBits</a>();</div>
<div class="line"> <a class="code" href="group__irq__ctrl__gr.html#gaa90aed20ac94420fff4bbbf55c12d4c2">IRQ_SetPriority</a>((<a class="code" href="irq__ctrl_8h.html#ac62964c04a7fed2c84aeea9e34f415e2">IRQn_ID_t</a>)<a class="code" href="ARMCA9_8h.html#a7e1129cd8a196f4284d41db3e82ad5c8a056f32088a9c8bdb9309b005dfeb648e">SGI0_IRQn</a>, 1u << subprio);</div>
<div class="line"> </div>
<div class="line"> <span class="comment">/* Set interrupt mode to falling edge */</span></div>
<div class="line"> <a class="code" href="group__irq__ctrl__gr.html#gab35da69354d2e515931580a1308a3a85">IRQ_SetMode</a>((<a class="code" href="irq__ctrl_8h.html#ac62964c04a7fed2c84aeea9e34f415e2">IRQn_ID_t</a>)<a class="code" href="ARMCA9_8h.html#a7e1129cd8a196f4284d41db3e82ad5c8a056f32088a9c8bdb9309b005dfeb648e">SGI0_IRQn</a>, <a class="code" href="group__irq__mode__defs.html#gab0d022bbd15beb1a6578b5535d95f9cf">IRQ_MODE_TYPE_IRQ</a> | <a class="code" href="group__irq__mode__defs.html#gacb276aa0488a9bf1aa56e1072d2a15a5">IRQ_MODE_CPU_0</a> | <a class="code" href="group__irq__mode__defs.html#gaa9a8e0968a4ccd57eb7544a16d05f24d">IRQ_MODE_TRIG_EDGE</a> | <a class="code" href="group__irq__mode__defs.html#ga99e0f3f6945991d50e766b19e71e0222">IRQ_MODE_TRIG_EDGE_FALLING</a>);</div>
<div class="line"> </div>
<div class="line"> <a class="code" href="group__irq__ctrl__gr.html#ga4ad780a3dc23a1b6222de8adcd7c20a7">IRQ_Enable</a>((<a class="code" href="irq__ctrl_8h.html#ac62964c04a7fed2c84aeea9e34f415e2">IRQn_ID_t</a>)<a class="code" href="ARMCA9_8h.html#a7e1129cd8a196f4284d41db3e82ad5c8a056f32088a9c8bdb9309b005dfeb648e">SGI0_IRQn</a>);</div>
<div class="line"> </div>
<div class="line"> <span class="comment">/* Trigger interrupt */</span></div>
<div class="line"> <a class="code" href="group__irq__ctrl__gr.html#ga88aedf1dee1061783e6c05c535e7b6c4">IRQ_SetPending</a>((<a class="code" href="irq__ctrl_8h.html#ac62964c04a7fed2c84aeea9e34f415e2">IRQn_ID_t</a>)<a class="code" href="ARMCA9_8h.html#a7e1129cd8a196f4284d41db3e82ad5c8a056f32088a9c8bdb9309b005dfeb648e">SGI0_IRQn</a>);</div>
<div class="line"> </div>
<div class="line"> <a class="code" href="group__irq__ctrl__gr.html#ga544cf4ae0159cc17e259d55898528248">IRQ_Disable</a>((<a class="code" href="irq__ctrl_8h.html#ac62964c04a7fed2c84aeea9e34f415e2">IRQn_ID_t</a>)<a class="code" href="ARMCA9_8h.html#a7e1129cd8a196f4284d41db3e82ad5c8a056f32088a9c8bdb9309b005dfeb648e">SGI0_IRQn</a>);</div>
<div class="line">}</div>
</div><!-- fragment --> <h2 class="groupheader">Function Documentation</h2>
<a class="anchor" id="gaad6b03f73b3d3ea2ccbb122484e8bd36"></a>
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname">int32_t IRQ_ClearPending </td>
<td>(</td>
<td class="paramtype"><a class="el" href="irq__ctrl_8h.html#ac62964c04a7fed2c84aeea9e34f415e2">IRQn_ID_t</a> </td>
<td class="paramname"><em>irqn</em></td><td>)</td>
<td></td>
</tr>
</table>
</div><div class="memdoc">
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramdir">[in]</td><td class="paramname">irqn</td><td>interrupt ID number </td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>0 on success, -1 on error.</dd></dl>
<p>This function clears the pending status of the interrupt identified by the irqn parameter.</p>
<p>For Arm GIC the default implementation looks like the following example:</p>
<div class="fragment"><div class="line">int32_t <a class="code" href="group__irq__ctrl__gr.html#gaad6b03f73b3d3ea2ccbb122484e8bd36">IRQ_ClearPending</a> (<a class="code" href="irq__ctrl_8h.html#ac62964c04a7fed2c84aeea9e34f415e2">IRQn_ID_t</a> irqn) {</div>
<div class="line"> int32_t status;</div>
<div class="line"> </div>
<div class="line"> <span class="keywordflow">if</span> ((irqn >= 16) && (irqn < IRQ_GIC_LINE_COUNT)) {</div>
<div class="line"> <a class="code" href="group__GIC__functions.html#ga5ad17ad70f23d1ff36015ffac33d383d">GIC_ClearPendingIRQ</a> ((<a class="code" href="ARMCA9_8h.html#a7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a>)irqn);</div>
<div class="line"> status = 0;</div>
<div class="line"> } <span class="keywordflow">else</span> {</div>
<div class="line"> status = -1;</div>
<div class="line"> }</div>
<div class="line"> </div>
<div class="line"> <span class="keywordflow">return</span> (status);</div>
<div class="line">}</div>
</div><!-- fragment -->
</div>
</div>
<a class="anchor" id="ga544cf4ae0159cc17e259d55898528248"></a>
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname">int32_t IRQ_Disable </td>
<td>(</td>
<td class="paramtype"><a class="el" href="irq__ctrl_8h.html#ac62964c04a7fed2c84aeea9e34f415e2">IRQn_ID_t</a> </td>
<td class="paramname"><em>irqn</em></td><td>)</td>
<td></td>
</tr>
</table>
</div><div class="memdoc">
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramdir">[in]</td><td class="paramname">irqn</td><td>interrupt ID number </td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>0 on success, -1 on error.</dd></dl>
<p>This function disables forwarding of the corresponding interrupt to the CPU.</p>
<p>For Arm GIC the default implementation looks like the following example:</p>
<div class="fragment"><div class="line">int32_t <a class="code" href="group__irq__ctrl__gr.html#ga544cf4ae0159cc17e259d55898528248">IRQ_Disable</a> (<a class="code" href="irq__ctrl_8h.html#ac62964c04a7fed2c84aeea9e34f415e2">IRQn_ID_t</a> irqn) {</div>
<div class="line"> int32_t status;</div>
<div class="line"> </div>
<div class="line"> <span class="keywordflow">if</span> ((irqn >= 0) && (irqn < IRQ_GIC_LINE_COUNT)) {</div>
<div class="line"> <a class="code" href="group__GIC__functions.html#ga2102399d255690c0674209a6faeec13d">GIC_DisableIRQ</a> ((<a class="code" href="ARMCA9_8h.html#a7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a>)irqn);</div>
<div class="line"> status = 0;</div>
<div class="line"> } <span class="keywordflow">else</span> {</div>
<div class="line"> status = -1;</div>
<div class="line"> }</div>
<div class="line"> </div>
<div class="line"> <span class="keywordflow">return</span> (status);</div>
<div class="line">}</div>
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<td class="memname">int32_t IRQ_Enable </td>
<td>(</td>
<td class="paramtype"><a class="el" href="irq__ctrl_8h.html#ac62964c04a7fed2c84aeea9e34f415e2">IRQn_ID_t</a> </td>
<td class="paramname"><em>irqn</em></td><td>)</td>
<td></td>
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<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramdir">[in]</td><td class="paramname">irqn</td><td>interrupt ID number </td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>0 on success, -1 on error.</dd></dl>
<p>This function enables forwarding of the corresponding interrupt to the CPU.</p>
<p>For Arm GIC the default implementation looks like the following example:</p>
<div class="fragment"><div class="line">int32_t <a class="code" href="group__irq__ctrl__gr.html#ga4ad780a3dc23a1b6222de8adcd7c20a7">IRQ_Enable</a> (<a class="code" href="irq__ctrl_8h.html#ac62964c04a7fed2c84aeea9e34f415e2">IRQn_ID_t</a> irqn) {</div>
<div class="line"> int32_t status;</div>
<div class="line"> </div>
<div class="line"> <span class="keywordflow">if</span> ((irqn >= 0) && (irqn < IRQ_GIC_LINE_COUNT)) {</div>
<div class="line"> <a class="code" href="group__GIC__functions.html#gaeba215d9c4ec3599e0a168800288c3f3">GIC_EnableIRQ</a> ((<a class="code" href="ARMCA9_8h.html#a7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a>)irqn);</div>
<div class="line"> status = 0;</div>
<div class="line"> } <span class="keywordflow">else</span> {</div>
<div class="line"> status = -1;</div>
<div class="line"> }</div>
<div class="line"> </div>
<div class="line"> <span class="keywordflow">return</span> (status);</div>
<div class="line">}</div>
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<td class="memname">int32_t IRQ_EndOfInterrupt </td>
<td>(</td>
<td class="paramtype"><a class="el" href="irq__ctrl_8h.html#ac62964c04a7fed2c84aeea9e34f415e2">IRQn_ID_t</a> </td>
<td class="paramname"><em>irqn</em></td><td>)</td>
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</div><div class="memdoc">
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramdir">[in]</td><td class="paramname">irqn</td><td>interrupt ID number </td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>0 on success, -1 on error.</dd></dl>
<p>This function informs the interrupt controller that the interrupt service routine processing of the currently active interrupt request is completed.</p>
<p>The parameter irqn should specify the value previously returned by the <a class="el" href="group__irq__ctrl__gr.html#ga1664e9fc682c3ace4b721906d6ce2b3d">IRQ_GetActiveIRQ</a> or <a class="el" href="group__irq__ctrl__gr.html#ga1376a5cf6ff38344a9bbbae080af5a0f">IRQ_GetActiveFIQ</a> functions.</p>
<p>For Arm GIC the default implementation looks like the following example:</p>
<div class="fragment"><div class="line">int32_t <a class="code" href="group__irq__ctrl__gr.html#ga55638c35efdc7a197b51165929ef0c10">IRQ_EndOfInterrupt</a> (<a class="code" href="irq__ctrl_8h.html#ac62964c04a7fed2c84aeea9e34f415e2">IRQn_ID_t</a> irqn) {</div>
<div class="line"> int32_t status;</div>
<div class="line"> </div>
<div class="line"> <span class="keywordflow">if</span> ((irqn >= 0) && (irqn < IRQ_GIC_LINE_COUNT)) {</div>
<div class="line"> <a class="code" href="group__GIC__functions.html#gac23f090f572a058b4a737f6613ded9cd">GIC_EndInterrupt</a> ((<a class="code" href="ARMCA9_8h.html#a7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a>)irqn);</div>
<div class="line"> </div>
<div class="line"> <span class="keywordflow">if</span> (irqn == 0) {</div>
<div class="line"> IRQ_ID0 = 0U;</div>
<div class="line"> }</div>
<div class="line"> </div>
<div class="line"> status = 0;</div>
<div class="line"> } <span class="keywordflow">else</span> {</div>
<div class="line"> status = -1;</div>
<div class="line"> }</div>
<div class="line"> </div>
<div class="line"> <span class="keywordflow">return</span> (status);</div>
<div class="line">}</div>
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<td class="memname"><a class="el" href="irq__ctrl_8h.html#ac62964c04a7fed2c84aeea9e34f415e2">IRQn_ID_t</a> IRQ_GetActiveFIQ </td>
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<td class="paramtype">void </td>
<td class="paramname"></td><td>)</td>
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<dl class="section return"><dt>Returns</dt><dd>interrupt ID number.</dd></dl>
<p>This function retrieves the interrupt ID number of current FIQ source and acknowledges the interrupt.</p>
<p>For Arm GIC the default implementation looks like the following example:</p>
<div class="fragment"><div class="line"><a class="code" href="irq__ctrl_8h.html#ac62964c04a7fed2c84aeea9e34f415e2">IRQn_ID_t</a> <a class="code" href="group__irq__ctrl__gr.html#ga1376a5cf6ff38344a9bbbae080af5a0f">IRQ_GetActiveFIQ</a> (<span class="keywordtype">void</span>) {</div>
<div class="line"> <span class="comment">// FIQ is not supported, return invalid ID</span></div>
<div class="line"> <span class="keywordflow">return</span> ((<a class="code" href="irq__ctrl_8h.html#ac62964c04a7fed2c84aeea9e34f415e2">IRQn_ID_t</a>)-1);</div>
<div class="line">}</div>
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<td class="memname"><a class="el" href="irq__ctrl_8h.html#ac62964c04a7fed2c84aeea9e34f415e2">IRQn_ID_t</a> IRQ_GetActiveIRQ </td>
<td>(</td>
<td class="paramtype">void </td>
<td class="paramname"></td><td>)</td>
<td></td>
</tr>
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<dl class="section return"><dt>Returns</dt><dd>interrupt ID number.</dd></dl>
<p>This function retrieves the interrupt ID number of current IRQ source and acknowledges the interrupt.</p>
<p>For Arm GIC the default implementation looks like the following example:</p>
<div class="fragment"><div class="line"><a class="code" href="irq__ctrl_8h.html#ac62964c04a7fed2c84aeea9e34f415e2">IRQn_ID_t</a> <a class="code" href="group__irq__ctrl__gr.html#ga1664e9fc682c3ace4b721906d6ce2b3d">IRQ_GetActiveIRQ</a> (<span class="keywordtype">void</span>) {</div>
<div class="line"> <a class="code" href="irq__ctrl_8h.html#ac62964c04a7fed2c84aeea9e34f415e2">IRQn_ID_t</a> irqn;</div>
<div class="line"> </div>
<div class="line"> irqn = (<a class="code" href="irq__ctrl_8h.html#ac62964c04a7fed2c84aeea9e34f415e2">IRQn_ID_t</a>)<a class="code" href="group__GIC__functions.html#gafc08bbc58b25fef0d24003313fd16eb8">GIC_AcknowledgePending</a>();</div>
<div class="line"> </div>
<div class="line"> <span class="keywordflow">return</span> (irqn);</div>
<div class="line">}</div>
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<td class="memname">uint32_t IRQ_GetEnableState </td>
<td>(</td>
<td class="paramtype"><a class="el" href="irq__ctrl_8h.html#ac62964c04a7fed2c84aeea9e34f415e2">IRQn_ID_t</a> </td>
<td class="paramname"><em>irqn</em></td><td>)</td>
<td></td>
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</div><div class="memdoc">
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramdir">[in]</td><td class="paramname">irqn</td><td>interrupt ID number </td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>0 - interrupt is disabled, 1 - interrupt is enabled.</dd></dl>
<p>This function retrieves the interrupt enable status of the interrupt identified by the irqn parameter.</p>
<p>Interrupt enable status can be either disabled (0) or enabled (1). Disabled status is returned for interrupts which cannot be identified by irqn.</p>
<p>For Arm GIC the default implementation looks like the following example:</p>
<div class="fragment"><div class="line">uint32_t <a class="code" href="group__irq__ctrl__gr.html#ga8913613a9075a35410af0eb7b275d9e2">IRQ_GetEnableState</a> (<a class="code" href="irq__ctrl_8h.html#ac62964c04a7fed2c84aeea9e34f415e2">IRQn_ID_t</a> irqn) {</div>
<div class="line"> uint32_t enable;</div>
<div class="line"> </div>
<div class="line"> <span class="keywordflow">if</span> ((irqn >= 0) && (irqn < IRQ_GIC_LINE_COUNT)) {</div>
<div class="line"> enable = <a class="code" href="core__ca_8h.html#abcd7d576ea634b1a708db9fda95d09df">GIC_GetEnableIRQ</a>((<a class="code" href="ARMCA9_8h.html#a7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a>)irqn);</div>
<div class="line"> } <span class="keywordflow">else</span> {</div>
<div class="line"> enable = 0U;</div>
<div class="line"> }</div>
<div class="line"> </div>
<div class="line"> <span class="keywordflow">return</span> (enable);</div>
<div class="line">}</div>
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<td class="memname"><a class="el" href="irq__ctrl_8h.html#afbfa2180a9b6208f34891d539e9e2d52">IRQHandler_t</a> IRQ_GetHandler </td>
<td>(</td>
<td class="paramtype"><a class="el" href="irq__ctrl_8h.html#ac62964c04a7fed2c84aeea9e34f415e2">IRQn_ID_t</a> </td>
<td class="paramname"><em>irqn</em></td><td>)</td>
<td></td>
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</table>
</div><div class="memdoc">
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramdir">[in]</td><td class="paramname">irqn</td><td>interrupt ID number </td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>registered interrupt handler function address.</dd></dl>
<p>This function retrieves address of the interrupt handler callback function corresponding to the specified interrupt ID number.</p>
<p>For Arm GIC the default implementation looks like the following example:</p>
<div class="fragment"><div class="line"><a class="code" href="irq__ctrl_8h.html#afbfa2180a9b6208f34891d539e9e2d52">IRQHandler_t</a> <a class="code" href="group__irq__ctrl__gr.html#gaa2a2df8fbc7bad465ada49bd690f65d5">IRQ_GetHandler</a> (<a class="code" href="irq__ctrl_8h.html#ac62964c04a7fed2c84aeea9e34f415e2">IRQn_ID_t</a> irqn) {</div>
<div class="line"> IRQHandler h;</div>
<div class="line"> </div>
<div class="line"> <span class="keywordflow">if</span> ((irqn >= 0) && (irqn < IRQ_GIC_LINE_COUNT)) {</div>
<div class="line"> h = IRQTable[irqn];</div>
<div class="line"> } <span class="keywordflow">else</span> {</div>
<div class="line"> h = (<a class="code" href="irq__ctrl_8h.html#afbfa2180a9b6208f34891d539e9e2d52">IRQHandler_t</a>)0;</div>
<div class="line"> }</div>
<div class="line"> </div>
<div class="line"> <span class="keywordflow">return</span> (h);</div>
<div class="line">}</div>
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<td class="memname">uint32_t IRQ_GetMode </td>
<td>(</td>
<td class="paramtype"><a class="el" href="irq__ctrl_8h.html#ac62964c04a7fed2c84aeea9e34f415e2">IRQn_ID_t</a> </td>
<td class="paramname"><em>irqn</em></td><td>)</td>
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<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramdir">[in]</td><td class="paramname">irqn</td><td>interrupt ID number </td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>current interrupt mode configuration with optional IRQ_MODE_ERROR bit set.</dd></dl>
<p>This function retrieves interrupt mode configuration of the interrupt identified by the irqn parameter. <a class="el" href="group__irq__mode__defs.html#gaacb93ae158e548c54698a7230647804a">IRQ_MODE_ERROR</a> is returned for interrupts which cannot be identified by irqn.</p>
<p>For Arm GIC the default implementation looks like the following example:</p>
<div class="fragment"><div class="line">uint32_t <a class="code" href="group__irq__ctrl__gr.html#gadba142ee49ae8f52f76b603c926ad711">IRQ_GetMode</a> (<a class="code" href="irq__ctrl_8h.html#ac62964c04a7fed2c84aeea9e34f415e2">IRQn_ID_t</a> irqn) {</div>
<div class="line"> uint32_t mode;</div>
<div class="line"> uint32_t val;</div>
<div class="line"> </div>
<div class="line"> <span class="keywordflow">if</span> ((irqn >= 0) && (irqn < IRQ_GIC_LINE_COUNT)) {</div>
<div class="line"> mode = <a class="code" href="group__irq__mode__defs.html#gab0d022bbd15beb1a6578b5535d95f9cf">IRQ_MODE_TYPE_IRQ</a>;</div>
<div class="line"> </div>
<div class="line"> <span class="comment">// Get trigger mode</span></div>
<div class="line"> val = <a class="code" href="core__ca_8h.html#a43cfac7327b49e2a89d63abc99b6b06a">GIC_GetConfiguration</a>((<a class="code" href="ARMCA9_8h.html#a7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a>)irqn);</div>
<div class="line"> </div>
<div class="line"> <span class="keywordflow">if</span> ((val & 2U) != 0U) {</div>
<div class="line"> <span class="comment">// Corresponding interrupt is edge triggered</span></div>
<div class="line"> mode |= <a class="code" href="group__irq__mode__defs.html#gaa9a8e0968a4ccd57eb7544a16d05f24d">IRQ_MODE_TRIG_EDGE</a>;</div>
<div class="line"> } <span class="keywordflow">else</span> {</div>
<div class="line"> <span class="comment">// Corresponding interrupt is level triggered</span></div>
<div class="line"> mode |= <a class="code" href="group__irq__mode__defs.html#gabc31ba71612436a6ccc49342f35fec58">IRQ_MODE_TRIG_LEVEL</a>;</div>
<div class="line"> }</div>
<div class="line"> </div>
<div class="line"> <span class="comment">// Get interrupt CPU targets</span></div>
<div class="line"> mode |= <a class="code" href="group__GIC__functions.html#gafccf881f9517592f30489bcabcb738a8">GIC_GetTarget</a> ((<a class="code" href="ARMCA9_8h.html#a7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a>)irqn) << <a class="code" href="irq__ctrl_8h.html#ab7527409c193021e65aaf4d519caea46">IRQ_MODE_CPU_Pos</a>;</div>
<div class="line"> </div>
<div class="line"> } <span class="keywordflow">else</span> {</div>
<div class="line"> mode = <a class="code" href="group__irq__mode__defs.html#gaacb93ae158e548c54698a7230647804a">IRQ_MODE_ERROR</a>;</div>
<div class="line"> }</div>
<div class="line"> </div>
<div class="line"> <span class="keywordflow">return</span> (mode);</div>
<div class="line">}</div>
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<td class="memname">uint32_t IRQ_GetPending </td>
<td>(</td>
<td class="paramtype"><a class="el" href="irq__ctrl_8h.html#ac62964c04a7fed2c84aeea9e34f415e2">IRQn_ID_t</a> </td>
<td class="paramname"><em>irqn</em></td><td>)</td>
<td></td>
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<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramdir">[in]</td><td class="paramname">irqn</td><td>interrupt ID number </td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>0 - interrupt is not pending, 1 - interrupt is pending.</dd></dl>
<p>This function retrieves the pending status of the interrupt identified by the irqn parameter.</p>
<p>Interrupt pending status can be either not pending (0) or pending (1). Not pending status is returned for interrupts which cannot be identified by irqn.</p>
<p>For Arm GIC the default implementation looks like the following example:</p>
<div class="fragment"><div class="line">uint32_t <a class="code" href="group__irq__ctrl__gr.html#gaa399f9169f136b3930f0d50247aa22fc">IRQ_GetPending</a> (<a class="code" href="irq__ctrl_8h.html#ac62964c04a7fed2c84aeea9e34f415e2">IRQn_ID_t</a> irqn) {</div>
<div class="line"> uint32_t pending;</div>
<div class="line"> </div>
<div class="line"> <span class="keywordflow">if</span> ((irqn >= 16) && (irqn < IRQ_GIC_LINE_COUNT)) {</div>
<div class="line"> pending = <a class="code" href="core__ca_8h.html#ab726a01df6ee9a480cc73910a06ddfb7">GIC_GetPendingIRQ</a> ((<a class="code" href="ARMCA9_8h.html#a7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a>)irqn);</div>
<div class="line"> } <span class="keywordflow">else</span> {</div>
<div class="line"> pending = 0U;</div>
<div class="line"> }</div>
<div class="line"> </div>
<div class="line"> <span class="keywordflow">return</span> (pending & 1U);</div>
<div class="line">}</div>
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<td class="memname">uint32_t IRQ_GetPriority </td>
<td>(</td>
<td class="paramtype"><a class="el" href="irq__ctrl_8h.html#ac62964c04a7fed2c84aeea9e34f415e2">IRQn_ID_t</a> </td>
<td class="paramname"><em>irqn</em></td><td>)</td>
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<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramdir">[in]</td><td class="paramname">irqn</td><td>interrupt ID number </td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>current interrupt priority value with optional IRQ_PRIORITY_ERROR bit set.</dd></dl>
<p>This function retrieves the priority of the interrupt identified by the irqn parameter.</p>
<p>The valid priority value can be from zero (0) to the value of <a class="el" href="group__irq__priority__defs.html#gabaa4e91ab84dbe5f669080af6d0d81fa">IRQ_PRIORITY_Msk</a>. <a class="el" href="group__irq__priority__defs.html#ga47b19866dc05c58c6923c313b371f881">IRQ_PRIORITY_ERROR</a> bit is set in returned value for interrupts which cannot be identified by irqn.</p>
<p>For Arm GIC the default implementation looks like the following example:</p>
<div class="fragment"><div class="line">uint32_t <a class="code" href="group__irq__ctrl__gr.html#ga0a6a18c8fa2bc3183598439b56c507c3">IRQ_GetPriority</a> (<a class="code" href="irq__ctrl_8h.html#ac62964c04a7fed2c84aeea9e34f415e2">IRQn_ID_t</a> irqn) {</div>
<div class="line"> uint32_t priority;</div>
<div class="line"> </div>
<div class="line"> <span class="keywordflow">if</span> ((irqn >= 0) && (irqn < IRQ_GIC_LINE_COUNT)) {</div>
<div class="line"> priority = <a class="code" href="group__GIC__functions.html#ga397048004654f792649742f95bf8ae67">GIC_GetPriority</a> ((<a class="code" href="ARMCA9_8h.html#a7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a>)irqn);</div>
<div class="line"> } <span class="keywordflow">else</span> {</div>
<div class="line"> priority = <a class="code" href="group__irq__priority__defs.html#ga47b19866dc05c58c6923c313b371f881">IRQ_PRIORITY_ERROR</a>;</div>
<div class="line"> }</div>
<div class="line"> </div>
<div class="line"> <span class="keywordflow">return</span> (priority);</div>
<div class="line">}</div>
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<td class="memname">uint32_t IRQ_GetPriorityGroupBits </td>
<td>(</td>
<td class="paramtype">void </td>
<td class="paramname"></td><td>)</td>
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<dl class="section return"><dt>Returns</dt><dd>current number of MSB bits included in the group priority field comparison with optional IRQ_PRIORITY_ERROR bit set.</dd></dl>
<p>This function retrieves the number of MSB bits used to determine whether a pending interrupt has sufficient priority to preempt a currently active interrupt.</p>
<p><a class="el" href="group__irq__priority__defs.html#ga47b19866dc05c58c6923c313b371f881">IRQ_PRIORITY_ERROR</a> value is returned when priority grouping is not supported.</p>
<p>For Arm GIC the default implementation looks like the following example:</p>
<div class="fragment"><div class="line">uint32_t <a class="code" href="group__irq__ctrl__gr.html#ga061da812739bdba1e32765ed6501b83c">IRQ_GetPriorityGroupBits</a> (<span class="keywordtype">void</span>) {</div>
<div class="line"> uint32_t bp;</div>
<div class="line"> </div>
<div class="line"> bp = <a class="code" href="group__GIC__functions.html#gaa7046d8206ddd4696716726e68f85906">GIC_GetBinaryPoint</a>() & 0x07U;</div>
<div class="line"> </div>
<div class="line"> <span class="keywordflow">return</span> (7U - bp);</div>
<div class="line">}</div>
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<td class="memname">uint32_t IRQ_GetPriorityMask </td>
<td>(</td>
<td class="paramtype">void </td>
<td class="paramname"></td><td>)</td>
<td></td>
</tr>
</table>
</div><div class="memdoc">
<dl class="section return"><dt>Returns</dt><dd>current priority masking threshold value with optional IRQ_PRIORITY_ERROR bit set.</dd></dl>
<p>This function retrieves the priority masking threshold for the current processor.</p>
<p><a class="el" href="group__irq__priority__defs.html#ga47b19866dc05c58c6923c313b371f881">IRQ_PRIORITY_ERROR</a> value is returned if priority masking is not supported.</p>
<p>For Arm GIC the default implementation looks like the following example:</p>
<div class="fragment"><div class="line">uint32_t <a class="code" href="group__irq__ctrl__gr.html#ga77632ae73f1ba46c4a9a0c12e6bc4869">IRQ_GetPriorityMask</a> (<span class="keywordtype">void</span>) {</div>
<div class="line"> <span class="keywordflow">return</span> <a class="code" href="group__GIC__functions.html#ga2c5f9e5637560fc9d5c29d772580a728">GIC_GetInterfacePriorityMask</a>();</div>
<div class="line">}</div>
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<td class="memname">int32_t IRQ_Initialize </td>
<td>(</td>
<td class="paramtype">void </td>
<td class="paramname"></td><td>)</td>
<td></td>
</tr>
</table>
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<dl class="section return"><dt>Returns</dt><dd>0 on success, -1 on error.</dd></dl>
<p>This function initializes interrupt controller.</p>
<p>It disables all interrupt sources, clears all pending interrupts, sets interrupt priorities to highest priority and configures priority mask to lowest priority. IRQ and FIQ signal lines should be enabled and all interrupt handlers should be set to NULL.</p>
<p>For Arm GIC the default implementation looks like the following example:</p>
<div class="fragment"><div class="line"><span class="preprocessor">#ifndef IRQ_GIC_LINE_COUNT</span></div>
<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define IRQ_GIC_LINE_COUNT (1020U)</span></div>
<div class="line"><span class="preprocessor"></span><span class="preprocessor">#endif</span></div>
<div class="line"><span class="preprocessor"></span> </div>
<div class="line"><span class="keyword">static</span> IRQHandler IRQTable[IRQ_GIC_LINE_COUNT] = { 0U };</div>
<div class="line"> </div>
<div class="line">int32_t <a class="code" href="group__irq__ctrl__gr.html#ga03ea5d5d67a89acff8a5b02286795a99">IRQ_Initialize</a> (<span class="keywordtype">void</span>) {</div>
<div class="line"> uint32_t i;</div>
<div class="line"> </div>
<div class="line"> <span class="keywordflow">for</span> (i = 0U; i < IRQ_GIC_LINE_COUNT; i++) {</div>
<div class="line"> IRQTable[i] = (IRQHandler)NULL;</div>
<div class="line"> }</div>
<div class="line"> <a class="code" href="group__GIC__functions.html#ga818881f69aae3eef6eb996bee6f6c63e">GIC_Enable</a>();</div>
<div class="line"> <span class="keywordflow">return</span> (0);</div>
<div class="line">}</div>
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<td class="memname">int32_t IRQ_SetHandler </td>
<td>(</td>
<td class="paramtype"><a class="el" href="irq__ctrl_8h.html#ac62964c04a7fed2c84aeea9e34f415e2">IRQn_ID_t</a> </td>
<td class="paramname"><em>irqn</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype"><a class="el" href="irq__ctrl_8h.html#afbfa2180a9b6208f34891d539e9e2d52">IRQHandler_t</a> </td>
<td class="paramname"><em>handler</em> </td>
</tr>
<tr>
<td></td>
<td>)</td>
<td></td><td></td>
</tr>
</table>
</div><div class="memdoc">
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramdir">[in]</td><td class="paramname">irqn</td><td>interrupt ID number </td></tr>
<tr><td class="paramdir">[in]</td><td class="paramname">handler</td><td>interrupt handler function address </td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>0 on success, -1 on error.</dd></dl>
<p>This function registers address of the interrupt handler callback function corresponding to the specified interrupt ID number.</p>
<p>For Arm GIC the default implementation looks like the following example:</p>
<div class="fragment"><div class="line">int32_t <a class="code" href="group__irq__ctrl__gr.html#gac1fcc16fb8e488d315cfa496f1d71db3">IRQ_SetHandler</a> (<a class="code" href="irq__ctrl_8h.html#ac62964c04a7fed2c84aeea9e34f415e2">IRQn_ID_t</a> irqn, <a class="code" href="irq__ctrl_8h.html#afbfa2180a9b6208f34891d539e9e2d52">IRQHandler_t</a> handler) {</div>
<div class="line"> int32_t status;</div>
<div class="line"> </div>
<div class="line"> <span class="keywordflow">if</span> ((irqn >= 0) && (irqn < IRQ_GIC_LINE_COUNT)) {</div>
<div class="line"> IRQTable[irqn] = handler;</div>
<div class="line"> status = 0;</div>
<div class="line"> } <span class="keywordflow">else</span> {</div>
<div class="line"> status = -1;</div>
<div class="line"> }</div>
<div class="line"> </div>
<div class="line"> <span class="keywordflow">return</span> (status);</div>
<div class="line">}</div>
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<td class="memname">int32_t IRQ_SetMode </td>
<td>(</td>
<td class="paramtype"><a class="el" href="irq__ctrl_8h.html#ac62964c04a7fed2c84aeea9e34f415e2">IRQn_ID_t</a> </td>
<td class="paramname"><em>irqn</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>mode</em> </td>
</tr>
<tr>
<td></td>
<td>)</td>
<td></td><td></td>
</tr>
</table>
</div><div class="memdoc">
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramdir">[in]</td><td class="paramname">irqn</td><td>interrupt ID number </td></tr>
<tr><td class="paramdir">[in]</td><td class="paramname">mode</td><td>mode configuration </td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>0 on success, -1 on error.</dd></dl>
<p>This function configures the interrupt triggering mode, type, secure access and target CPUs of the interrupt (see <a class="el" href="group__irq__mode__defs.html">IRQ Mode Bit-Masks</a>) identified by the irqn parameter.</p>
<p>For Arm GIC the default implementation looks like the following example:</p>
<div class="fragment"><div class="line">int32_t <a class="code" href="group__irq__ctrl__gr.html#gab35da69354d2e515931580a1308a3a85">IRQ_SetMode</a> (<a class="code" href="irq__ctrl_8h.html#ac62964c04a7fed2c84aeea9e34f415e2">IRQn_ID_t</a> irqn, uint32_t mode) {</div>
<div class="line"> int32_t status;</div>
<div class="line"> uint32_t val;</div>
<div class="line"> uint8_t cfg;</div>
<div class="line"> uint8_t secure;</div>
<div class="line"> uint8_t cpu;</div>
<div class="line"> </div>
<div class="line"> status = 0;</div>
<div class="line"> </div>
<div class="line"> <span class="keywordflow">if</span> ((irqn >= 0) && (irqn < IRQ_GIC_LINE_COUNT)) {</div>
<div class="line"> <span class="comment">// Check triggering mode</span></div>
<div class="line"> val = (mode & <a class="code" href="irq__ctrl_8h.html#a2fafbaf2f6da5241ad97af6c493fa218">IRQ_MODE_TRIG_Msk</a>);</div>
<div class="line"></div>
<div class="line"> <span class="keywordflow">if</span> (val == <a class="code" href="group__irq__mode__defs.html#gabc31ba71612436a6ccc49342f35fec58">IRQ_MODE_TRIG_LEVEL</a>) {</div>
<div class="line"> cfg = 0x00U;</div>
<div class="line"> } <span class="keywordflow">else</span> <span class="keywordflow">if</span> (val == <a class="code" href="group__irq__mode__defs.html#gaa9a8e0968a4ccd57eb7544a16d05f24d">IRQ_MODE_TRIG_EDGE</a>) {</div>
<div class="line"> cfg = 0x02U;</div>
<div class="line"> } <span class="keywordflow">else</span> {</div>
<div class="line"> status = -1;</div>
<div class="line"> }</div>
<div class="line"> </div>
<div class="line"> <span class="comment">// Check interrupt type</span></div>
<div class="line"> val = mode & <a class="code" href="irq__ctrl_8h.html#a7b0581db3736a143cd582cd2457bf3cc">IRQ_MODE_TYPE_Msk</a>;</div>
<div class="line"> </div>
<div class="line"> <span class="keywordflow">if</span> (val != <a class="code" href="group__irq__mode__defs.html#gab0d022bbd15beb1a6578b5535d95f9cf">IRQ_MODE_TYPE_IRQ</a>) {</div>
<div class="line"> status = -1;</div>
<div class="line"> }</div>
<div class="line"> </div>
<div class="line"> <span class="comment">// Check interrupt domain</span></div>
<div class="line"> val = mode & <a class="code" href="irq__ctrl_8h.html#afdc87f9fda2bafac2b0399ebdb39bf3e">IRQ_MODE_DOMAIN_Msk</a>;</div>
<div class="line"> </div>
<div class="line"> <span class="keywordflow">if</span> (val == <a class="code" href="group__irq__mode__defs.html#ga7498851a6a7f3e2c5e087041617f5be7">IRQ_MODE_DOMAIN_NONSECURE</a>) {</div>
<div class="line"> secure = 0;</div>
<div class="line"> } <span class="keywordflow">else</span> {</div>
<div class="line"> <span class="comment">// Check security extensions support</span></div>
<div class="line"> val = <a class="code" href="group__GIC__functions.html#ga7d93d39736ef5e379e6511430ee6e75f">GIC_DistributorInfo</a>() & (1UL << 10U);</div>
<div class="line"> </div>
<div class="line"> <span class="keywordflow">if</span> (val != 0U) {</div>
<div class="line"> <span class="comment">// Security extensions are supported</span></div>
<div class="line"> secure = 1;</div>
<div class="line"> } <span class="keywordflow">else</span> {</div>
<div class="line"> status = -1;</div>
<div class="line"> }</div>
<div class="line"> }</div>
<div class="line"> </div>
<div class="line"> <span class="comment">// Check interrupt CPU targets</span></div>
<div class="line"> val = mode & <a class="code" href="irq__ctrl_8h.html#a96f739279c27f3e56ede4f28de4a48d8">IRQ_MODE_CPU_Msk</a>;</div>
<div class="line"> </div>
<div class="line"> <span class="keywordflow">if</span> (val == <a class="code" href="group__irq__mode__defs.html#gad3d0505689768247c67495b7359e147f">IRQ_MODE_CPU_ALL</a>) {</div>
<div class="line"> cpu = 0xFF;</div>
<div class="line"> } <span class="keywordflow">else</span> {</div>
<div class="line"> cpu = val >> <a class="code" href="irq__ctrl_8h.html#ab7527409c193021e65aaf4d519caea46">IRQ_MODE_CPU_Pos</a>;</div>
<div class="line"> }</div>
<div class="line"> </div>
<div class="line"> <span class="comment">// Apply configuration if no mode error</span></div>
<div class="line"> <span class="keywordflow">if</span> (status == 0) {</div>
<div class="line"> <a class="code" href="core__ca_8h.html#a5dffcd04b18d2c3ee5a410e185ce5108">GIC_SetConfiguration</a>((<a class="code" href="ARMCA9_8h.html#a7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a>)irqn, cfg);</div>
<div class="line"> <a class="code" href="group__GIC__functions.html#gae86bba705d0d4ef812b84d29d7b3ca2b">GIC_SetTarget</a> ((<a class="code" href="ARMCA9_8h.html#a7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a>)irqn, cpu);</div>
<div class="line"> </div>
<div class="line"> <span class="keywordflow">if</span> (secure != 0U) {</div>
<div class="line"> <a class="code" href="core__ca_8h.html#ab875d63dc51a75149802945bb00e2695">GIC_SetGroup</a> ((<a class="code" href="ARMCA9_8h.html#a7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a>)irqn, secure);</div>
<div class="line"> }</div>
<div class="line"> }</div>
<div class="line"> }</div>
<div class="line"> </div>
<div class="line"> <span class="keywordflow">return</span> (status);</div>
<div class="line">}</div>
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<td class="memname">int32_t IRQ_SetPending </td>
<td>(</td>
<td class="paramtype"><a class="el" href="irq__ctrl_8h.html#ac62964c04a7fed2c84aeea9e34f415e2">IRQn_ID_t</a> </td>
<td class="paramname"><em>irqn</em></td><td>)</td>
<td></td>
</tr>
</table>
</div><div class="memdoc">
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramdir">[in]</td><td class="paramname">irqn</td><td>interrupt ID number </td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>0 on success, -1 on error.</dd></dl>
<p>This function sets the pending status of the interrupt identified by the irqn parameter.</p>
<p>For Arm GIC the default implementation looks like the following example:</p>
<div class="fragment"><div class="line">int32_t <a class="code" href="group__irq__ctrl__gr.html#ga88aedf1dee1061783e6c05c535e7b6c4">IRQ_SetPending</a> (<a class="code" href="irq__ctrl_8h.html#ac62964c04a7fed2c84aeea9e34f415e2">IRQn_ID_t</a> irqn) {</div>
<div class="line"> int32_t status;</div>
<div class="line"> </div>
<div class="line"> <span class="keywordflow">if</span> ((irqn >= 0) && (irqn < IRQ_GIC_LINE_COUNT)) {</div>
<div class="line"> <a class="code" href="group__GIC__functions.html#ga18fbddf7f3594df141c97f61a71da47c">GIC_SetPendingIRQ</a> ((<a class="code" href="ARMCA9_8h.html#a7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a>)irqn);</div>
<div class="line"> status = 0;</div>
<div class="line"> } <span class="keywordflow">else</span> {</div>
<div class="line"> status = -1;</div>
<div class="line"> }</div>
<div class="line"> </div>
<div class="line"> <span class="keywordflow">return</span> (status);</div>
<div class="line">}</div>
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<td class="memname">int32_t IRQ_SetPriority </td>
<td>(</td>
<td class="paramtype"><a class="el" href="irq__ctrl_8h.html#ac62964c04a7fed2c84aeea9e34f415e2">IRQn_ID_t</a> </td>
<td class="paramname"><em>irqn</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>priority</em> </td>
</tr>
<tr>
<td></td>
<td>)</td>
<td></td><td></td>
</tr>
</table>
</div><div class="memdoc">
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramdir">[in]</td><td class="paramname">irqn</td><td>interrupt ID number </td></tr>
<tr><td class="paramdir">[in]</td><td class="paramname">priority</td><td>interrupt priority value </td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>0 on success, -1 on error.</dd></dl>
<p>This function sets the priority of the interrupt identified by the irqn parameter.</p>
<p>Higher priority numbers have lower priority. The highest interrupt priority has priority value 0, while the lowest value depends on the number of implemented priority levels.</p>
<p>The number of implemented priority bits can be determined by setting value <a class="el" href="group__irq__priority__defs.html#gabaa4e91ab84dbe5f669080af6d0d81fa">IRQ_PRIORITY_Msk</a> to arbitrary irqn and by retrieving the actual stored value with IRQ_GetPriority function.</p>
<p>For Arm GIC the default implementation looks like the following example:</p>
<div class="fragment"><div class="line">int32_t <a class="code" href="group__irq__ctrl__gr.html#gaa90aed20ac94420fff4bbbf55c12d4c2">IRQ_SetPriority</a> (<a class="code" href="irq__ctrl_8h.html#ac62964c04a7fed2c84aeea9e34f415e2">IRQn_ID_t</a> irqn, uint32_t priority) {</div>
<div class="line"> int32_t status;</div>
<div class="line"> </div>
<div class="line"> <span class="keywordflow">if</span> ((irqn >= 0) && (irqn < IRQ_GIC_LINE_COUNT)) {</div>
<div class="line"> <a class="code" href="group__GIC__functions.html#ga27b9862b58290276851ec669cabf0f71">GIC_SetPriority</a> ((<a class="code" href="ARMCA9_8h.html#a7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a>)irqn, priority);</div>
<div class="line"> status = 0;</div>
<div class="line"> } <span class="keywordflow">else</span> {</div>
<div class="line"> status = -1;</div>
<div class="line"> }</div>
<div class="line"> </div>
<div class="line"> <span class="keywordflow">return</span> (status);</div>
<div class="line">}</div>
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<td class="memname">int32_t IRQ_SetPriorityGroupBits </td>
<td>(</td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>bits</em></td><td>)</td>
<td></td>
</tr>
</table>
</div><div class="memdoc">
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramdir">[in]</td><td class="paramname">bits</td><td>number of MSB bits included in the group priority field comparison </td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>0 on success, -1 on error.</dd></dl>
<p>This function sets the number of MSB priority bits used to determine whether a pending interrupt has sufficient priority to preempt a currently active interrupt.</p>
<p>The number of implemented group priority bits can be determined by setting value <a class="el" href="group__irq__priority__defs.html#gabaa4e91ab84dbe5f669080af6d0d81fa">IRQ_PRIORITY_Msk</a> and by retrieving the actual stored value with <a class="el" href="group__irq__ctrl__gr.html#ga061da812739bdba1e32765ed6501b83c">IRQ_GetPriorityGroupBits</a> function. Function returns error status -1 if priority grouping is not supported.</p>
<p>For Arm GIC the default implementation looks like the following example:</p>
<div class="fragment"><div class="line">int32_t <a class="code" href="group__irq__ctrl__gr.html#gabaa4074988ea9e30523f7ed5a86953c2">IRQ_SetPriorityGroupBits</a> (uint32_t bits) {</div>
<div class="line"> int32_t status;</div>
<div class="line"> </div>
<div class="line"> <span class="keywordflow">if</span> (bits == <a class="code" href="group__irq__priority__defs.html#gabaa4e91ab84dbe5f669080af6d0d81fa">IRQ_PRIORITY_Msk</a>) {</div>
<div class="line"> bits = 7U;</div>
<div class="line"> }</div>
<div class="line"> </div>
<div class="line"> <span class="keywordflow">if</span> (bits < 8U) {</div>
<div class="line"> <a class="code" href="group__GIC__functions.html#ga5dfedeb5403656a77e0fef4e1cc2c0c6">GIC_SetBinaryPoint</a> (7U - bits);</div>
<div class="line"> status = 0;</div>
<div class="line"> } <span class="keywordflow">else</span> {</div>
<div class="line"> status = -1;</div>
<div class="line"> }</div>
<div class="line"> </div>
<div class="line"> <span class="keywordflow">return</span> (status);</div>
<div class="line">}</div>
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<td class="memname">int32_t IRQ_SetPriorityMask </td>
<td>(</td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>priority</em></td><td>)</td>
<td></td>
</tr>
</table>
</div><div class="memdoc">
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramdir">[in]</td><td class="paramname">priority</td><td>priority masking threshold value </td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>0 on success, -1 on error.</dd></dl>
<p>This function sets the priority masking threshold for the current processor.</p>
<p>It ensures that only interrupts with a higher priority than priority threshold value are signaled to the target processor. Function returns error status -1 if priority masking is not supported.</p>
<p>For Arm GIC the default implementation looks like the following example:</p>
<div class="fragment"><div class="line"><a class="code" href="group__irq__ctrl__gr.html#ga3a79888f72bd1db45f0b9a59dbaa2337">IRQ_SetPriorityMask</a> (uint32_t priority) {</div>
<div class="line"> <a class="code" href="group__GIC__functions.html#gaa5eb0e76dbc89596e1ce47ddb9edc4a0">GIC_SetInterfacePriorityMask</a> (priority);</div>
<div class="line"> <span class="keywordflow">return</span> (0);</div>
<div class="line">}</div>
</div><!-- fragment -->
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