Drivers/CMSIS/docs/Core_A/html/rev_histCoreA.html


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<title>CMSIS-Core (Cortex-A): Revision History of CMSIS-Core (Cortex-A)</title>
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   &#160;<span id="projectnumber">Version 1.1.2</span>
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<div class="title">Revision History of CMSIS-Core (Cortex-A) </div>  </div>
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<div class="textblock"><table  class="cmtable" summary="Revision History">
<tr>
<th>Version </th><th>Description  </th></tr>
<tr>
<td>V1.1.2 </td><td><ul>
<li>
Removed using get/set built-ins FPSCR in GCC &gt;= 7.2 due to shortcomings. </li>
<li>
Fixed co-processor register access macros for Arm Compiler 5. </li>
</ul>
</td></tr>
<tr>
<td>V1.1.1 </td><td><ul>
<li>
Refactored L1 cache maintenance to be compiler agnostic. </li>
</ul>
</td></tr>
<tr>
<td>V1.1.0 </td><td><ul>
<li>
Added compiler_iccarm.h for IAR compiler. </li>
<li>
Added missing core access functions for Arm Compiler 5. </li>
<li>
Aligned access function to coprocessor 15. </li>
<li>
Additional generic Timer functions. </li>
<li>
Bug fixes and minor enhancements. </li>
</ul>
</td></tr>
<tr>
<td>V1.0.0 </td><td>Initial Release for Cortex-A5/A7/A9 processors.  </td></tr>
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