1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
|
/**
******************************************************************************
* @file stm32wbxx_ll_ipcc.h
* @author MCD Application Team
* @brief Header file of IPCC LL module.
******************************************************************************
* @attention
*
* Copyright (c) 2019 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32WBxx_LL_IPCC_H
#define STM32WBxx_LL_IPCC_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32wbxx.h"
/** @addtogroup STM32WBxx_LL_Driver
* @{
*/
#if defined(IPCC)
/** @defgroup IPCC_LL IPCC
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup IPCC_LL_Exported_Constants IPCC Exported Constants
* @{
*/
/** @defgroup IPCC_LL_EC_GET_FLAG Get Flags Defines
* @brief Flags defines which can be used with LL_IPCC_ReadReg function
* @{
*/
#define LL_IPCC_C1TOC2SR_CH1F IPCC_C1TOC2SR_CH1F_Msk /*!< C1 transmit to C2 receive Channel1 status flag before masking */
#define LL_IPCC_C1TOC2SR_CH2F IPCC_C1TOC2SR_CH2F_Msk /*!< C1 transmit to C2 receive Channel2 status flag before masking */
#define LL_IPCC_C1TOC2SR_CH3F IPCC_C1TOC2SR_CH3F_Msk /*!< C1 transmit to C2 receive Channel3 status flag before masking */
#define LL_IPCC_C1TOC2SR_CH4F IPCC_C1TOC2SR_CH4F_Msk /*!< C1 transmit to C2 receive Channel4 status flag before masking */
#define LL_IPCC_C1TOC2SR_CH5F IPCC_C1TOC2SR_CH5F_Msk /*!< C1 transmit to C2 receive Channel5 status flag before masking */
#define LL_IPCC_C1TOC2SR_CH6F IPCC_C1TOC2SR_CH6F_Msk /*!< C1 transmit to C2 receive Channel6 status flag before masking */
#define LL_IPCC_C2TOC1SR_CH1F IPCC_C2TOC1SR_CH1F_Msk /*!< C2 transmit to C1 receive Channel1 status flag before masking */
#define LL_IPCC_C2TOC1SR_CH2F IPCC_C2TOC1SR_CH2F_Msk /*!< C2 transmit to C1 receive Channel2 status flag before masking */
#define LL_IPCC_C2TOC1SR_CH3F IPCC_C2TOC1SR_CH3F_Msk /*!< C2 transmit to C1 receive Channel3 status flag before masking */
#define LL_IPCC_C2TOC1SR_CH4F IPCC_C2TOC1SR_CH4F_Msk /*!< C2 transmit to C1 receive Channel4 status flag before masking */
#define LL_IPCC_C2TOC1SR_CH5F IPCC_C2TOC1SR_CH5F_Msk /*!< C2 transmit to C1 receive Channel5 status flag before masking */
#define LL_IPCC_C2TOC1SR_CH6F IPCC_C2TOC1SR_CH6F_Msk /*!< C2 transmit to C1 receive Channel6 status flag before masking */
/**
* @}
*/
/** @defgroup IPCC_LL_EC_Channel Channel
* @{
*/
#define LL_IPCC_CHANNEL_1 (0x00000001U) /*!< IPCC Channel 1 */
#define LL_IPCC_CHANNEL_2 (0x00000002U) /*!< IPCC Channel 2 */
#define LL_IPCC_CHANNEL_3 (0x00000004U) /*!< IPCC Channel 3 */
#define LL_IPCC_CHANNEL_4 (0x00000008U) /*!< IPCC Channel 4 */
#define LL_IPCC_CHANNEL_5 (0x00000010U) /*!< IPCC Channel 5 */
#define LL_IPCC_CHANNEL_6 (0x00000020U) /*!< IPCC Channel 6 */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup IPCC_LL_Exported_Macros IPCC Exported Macros
* @{
*/
/** @defgroup IPCC_LL_EM_WRITE_READ Common Write and read registers Macros
* @{
*/
/**
* @brief Write a value in IPCC register
* @param __INSTANCE__ IPCC Instance
* @param __REG__ Register to be written
* @param __VALUE__ Value to be written in the register
* @retval None
*/
#define LL_IPCC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
/**
* @brief Read a value in IPCC register
* @param __INSTANCE__ IPCC Instance
* @param __REG__ Register to be read
* @retval Register value
*/
#define LL_IPCC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
/**
* @}
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup IPCC_LL_Exported_Functions IPCC Exported Functions
* @{
*/
/** @defgroup IPCC_LL_EF_IT_Management IT_Management
* @{
*/
/**
* @brief Enable Transmit channel free interrupt for processor 1.
* @rmtoll C1CR TXFIE LL_C1_IPCC_EnableIT_TXF
* @param IPCCx IPCC Instance.
* @retval None
*/
__STATIC_INLINE void LL_C1_IPCC_EnableIT_TXF(IPCC_TypeDef *IPCCx)
{
SET_BIT(IPCCx->C1CR, IPCC_C1CR_TXFIE);
}
/**
* @brief Disable Transmit channel free interrupt for processor 1.
* @rmtoll C1CR TXFIE LL_C1_IPCC_DisableIT_TXF
* @param IPCCx IPCC Instance.
* @retval None
*/
__STATIC_INLINE void LL_C1_IPCC_DisableIT_TXF(IPCC_TypeDef *IPCCx)
{
CLEAR_BIT(IPCCx->C1CR, IPCC_C1CR_TXFIE);
}
/**
* @brief Check if Transmit channel free interrupt for processor 1 is enabled.
* @rmtoll C1CR TXFIE LL_C1_IPCC_IsEnabledIT_TXF
* @param IPCCx IPCC Instance.
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_C1_IPCC_IsEnabledIT_TXF(IPCC_TypeDef const *const IPCCx)
{
return ((READ_BIT(IPCCx->C1CR, IPCC_C1CR_TXFIE) == (IPCC_C1CR_TXFIE)) ? 1UL : 0UL);
}
/**
* @brief Enable Receive channel occupied interrupt for processor 1.
* @rmtoll C1CR RXOIE LL_C1_IPCC_EnableIT_RXO
* @param IPCCx IPCC Instance.
* @retval None
*/
__STATIC_INLINE void LL_C1_IPCC_EnableIT_RXO(IPCC_TypeDef *IPCCx)
{
SET_BIT(IPCCx->C1CR, IPCC_C1CR_RXOIE);
}
/**
* @brief Disable Receive channel occupied interrupt for processor 1.
* @rmtoll C1CR RXOIE LL_C1_IPCC_DisableIT_RXO
* @param IPCCx IPCC Instance.
* @retval None
*/
__STATIC_INLINE void LL_C1_IPCC_DisableIT_RXO(IPCC_TypeDef *IPCCx)
{
CLEAR_BIT(IPCCx->C1CR, IPCC_C1CR_RXOIE);
}
/**
* @brief Check if Receive channel occupied interrupt for processor 1 is enabled.
* @rmtoll C1CR RXOIE LL_C1_IPCC_IsEnabledIT_RXO
* @param IPCCx IPCC Instance.
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_C1_IPCC_IsEnabledIT_RXO(IPCC_TypeDef const *const IPCCx)
{
return ((READ_BIT(IPCCx->C1CR, IPCC_C1CR_RXOIE) == (IPCC_C1CR_RXOIE)) ? 1UL : 0UL);
}
/**
* @brief Enable Transmit channel free interrupt for processor 2.
* @rmtoll C2CR TXFIE LL_C2_IPCC_EnableIT_TXF
* @param IPCCx IPCC Instance.
* @retval None
*/
__STATIC_INLINE void LL_C2_IPCC_EnableIT_TXF(IPCC_TypeDef *IPCCx)
{
SET_BIT(IPCCx->C2CR, IPCC_C2CR_TXFIE);
}
/**
* @brief Disable Transmit channel free interrupt for processor 2.
* @rmtoll C2CR TXFIE LL_C2_IPCC_DisableIT_TXF
* @param IPCCx IPCC Instance.
* @retval None
*/
__STATIC_INLINE void LL_C2_IPCC_DisableIT_TXF(IPCC_TypeDef *IPCCx)
{
CLEAR_BIT(IPCCx->C2CR, IPCC_C2CR_TXFIE);
}
/**
* @brief Check if Transmit channel free interrupt for processor 2 is enabled.
* @rmtoll C2CR TXFIE LL_C2_IPCC_IsEnabledIT_TXF
* @param IPCCx IPCC Instance.
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_C2_IPCC_IsEnabledIT_TXF(IPCC_TypeDef const *const IPCCx)
{
return ((READ_BIT(IPCCx->C2CR, IPCC_C2CR_TXFIE) == (IPCC_C2CR_TXFIE)) ? 1UL : 0UL);
}
/**
* @brief Enable Receive channel occupied interrupt for processor 2.
* @rmtoll C2CR RXOIE LL_C2_IPCC_EnableIT_RXO
* @param IPCCx IPCC Instance.
* @retval None
*/
__STATIC_INLINE void LL_C2_IPCC_EnableIT_RXO(IPCC_TypeDef *IPCCx)
{
SET_BIT(IPCCx->C2CR, IPCC_C2CR_RXOIE);
}
/**
* @brief Disable Receive channel occupied interrupt for processor 2.
* @rmtoll C2CR RXOIE LL_C2_IPCC_DisableIT_RXO
* @param IPCCx IPCC Instance.
* @retval None
*/
__STATIC_INLINE void LL_C2_IPCC_DisableIT_RXO(IPCC_TypeDef *IPCCx)
{
CLEAR_BIT(IPCCx->C2CR, IPCC_C2CR_RXOIE);
}
/**
* @brief Check if Receive channel occupied interrupt for processor 2 is enabled.
* @rmtoll C2CR RXOIE LL_C2_IPCC_IsEnabledIT_RXO
* @param IPCCx IPCC Instance.
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_C2_IPCC_IsEnabledIT_RXO(IPCC_TypeDef const *const IPCCx)
{
return ((READ_BIT(IPCCx->C2CR, IPCC_C2CR_RXOIE) == (IPCC_C2CR_RXOIE)) ? 1UL : 0UL);
}
/**
* @}
*/
/** @defgroup IPCC_LL_EF_Configuration Configuration
* @{
*/
/**
* @brief Unmask transmit channel free interrupt for processor 1.
* @rmtoll C1MR CH1FM LL_C1_IPCC_EnableTransmitChannel\n
* C1MR CH2FM LL_C1_IPCC_EnableTransmitChannel\n
* C1MR CH3FM LL_C1_IPCC_EnableTransmitChannel\n
* C1MR CH4FM LL_C1_IPCC_EnableTransmitChannel\n
* C1MR CH5FM LL_C1_IPCC_EnableTransmitChannel\n
* C1MR CH6FM LL_C1_IPCC_EnableTransmitChannel
* @param IPCCx IPCC Instance.
* @param Channel This parameter can be a combination of the following values:
* @arg @ref LL_IPCC_CHANNEL_1
* @arg @ref LL_IPCC_CHANNEL_2
* @arg @ref LL_IPCC_CHANNEL_3
* @arg @ref LL_IPCC_CHANNEL_4
* @arg @ref LL_IPCC_CHANNEL_5
* @arg @ref LL_IPCC_CHANNEL_6
* @retval None
*/
__STATIC_INLINE void LL_C1_IPCC_EnableTransmitChannel(IPCC_TypeDef *IPCCx, uint32_t Channel)
{
CLEAR_BIT(IPCCx->C1MR, Channel << IPCC_C1MR_CH1FM_Pos);
}
/**
* @brief Mask transmit channel free interrupt for processor 1.
* @rmtoll C1MR CH1FM LL_C1_IPCC_DisableTransmitChannel\n
* C1MR CH2FM LL_C1_IPCC_DisableTransmitChannel\n
* C1MR CH3FM LL_C1_IPCC_DisableTransmitChannel\n
* C1MR CH4FM LL_C1_IPCC_DisableTransmitChannel\n
* C1MR CH5FM LL_C1_IPCC_DisableTransmitChannel\n
* C1MR CH6FM LL_C1_IPCC_DisableTransmitChannel
* @param IPCCx IPCC Instance.
* @param Channel This parameter can be a combination of the following values:
* @arg @ref LL_IPCC_CHANNEL_1
* @arg @ref LL_IPCC_CHANNEL_2
* @arg @ref LL_IPCC_CHANNEL_3
* @arg @ref LL_IPCC_CHANNEL_4
* @arg @ref LL_IPCC_CHANNEL_5
* @arg @ref LL_IPCC_CHANNEL_6
* @retval None
*/
__STATIC_INLINE void LL_C1_IPCC_DisableTransmitChannel(IPCC_TypeDef *IPCCx, uint32_t Channel)
{
SET_BIT(IPCCx->C1MR, Channel << IPCC_C1MR_CH1FM_Pos);
}
/**
* @brief Check if Transmit channel free interrupt for processor 1 is masked.
* @rmtoll C1MR CH1FM LL_C1_IPCC_IsEnabledTransmitChannel\n
* C1MR CH2FM LL_C1_IPCC_IsEnabledTransmitChannel\n
* C1MR CH3FM LL_C1_IPCC_IsEnabledTransmitChannel\n
* C1MR CH4FM LL_C1_IPCC_IsEnabledTransmitChannel\n
* C1MR CH5FM LL_C1_IPCC_IsEnabledTransmitChannel\n
* C1MR CH6FM LL_C1_IPCC_IsEnabledTransmitChannel
* @param IPCCx IPCC Instance.
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_IPCC_CHANNEL_1
* @arg @ref LL_IPCC_CHANNEL_2
* @arg @ref LL_IPCC_CHANNEL_3
* @arg @ref LL_IPCC_CHANNEL_4
* @arg @ref LL_IPCC_CHANNEL_5
* @arg @ref LL_IPCC_CHANNEL_6
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_C1_IPCC_IsEnabledTransmitChannel(IPCC_TypeDef const *const IPCCx, uint32_t Channel)
{
return ((READ_BIT(IPCCx->C1MR, Channel << IPCC_C1MR_CH1FM_Pos) != (Channel << IPCC_C1MR_CH1FM_Pos)) ? 1UL : 0UL);
}
/**
* @brief Unmask receive channel occupied interrupt for processor 1.
* @rmtoll C1MR CH1OM LL_C1_IPCC_EnableReceiveChannel\n
* C1MR CH2OM LL_C1_IPCC_EnableReceiveChannel\n
* C1MR CH3OM LL_C1_IPCC_EnableReceiveChannel\n
* C1MR CH4OM LL_C1_IPCC_EnableReceiveChannel\n
* C1MR CH5OM LL_C1_IPCC_EnableReceiveChannel\n
* C1MR CH6OM LL_C1_IPCC_EnableReceiveChannel
* @param IPCCx IPCC Instance.
* @param Channel This parameter can be a combination of the following values:
* @arg @ref LL_IPCC_CHANNEL_1
* @arg @ref LL_IPCC_CHANNEL_2
* @arg @ref LL_IPCC_CHANNEL_3
* @arg @ref LL_IPCC_CHANNEL_4
* @arg @ref LL_IPCC_CHANNEL_5
* @arg @ref LL_IPCC_CHANNEL_6
* @retval None
*/
__STATIC_INLINE void LL_C1_IPCC_EnableReceiveChannel(IPCC_TypeDef *IPCCx, uint32_t Channel)
{
CLEAR_BIT(IPCCx->C1MR, Channel);
}
/**
* @brief Mask receive channel occupied interrupt for processor 1.
* @rmtoll C1MR CH1OM LL_C1_IPCC_DisableReceiveChannel\n
* C1MR CH2OM LL_C1_IPCC_DisableReceiveChannel\n
* C1MR CH3OM LL_C1_IPCC_DisableReceiveChannel\n
* C1MR CH4OM LL_C1_IPCC_DisableReceiveChannel\n
* C1MR CH5OM LL_C1_IPCC_DisableReceiveChannel\n
* C1MR CH6OM LL_C1_IPCC_DisableReceiveChannel
* @param IPCCx IPCC Instance.
* @param Channel This parameter can be a combination of the following values:
* @arg @ref LL_IPCC_CHANNEL_1
* @arg @ref LL_IPCC_CHANNEL_2
* @arg @ref LL_IPCC_CHANNEL_3
* @arg @ref LL_IPCC_CHANNEL_4
* @arg @ref LL_IPCC_CHANNEL_5
* @arg @ref LL_IPCC_CHANNEL_6
* @retval None
*/
__STATIC_INLINE void LL_C1_IPCC_DisableReceiveChannel(IPCC_TypeDef *IPCCx, uint32_t Channel)
{
SET_BIT(IPCCx->C1MR, Channel);
}
/**
* @brief Check if Receive channel occupied interrupt for processor 1 is masked.
* @rmtoll C1MR CH1OM LL_C1_IPCC_IsEnabledReceiveChannel\n
* C1MR CH2OM LL_C1_IPCC_IsEnabledReceiveChannel\n
* C1MR CH3OM LL_C1_IPCC_IsEnabledReceiveChannel\n
* C1MR CH4OM LL_C1_IPCC_IsEnabledReceiveChannel\n
* C1MR CH5OM LL_C1_IPCC_IsEnabledReceiveChannel\n
* C1MR CH6OM LL_C1_IPCC_IsEnabledReceiveChannel
* @param IPCCx IPCC Instance.
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_IPCC_CHANNEL_1
* @arg @ref LL_IPCC_CHANNEL_2
* @arg @ref LL_IPCC_CHANNEL_3
* @arg @ref LL_IPCC_CHANNEL_4
* @arg @ref LL_IPCC_CHANNEL_5
* @arg @ref LL_IPCC_CHANNEL_6
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_C1_IPCC_IsEnabledReceiveChannel(IPCC_TypeDef const *const IPCCx, uint32_t Channel)
{
return ((READ_BIT(IPCCx->C1MR, Channel) != (Channel)) ? 1UL : 0UL);
}
/**
* @brief Unmask transmit channel free interrupt for processor 2.
* @rmtoll C2MR CH1FM LL_C2_IPCC_EnableTransmitChannel\n
* C2MR CH2FM LL_C2_IPCC_EnableTransmitChannel\n
* C2MR CH3FM LL_C2_IPCC_EnableTransmitChannel\n
* C2MR CH4FM LL_C2_IPCC_EnableTransmitChannel\n
* C2MR CH5FM LL_C2_IPCC_EnableTransmitChannel\n
* C2MR CH6FM LL_C2_IPCC_EnableTransmitChannel
* @param IPCCx IPCC Instance.
* @param Channel This parameter can be a combination of the following values:
* @arg @ref LL_IPCC_CHANNEL_1
* @arg @ref LL_IPCC_CHANNEL_2
* @arg @ref LL_IPCC_CHANNEL_3
* @arg @ref LL_IPCC_CHANNEL_4
* @arg @ref LL_IPCC_CHANNEL_5
* @arg @ref LL_IPCC_CHANNEL_6
* @retval None
*/
__STATIC_INLINE void LL_C2_IPCC_EnableTransmitChannel(IPCC_TypeDef *IPCCx, uint32_t Channel)
{
CLEAR_BIT(IPCCx->C2MR, Channel << IPCC_C2MR_CH1FM_Pos);
}
/**
* @brief Mask transmit channel free interrupt for processor 2.
* @rmtoll C2MR CH1FM LL_C2_IPCC_DisableTransmitChannel\n
* C2MR CH2FM LL_C2_IPCC_DisableTransmitChannel\n
* C2MR CH3FM LL_C2_IPCC_DisableTransmitChannel\n
* C2MR CH4FM LL_C2_IPCC_DisableTransmitChannel\n
* C2MR CH5FM LL_C2_IPCC_DisableTransmitChannel\n
* C2MR CH6FM LL_C2_IPCC_DisableTransmitChannel
* @param IPCCx IPCC Instance.
* @param Channel This parameter can be a combination of the following values:
* @arg @ref LL_IPCC_CHANNEL_1
* @arg @ref LL_IPCC_CHANNEL_2
* @arg @ref LL_IPCC_CHANNEL_3
* @arg @ref LL_IPCC_CHANNEL_4
* @arg @ref LL_IPCC_CHANNEL_5
* @arg @ref LL_IPCC_CHANNEL_6
* @retval None
*/
__STATIC_INLINE void LL_C2_IPCC_DisableTransmitChannel(IPCC_TypeDef *IPCCx, uint32_t Channel)
{
SET_BIT(IPCCx->C2MR, Channel << (IPCC_C2MR_CH1FM_Pos));
}
/**
* @brief Check if Transmit channel free interrupt for processor 2 is masked.
* @rmtoll C2MR CH1FM LL_C2_IPCC_IsEnabledTransmitChannel\n
* C2MR CH2FM LL_C2_IPCC_IsEnabledTransmitChannel\n
* C2MR CH3FM LL_C2_IPCC_IsEnabledTransmitChannel\n
* C2MR CH4FM LL_C2_IPCC_IsEnabledTransmitChannel\n
* C2MR CH5FM LL_C2_IPCC_IsEnabledTransmitChannel\n
* C2MR CH6FM LL_C2_IPCC_IsEnabledTransmitChannel
* @param IPCCx IPCC Instance.
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_IPCC_CHANNEL_1
* @arg @ref LL_IPCC_CHANNEL_2
* @arg @ref LL_IPCC_CHANNEL_3
* @arg @ref LL_IPCC_CHANNEL_4
* @arg @ref LL_IPCC_CHANNEL_5
* @arg @ref LL_IPCC_CHANNEL_6
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_C2_IPCC_IsEnabledTransmitChannel(IPCC_TypeDef const *const IPCCx, uint32_t Channel)
{
return ((READ_BIT(IPCCx->C2MR, Channel << IPCC_C2MR_CH1FM_Pos) != (Channel << IPCC_C2MR_CH1FM_Pos)) ? 1UL : 0UL);
}
/**
* @brief Unmask receive channel occupied interrupt for processor 2.
* @rmtoll C2MR CH1OM LL_C2_IPCC_EnableReceiveChannel\n
* C2MR CH2OM LL_C2_IPCC_EnableReceiveChannel\n
* C2MR CH3OM LL_C2_IPCC_EnableReceiveChannel\n
* C2MR CH4OM LL_C2_IPCC_EnableReceiveChannel\n
* C2MR CH5OM LL_C2_IPCC_EnableReceiveChannel\n
* C2MR CH6OM LL_C2_IPCC_EnableReceiveChannel
* @param IPCCx IPCC Instance.
* @param Channel This parameter can be a combination of the following values:
* @arg @ref LL_IPCC_CHANNEL_1
* @arg @ref LL_IPCC_CHANNEL_2
* @arg @ref LL_IPCC_CHANNEL_3
* @arg @ref LL_IPCC_CHANNEL_4
* @arg @ref LL_IPCC_CHANNEL_5
* @arg @ref LL_IPCC_CHANNEL_6
* @retval None
*/
__STATIC_INLINE void LL_C2_IPCC_EnableReceiveChannel(IPCC_TypeDef *IPCCx, uint32_t Channel)
{
CLEAR_BIT(IPCCx->C2MR, Channel);
}
/**
* @brief Mask receive channel occupied interrupt for processor 1.
* @rmtoll C2MR CH1OM LL_C2_IPCC_DisableReceiveChannel\n
* C2MR CH2OM LL_C2_IPCC_DisableReceiveChannel\n
* C2MR CH3OM LL_C2_IPCC_DisableReceiveChannel\n
* C2MR CH4OM LL_C2_IPCC_DisableReceiveChannel\n
* C2MR CH5OM LL_C2_IPCC_DisableReceiveChannel\n
* C2MR CH6OM LL_C2_IPCC_DisableReceiveChannel
* @param IPCCx IPCC Instance.
* @param Channel This parameter can be a combination of the following values:
* @arg @ref LL_IPCC_CHANNEL_1
* @arg @ref LL_IPCC_CHANNEL_2
* @arg @ref LL_IPCC_CHANNEL_3
* @arg @ref LL_IPCC_CHANNEL_4
* @arg @ref LL_IPCC_CHANNEL_5
* @arg @ref LL_IPCC_CHANNEL_6
* @retval None
*/
__STATIC_INLINE void LL_C2_IPCC_DisableReceiveChannel(IPCC_TypeDef *IPCCx, uint32_t Channel)
{
SET_BIT(IPCCx->C2MR, Channel);
}
/**
* @brief Check if Receive channel occupied interrupt for processor 2 is masked.
* @rmtoll C2MR CH1OM LL_C2_IPCC_IsEnabledReceiveChannel\n
* C2MR CH2OM LL_C2_IPCC_IsEnabledReceiveChannel\n
* C2MR CH3OM LL_C2_IPCC_IsEnabledReceiveChannel\n
* C2MR CH4OM LL_C2_IPCC_IsEnabledReceiveChannel\n
* C2MR CH5OM LL_C2_IPCC_IsEnabledReceiveChannel\n
* C2MR CH6OM LL_C2_IPCC_IsEnabledReceiveChannel
* @param IPCCx IPCC Instance.
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_IPCC_CHANNEL_1
* @arg @ref LL_IPCC_CHANNEL_2
* @arg @ref LL_IPCC_CHANNEL_3
* @arg @ref LL_IPCC_CHANNEL_4
* @arg @ref LL_IPCC_CHANNEL_5
* @arg @ref LL_IPCC_CHANNEL_6
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_C2_IPCC_IsEnabledReceiveChannel(IPCC_TypeDef const *const IPCCx, uint32_t Channel)
{
return ((READ_BIT(IPCCx->C2MR, Channel) != (Channel)) ? 1UL : 0UL);
}
/**
* @}
*/
/** @defgroup IPCC_LL_EF_FLAG_Management FLAG_Management
* @{
*/
/**
* @brief Clear IPCC receive channel status for processor 1.
* @note Associated with IPCC_C2TOC1SR.CHxF
* @rmtoll C1SCR CH1C LL_C1_IPCC_ClearFlag_CHx\n
* C1SCR CH2C LL_C1_IPCC_ClearFlag_CHx\n
* C1SCR CH3C LL_C1_IPCC_ClearFlag_CHx\n
* C1SCR CH4C LL_C1_IPCC_ClearFlag_CHx\n
* C1SCR CH5C LL_C1_IPCC_ClearFlag_CHx\n
* C1SCR CH6C LL_C1_IPCC_ClearFlag_CHx
* @param IPCCx IPCC Instance.
* @param Channel This parameter can be a combination of the following values:
* @arg @ref LL_IPCC_CHANNEL_1
* @arg @ref LL_IPCC_CHANNEL_2
* @arg @ref LL_IPCC_CHANNEL_3
* @arg @ref LL_IPCC_CHANNEL_4
* @arg @ref LL_IPCC_CHANNEL_5
* @arg @ref LL_IPCC_CHANNEL_6
* @retval None
*/
__STATIC_INLINE void LL_C1_IPCC_ClearFlag_CHx(IPCC_TypeDef *IPCCx, uint32_t Channel)
{
WRITE_REG(IPCCx->C1SCR, Channel);
}
/**
* @brief Set IPCC transmit channel status for processor 1.
* @note Associated with IPCC_C1TOC2SR.CHxF
* @rmtoll C1SCR CH1S LL_C1_IPCC_SetFlag_CHx\n
* C1SCR CH2S LL_C1_IPCC_SetFlag_CHx\n
* C1SCR CH3S LL_C1_IPCC_SetFlag_CHx\n
* C1SCR CH4S LL_C1_IPCC_SetFlag_CHx\n
* C1SCR CH5S LL_C1_IPCC_SetFlag_CHx\n
* C1SCR CH6S LL_C1_IPCC_SetFlag_CHx
* @param IPCCx IPCC Instance.
* @param Channel This parameter can be a combination of the following values:
* @arg @ref LL_IPCC_CHANNEL_1
* @arg @ref LL_IPCC_CHANNEL_2
* @arg @ref LL_IPCC_CHANNEL_3
* @arg @ref LL_IPCC_CHANNEL_4
* @arg @ref LL_IPCC_CHANNEL_5
* @arg @ref LL_IPCC_CHANNEL_6
* @retval None
*/
__STATIC_INLINE void LL_C1_IPCC_SetFlag_CHx(IPCC_TypeDef *IPCCx, uint32_t Channel)
{
WRITE_REG(IPCCx->C1SCR, Channel << IPCC_C1SCR_CH1S_Pos);
}
/**
* @brief Get channel status for processor 1.
* @rmtoll C1TOC2SR CH1F LL_C1_IPCC_IsActiveFlag_CHx\n
* C1TOC2SR CH2F LL_C1_IPCC_IsActiveFlag_CHx\n
* C1TOC2SR CH3F LL_C1_IPCC_IsActiveFlag_CHx\n
* C1TOC2SR CH4F LL_C1_IPCC_IsActiveFlag_CHx\n
* C1TOC2SR CH5F LL_C1_IPCC_IsActiveFlag_CHx\n
* C1TOC2SR CH6F LL_C1_IPCC_IsActiveFlag_CHx
* @param IPCCx IPCC Instance.
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_IPCC_CHANNEL_1
* @arg @ref LL_IPCC_CHANNEL_2
* @arg @ref LL_IPCC_CHANNEL_3
* @arg @ref LL_IPCC_CHANNEL_4
* @arg @ref LL_IPCC_CHANNEL_5
* @arg @ref LL_IPCC_CHANNEL_6
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_C1_IPCC_IsActiveFlag_CHx(IPCC_TypeDef const *const IPCCx, uint32_t Channel)
{
return ((READ_BIT(IPCCx->C1TOC2SR, Channel) == (Channel)) ? 1UL : 0UL);
}
/**
* @brief Clear IPCC receive channel status for processor 2.
* @note Associated with IPCC_C1TOC2SR.CHxF
* @rmtoll C2SCR CH1C LL_C2_IPCC_ClearFlag_CHx\n
* C2SCR CH2C LL_C2_IPCC_ClearFlag_CHx\n
* C2SCR CH3C LL_C2_IPCC_ClearFlag_CHx\n
* C2SCR CH4C LL_C2_IPCC_ClearFlag_CHx\n
* C2SCR CH5C LL_C2_IPCC_ClearFlag_CHx\n
* C2SCR CH6C LL_C2_IPCC_ClearFlag_CHx
* @param IPCCx IPCC Instance.
* @param Channel This parameter can be a combination of the following values:
* @arg @ref LL_IPCC_CHANNEL_1
* @arg @ref LL_IPCC_CHANNEL_2
* @arg @ref LL_IPCC_CHANNEL_3
* @arg @ref LL_IPCC_CHANNEL_4
* @arg @ref LL_IPCC_CHANNEL_5
* @arg @ref LL_IPCC_CHANNEL_6
* @retval None
*/
__STATIC_INLINE void LL_C2_IPCC_ClearFlag_CHx(IPCC_TypeDef *IPCCx, uint32_t Channel)
{
WRITE_REG(IPCCx->C2SCR, Channel);
}
/**
* @brief Set IPCC transmit channel status for processor 2.
* @note Associated with IPCC_C2TOC1SR.CHxF
* @rmtoll C2SCR CH1S LL_C2_IPCC_SetFlag_CHx\n
* C2SCR CH2S LL_C2_IPCC_SetFlag_CHx\n
* C2SCR CH3S LL_C2_IPCC_SetFlag_CHx\n
* C2SCR CH4S LL_C2_IPCC_SetFlag_CHx\n
* C2SCR CH5S LL_C2_IPCC_SetFlag_CHx\n
* C2SCR CH6S LL_C2_IPCC_SetFlag_CHx
* @param IPCCx IPCC Instance.
* @param Channel This parameter can be a combination of the following values:
* @arg @ref LL_IPCC_CHANNEL_1
* @arg @ref LL_IPCC_CHANNEL_2
* @arg @ref LL_IPCC_CHANNEL_3
* @arg @ref LL_IPCC_CHANNEL_4
* @arg @ref LL_IPCC_CHANNEL_5
* @arg @ref LL_IPCC_CHANNEL_6
* @retval None
*/
__STATIC_INLINE void LL_C2_IPCC_SetFlag_CHx(IPCC_TypeDef *IPCCx, uint32_t Channel)
{
WRITE_REG(IPCCx->C2SCR, Channel << IPCC_C2SCR_CH1S_Pos);
}
/**
* @brief Get channel status for processor 2.
* @rmtoll C2TOC1SR CH1F LL_C2_IPCC_IsActiveFlag_CHx\n
* C2TOC1SR CH2F LL_C2_IPCC_IsActiveFlag_CHx\n
* C2TOC1SR CH3F LL_C2_IPCC_IsActiveFlag_CHx\n
* C2TOC1SR CH4F LL_C2_IPCC_IsActiveFlag_CHx\n
* C2TOC1SR CH5F LL_C2_IPCC_IsActiveFlag_CHx\n
* C2TOC1SR CH6F LL_C2_IPCC_IsActiveFlag_CHx
* @param IPCCx IPCC Instance.
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_IPCC_CHANNEL_1
* @arg @ref LL_IPCC_CHANNEL_2
* @arg @ref LL_IPCC_CHANNEL_3
* @arg @ref LL_IPCC_CHANNEL_4
* @arg @ref LL_IPCC_CHANNEL_5
* @arg @ref LL_IPCC_CHANNEL_6
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_C2_IPCC_IsActiveFlag_CHx(IPCC_TypeDef const *const IPCCx, uint32_t Channel)
{
return ((READ_BIT(IPCCx->C2TOC1SR, Channel) == (Channel)) ? 1UL : 0UL);
}
/**
* @brief Get the number of supported channels.
* @param IPCCx IPCC Instance.
* @retval Number of supported channels.
*/
__STATIC_INLINE uint32_t LL_IPCC_GetChannelNumber(IPCC_TypeDef *IPCCx)
{
/* Added for compatibility with other STM32 series */
(void)(IPCCx); /* To avoid gcc/g++ warnings */
return 6U;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* defined(IPCC) */
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32WBxx_LL_IPCC_H */
|
