diff options
| author | Gaetan Bahl <gaetan.bahl@nxp.com> | 2022-05-17 19:15:51 +0300 |
|---|---|---|
| committer | Gaetan Bahl <gaetan.bahl@nxp.com> | 2022-06-01 19:39:00 +0300 |
| commit | 5d5515ea5b01c82bbe559029255f528082c4fce1 (patch) | |
| tree | 19fce4788ffef2570ca15e81e10403c04cd27dba | |
| parent | 03d9f144cb333057bb203cbecea3fc29bb336120 (diff) | |
neon: Fix out-of-shift errors when compiling certain float/double opcodes using neon
Setting the correct shift values solve the "out-of-shift" errors
and allow the following operators to successfully compile:
addf, subf, mulf, maxf, minf, cmpeqf, convfl, convlf, addd, subd, muld, divd
Fixes #33, #20, #2.
Signed-off-by: Gaetan Bahl <gaetan.bahl@nxp.com>
| -rw-r--r-- | orc/orcrules-neon.c | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/orc/orcrules-neon.c b/orc/orcrules-neon.c index a9c6bb0..aed2884 100644 --- a/orc/orcrules-neon.c +++ b/orc/orcrules-neon.c @@ -2859,16 +2859,16 @@ UNARY_NARROW(select0ql,"vmovn.i64",0xf3ba0200, "xtn", 0x0ea12800, 1) UNARY_NARROW(select0lw,"vmovn.i32",0xf3b60200, "xtn", 0x0e612800, 2) UNARY_NARROW(select0wb,"vmovn.i16",0xf3b20200, "xtn", 0x0e212800, 3) -BINARY(addf,"vadd.f32",0xf2000d00, "fadd", 0x0e20d400, 0) -BINARY(subf,"vsub.f32",0xf2200d00, "fsub", 0x0ea0d400, 0) -BINARY(mulf,"vmul.f32",0xf3000d10, "fmul", 0x2e20dc00, 0) -BINARY(maxf,"vmax.f32",0xf2000f00, "fmax", 0x0e20f400, 0) -BINARY(minf,"vmin.f32",0xf2200f00, "fmin", 0x0ea0f400, 0) -BINARY(cmpeqf,"vceq.f32",0xf2000e00, "fcmeq", 0x5e20e400, 0) +BINARY(addf,"vadd.f32",0xf2000d00, "fadd", 0x0e20d400, 1) +BINARY(subf,"vsub.f32",0xf2200d00, "fsub", 0x0ea0d400, 1) +BINARY(mulf,"vmul.f32",0xf3000d10, "fmul", 0x2e20dc00, 1) +BINARY(maxf,"vmax.f32",0xf2000f00, "fmax", 0x0e20f400, 1) +BINARY(minf,"vmin.f32",0xf2200f00, "fmin", 0x0ea0f400, 1) +BINARY(cmpeqf,"vceq.f32",0xf2000e00, "fcmeq", 0x5e20e400, 1) /* BINARY_R(cmpltf,"vclt.f32",0xf3200e00, "fcmlt", 0x5ef8e800, 1) */ /* BINARY_R(cmplef,"vcle.f32",0xf3000e00, "fcmle", 0x7ef8d800, 1) */ -UNARY(convfl,"vcvt.s32.f32",0xf3bb0700, "fcvtzs", 0x0ea1b800, 0) -UNARY(convlf,"vcvt.f32.s32",0xf3bb0600, "scvtf", 0x0e21d800, 0) +UNARY(convfl,"vcvt.s32.f32",0xf3bb0700, "fcvtzs", 0x0ea1b800, 1) +UNARY(convlf,"vcvt.f32.s32",0xf3bb0600, "scvtf", 0x0e21d800, 1) #define UNARY_VFP(opcode,insn_name,code,insn_name64,code64,vec_shift) \ static void \ @@ -2905,7 +2905,7 @@ orc_neon_rule_ ## opcode (OrcCompiler *p, void *user, OrcInstruction *insn) \ orc_neon64_emit_binary (p, insn_name64, code64, \ p->vars[insn->dest_args[0]], \ p->vars[insn->src_args[0]], \ - p->vars[insn->src_args[1]], vec_shift - 1); \ + p->vars[insn->src_args[1]], vec_shift); \ } else { \ ORC_COMPILER_ERROR(p, "not supported in AArch64 yet [%s %x]", (insn_name64), (code64)); \ } \ |