Implement SPV_INTEL_memory_access_aliasing extension (#265)

Modify headers to include declarations of tokens described
by this spec:

   https://github.com/intel/llvm/pull/3426

9 files changed, 169 insertions, 1 deletions

diff --git a/include/spirv/unified1/spirv.core.grammar.json b/include/spirv/unified1/spirv.core.grammar.json
index 766a4ed..8b98770 100644
--- a/include/spirv/unified1/spirv.core.grammar.json
+++ b/include/spirv/unified1/spirv.core.grammar.json
@@ -7870,6 +7870,43 @@
       "version" : "None"
     },
     {
+      "opname" : "OpAliasDomainDeclINTEL",
+      "class"  : "@exclude",
+      "opcode" : 5911,
+      "operands" : [
+        { "kind" : "IdResult"},
+        { "kind" : "IdRef", "quantifier" : "?", "name" : "'Name'" }
+      ],
+      "capabilities" : [ "MemoryAccessAliasingINTEL" ],
+      "extensions" : [ "SPV_INTEL_memory_access_aliasing" ],
+      "version" : "None"
+    },
+    {
+      "opname" : "OpAliasScopeDeclINTEL",
+      "class"  : "@exclude",
+      "opcode" : 5912,
+      "operands" : [
+        { "kind" : "IdResult"},
+        { "kind" : "IdRef", "name" : "'Alias Domain'"},
+        { "kind" : "IdRef", "quantifier" : "?", "name" : "'Name'" }
+      ],
+      "capabilities" : [ "MemoryAccessAliasingINTEL" ],
+      "extensions" : [ "SPV_INTEL_memory_access_aliasing" ],
+      "version" : "None"
+    },
+    {
+      "opname" : "OpAliasScopeListDeclINTEL",
+      "class"  : "@exclude",
+      "opcode" : 5913,
+      "operands" : [
+        { "kind" : "IdResult"},
+        { "kind" : "IdRef", "quantifier" : "*", "name" : "'AliasScope1, AliasScope2, ...'" }
+      ],
+      "capabilities" : [ "MemoryAccessAliasingINTEL" ],
+      "extensions" : [ "SPV_INTEL_memory_access_aliasing" ],
+      "version" : "None"
+    },
+    {
       "opname" : "OpFixedSqrtINTEL",
       "class"  : "@exclude",
       "opcode" : 5923,
@@ -9090,6 +9127,26 @@
           "capabilities" : [ "VulkanMemoryModel" ],
           "extensions" : [ "SPV_KHR_vulkan_memory_model" ],
           "version" : "1.5"
+        },
+        {
+          "enumerant" : "AliasScopeINTELMask",
+          "value" : "0x10000",
+          "parameters" : [
+            { "kind" : "IdRef" }
+          ],
+          "capabilities" : [ "MemoryAccessAliasingINTEL" ],
+          "extensions" : [ "SPV_INTEL_memory_access_aliasing" ],
+          "version" : "None"
+        },
+        {
+          "enumerant" : "NoAliasINTELMask",
+          "parameters" : [
+            { "kind" : "IdRef" }
+          ],
+          "value" : "0x20000",
+          "capabilities" : [ "MemoryAccessAliasingINTEL" ],
+          "extensions" : [ "SPV_INTEL_memory_access_aliasing" ],
+          "version" : "None"
         }
       ]
     },
@@ -11580,6 +11637,24 @@
           "version" : "None"
         },
         {
+          "enumerant" : "AliasScopeINTEL",
+          "value" : 5914,
+          "parameters" : [
+            { "kind" : "IdRef", "name" : "'Aliasing Scopes List'" }
+          ],
+          "capabilities" : [ "MemoryAccessAliasingINTEL" ],
+          "version" : "None"
+        },
+        {
+          "enumerant" : "NoAliasINTEL",
+          "value" : 5915,
+          "parameters" : [
+            { "kind" : "IdRef", "name" : "'Aliasing Scopes List'" }
+          ],
+          "capabilities" : [ "MemoryAccessAliasingINTEL" ],
+          "version" : "None"
+        },
+        {
           "enumerant" : "BufferLocationINTEL",
           "value" : 5921,
           "parameters" : [
@@ -13678,6 +13753,12 @@
           "version" : "None"
         },
         {
+          "enumerant" : "MemoryAccessAliasingINTEL",
+          "value" : 5910,
+          "extensions" : [ "SPV_INTEL_memory_access_aliasing" ],
+          "version" : "None"
+        },
+        {
           "enumerant" : "FPGABufferLocationINTEL",
           "value" : 5920,
           "extensions" : [ "SPV_INTEL_fpga_buffer_location" ],
diff --git a/include/spirv/unified1/spirv.cs b/include/spirv/unified1/spirv.cs
index 9cf00ec..9e2bccd 100644
--- a/include/spirv/unified1/spirv.cs
+++ b/include/spirv/unified1/spirv.cs
@@ -540,6 +540,8 @@ namespace Spv
             PrefetchINTEL = 5902,
             StallEnableINTEL = 5905,
             FuseLoopsInFunctionINTEL = 5907,
+            AliasScopeINTEL = 5914,
+            NoAliasINTEL = 5915,
             BufferLocationINTEL = 5921,
             IOPipeStorageINTEL = 5944,
             FunctionFloatingPointModeINTEL = 6080,
@@ -802,6 +804,8 @@ namespace Spv
             MakePointerVisibleKHR = 4,
             NonPrivatePointer = 5,
             NonPrivatePointerKHR = 5,
+            AliasScopeINTELMask = 16,
+            NoAliasINTELMask = 17,
         }
 
         public enum MemoryAccessMask
@@ -816,6 +820,8 @@ namespace Spv
             MakePointerVisibleKHR = 0x00000010,
             NonPrivatePointer = 0x00000020,
             NonPrivatePointerKHR = 0x00000020,
+            AliasScopeINTELMask = 0x00010000,
+            NoAliasINTELMask = 0x00020000,
         }
 
         public enum Scope
@@ -1059,6 +1065,7 @@ namespace Spv
             FPGAMemoryAccessesINTEL = 5898,
             FPGAClusterAttributesINTEL = 5904,
             LoopFuseINTEL = 5906,
+            MemoryAccessAliasingINTEL = 5910,
             FPGABufferLocationINTEL = 5920,
             ArbitraryPrecisionFixedPointINTEL = 5922,
             USMStorageClassesINTEL = 5935,
@@ -1803,6 +1810,9 @@ namespace Spv
             OpArbitraryFloatPowRINTEL = 5881,
             OpArbitraryFloatPowNINTEL = 5882,
             OpLoopControlINTEL = 5887,
+            OpAliasDomainDeclINTEL = 5911,
+            OpAliasScopeDeclINTEL = 5912,
+            OpAliasScopeListDeclINTEL = 5913,
             OpFixedSqrtINTEL = 5923,
             OpFixedRecipINTEL = 5924,
             OpFixedRsqrtINTEL = 5925,
diff --git a/include/spirv/unified1/spirv.h b/include/spirv/unified1/spirv.h
index c15736e..3d617da 100644
--- a/include/spirv/unified1/spirv.h
+++ b/include/spirv/unified1/spirv.h
@@ -546,6 +546,8 @@ typedef enum SpvDecoration_ {
     SpvDecorationPrefetchINTEL = 5902,
     SpvDecorationStallEnableINTEL = 5905,
     SpvDecorationFuseLoopsInFunctionINTEL = 5907,
+    SpvDecorationAliasScopeINTEL = 5914,
+    SpvDecorationNoAliasINTEL = 5915,
     SpvDecorationBufferLocationINTEL = 5921,
     SpvDecorationIOPipeStorageINTEL = 5944,
     SpvDecorationFunctionFloatingPointModeINTEL = 6080,
@@ -804,6 +806,8 @@ typedef enum SpvMemoryAccessShift_ {
     SpvMemoryAccessMakePointerVisibleKHRShift = 4,
     SpvMemoryAccessNonPrivatePointerShift = 5,
     SpvMemoryAccessNonPrivatePointerKHRShift = 5,
+    SpvMemoryAccessAliasScopeINTELMaskShift = 16,
+    SpvMemoryAccessNoAliasINTELMaskShift = 17,
     SpvMemoryAccessMax = 0x7fffffff,
 } SpvMemoryAccessShift;
 
@@ -818,6 +822,8 @@ typedef enum SpvMemoryAccessMask_ {
     SpvMemoryAccessMakePointerVisibleKHRMask = 0x00000010,
     SpvMemoryAccessNonPrivatePointerMask = 0x00000020,
     SpvMemoryAccessNonPrivatePointerKHRMask = 0x00000020,
+    SpvMemoryAccessAliasScopeINTELMaskMask = 0x00010000,
+    SpvMemoryAccessNoAliasINTELMaskMask = 0x00020000,
 } SpvMemoryAccessMask;
 
 typedef enum SpvScope_ {
@@ -1059,6 +1065,7 @@ typedef enum SpvCapability_ {
     SpvCapabilityFPGAMemoryAccessesINTEL = 5898,
     SpvCapabilityFPGAClusterAttributesINTEL = 5904,
     SpvCapabilityLoopFuseINTEL = 5906,
+    SpvCapabilityMemoryAccessAliasingINTEL = 5910,
     SpvCapabilityFPGABufferLocationINTEL = 5920,
     SpvCapabilityArbitraryPrecisionFixedPointINTEL = 5922,
     SpvCapabilityUSMStorageClassesINTEL = 5935,
@@ -1801,6 +1808,9 @@ typedef enum SpvOp_ {
     SpvOpArbitraryFloatPowRINTEL = 5881,
     SpvOpArbitraryFloatPowNINTEL = 5882,
     SpvOpLoopControlINTEL = 5887,
+    SpvOpAliasDomainDeclINTEL = 5911,
+    SpvOpAliasScopeDeclINTEL = 5912,
+    SpvOpAliasScopeListDeclINTEL = 5913,
     SpvOpFixedSqrtINTEL = 5923,
     SpvOpFixedRecipINTEL = 5924,
     SpvOpFixedRsqrtINTEL = 5925,
@@ -2452,6 +2462,9 @@ inline void SpvHasResultAndType(SpvOp opcode, bool *hasResult, bool *hasResultTy
     case SpvOpArbitraryFloatPowRINTEL: *hasResult = true; *hasResultType = true; break;
     case SpvOpArbitraryFloatPowNINTEL: *hasResult = true; *hasResultType = true; break;
     case SpvOpLoopControlINTEL: *hasResult = false; *hasResultType = false; break;
+    case SpvOpAliasDomainDeclINTEL: *hasResult = true; *hasResultType = false; break;
+    case SpvOpAliasScopeDeclINTEL: *hasResult = true; *hasResultType = false; break;
+    case SpvOpAliasScopeListDeclINTEL: *hasResult = true; *hasResultType = false; break;
     case SpvOpFixedSqrtINTEL: *hasResult = true; *hasResultType = true; break;
     case SpvOpFixedRecipINTEL: *hasResult = true; *hasResultType = true; break;
     case SpvOpFixedRsqrtINTEL: *hasResult = true; *hasResultType = true; break;
diff --git a/include/spirv/unified1/spirv.hpp b/include/spirv/unified1/spirv.hpp
index 3d500eb..97a5101 100644
--- a/include/spirv/unified1/spirv.hpp
+++ b/include/spirv/unified1/spirv.hpp
@@ -542,6 +542,8 @@ enum Decoration {
     DecorationPrefetchINTEL = 5902,
     DecorationStallEnableINTEL = 5905,
     DecorationFuseLoopsInFunctionINTEL = 5907,
+    DecorationAliasScopeINTEL = 5914,
+    DecorationNoAliasINTEL = 5915,
     DecorationBufferLocationINTEL = 5921,
     DecorationIOPipeStorageINTEL = 5944,
     DecorationFunctionFloatingPointModeINTEL = 6080,
@@ -800,6 +802,8 @@ enum MemoryAccessShift {
     MemoryAccessMakePointerVisibleKHRShift = 4,
     MemoryAccessNonPrivatePointerShift = 5,
     MemoryAccessNonPrivatePointerKHRShift = 5,
+    MemoryAccessAliasScopeINTELMaskShift = 16,
+    MemoryAccessNoAliasINTELMaskShift = 17,
     MemoryAccessMax = 0x7fffffff,
 };
 
@@ -814,6 +818,8 @@ enum MemoryAccessMask {
     MemoryAccessMakePointerVisibleKHRMask = 0x00000010,
     MemoryAccessNonPrivatePointerMask = 0x00000020,
     MemoryAccessNonPrivatePointerKHRMask = 0x00000020,
+    MemoryAccessAliasScopeINTELMaskMask = 0x00010000,
+    MemoryAccessNoAliasINTELMaskMask = 0x00020000,
 };
 
 enum Scope {
@@ -1055,6 +1061,7 @@ enum Capability {
     CapabilityFPGAMemoryAccessesINTEL = 5898,
     CapabilityFPGAClusterAttributesINTEL = 5904,
     CapabilityLoopFuseINTEL = 5906,
+    CapabilityMemoryAccessAliasingINTEL = 5910,
     CapabilityFPGABufferLocationINTEL = 5920,
     CapabilityArbitraryPrecisionFixedPointINTEL = 5922,
     CapabilityUSMStorageClassesINTEL = 5935,
@@ -1797,6 +1804,9 @@ enum Op {
     OpArbitraryFloatPowRINTEL = 5881,
     OpArbitraryFloatPowNINTEL = 5882,
     OpLoopControlINTEL = 5887,
+    OpAliasDomainDeclINTEL = 5911,
+    OpAliasScopeDeclINTEL = 5912,
+    OpAliasScopeListDeclINTEL = 5913,
     OpFixedSqrtINTEL = 5923,
     OpFixedRecipINTEL = 5924,
     OpFixedRsqrtINTEL = 5925,
@@ -2448,6 +2458,9 @@ inline void HasResultAndType(Op opcode, bool *hasResult, bool *hasResultType) {
     case OpArbitraryFloatPowRINTEL: *hasResult = true; *hasResultType = true; break;
     case OpArbitraryFloatPowNINTEL: *hasResult = true; *hasResultType = true; break;
     case OpLoopControlINTEL: *hasResult = false; *hasResultType = false; break;
+    case OpAliasDomainDeclINTEL: *hasResult = true; *hasResultType = false; break;
+    case OpAliasScopeDeclINTEL: *hasResult = true; *hasResultType = false; break;
+    case OpAliasScopeListDeclINTEL: *hasResult = true; *hasResultType = false; break;
     case OpFixedSqrtINTEL: *hasResult = true; *hasResultType = true; break;
     case OpFixedRecipINTEL: *hasResult = true; *hasResultType = true; break;
     case OpFixedRsqrtINTEL: *hasResult = true; *hasResultType = true; break;
diff --git a/include/spirv/unified1/spirv.hpp11 b/include/spirv/unified1/spirv.hpp11
index f1fd764..a5de0be 100644
--- a/include/spirv/unified1/spirv.hpp11
+++ b/include/spirv/unified1/spirv.hpp11
@@ -542,6 +542,8 @@ enum class Decoration : unsigned {
     PrefetchINTEL = 5902,
     StallEnableINTEL = 5905,
     FuseLoopsInFunctionINTEL = 5907,
+    AliasScopeINTEL = 5914,
+    NoAliasINTEL = 5915,
     BufferLocationINTEL = 5921,
     IOPipeStorageINTEL = 5944,
     FunctionFloatingPointModeINTEL = 6080,
@@ -800,6 +802,8 @@ enum class MemoryAccessShift : unsigned {
     MakePointerVisibleKHR = 4,
     NonPrivatePointer = 5,
     NonPrivatePointerKHR = 5,
+    AliasScopeINTELMask = 16,
+    NoAliasINTELMask = 17,
     Max = 0x7fffffff,
 };
 
@@ -814,6 +818,8 @@ enum class MemoryAccessMask : unsigned {
     MakePointerVisibleKHR = 0x00000010,
     NonPrivatePointer = 0x00000020,
     NonPrivatePointerKHR = 0x00000020,
+    AliasScopeINTELMask = 0x00010000,
+    NoAliasINTELMask = 0x00020000,
 };
 
 enum class Scope : unsigned {
@@ -1055,6 +1061,7 @@ enum class Capability : unsigned {
     FPGAMemoryAccessesINTEL = 5898,
     FPGAClusterAttributesINTEL = 5904,
     LoopFuseINTEL = 5906,
+    MemoryAccessAliasingINTEL = 5910,
     FPGABufferLocationINTEL = 5920,
     ArbitraryPrecisionFixedPointINTEL = 5922,
     USMStorageClassesINTEL = 5935,
@@ -1797,6 +1804,9 @@ enum class Op : unsigned {
     OpArbitraryFloatPowRINTEL = 5881,
     OpArbitraryFloatPowNINTEL = 5882,
     OpLoopControlINTEL = 5887,
+    OpAliasDomainDeclINTEL = 5911,
+    OpAliasScopeDeclINTEL = 5912,
+    OpAliasScopeListDeclINTEL = 5913,
     OpFixedSqrtINTEL = 5923,
     OpFixedRecipINTEL = 5924,
     OpFixedRsqrtINTEL = 5925,
@@ -2448,6 +2458,9 @@ inline void HasResultAndType(Op opcode, bool *hasResult, bool *hasResultType) {
     case Op::OpArbitraryFloatPowRINTEL: *hasResult = true; *hasResultType = true; break;
     case Op::OpArbitraryFloatPowNINTEL: *hasResult = true; *hasResultType = true; break;
     case Op::OpLoopControlINTEL: *hasResult = false; *hasResultType = false; break;
+    case Op::OpAliasDomainDeclINTEL: *hasResult = true; *hasResultType = false; break;
+    case Op::OpAliasScopeDeclINTEL: *hasResult = true; *hasResultType = false; break;
+    case Op::OpAliasScopeListDeclINTEL: *hasResult = true; *hasResultType = false; break;
     case Op::OpFixedSqrtINTEL: *hasResult = true; *hasResultType = true; break;
     case Op::OpFixedRecipINTEL: *hasResult = true; *hasResultType = true; break;
     case Op::OpFixedRsqrtINTEL: *hasResult = true; *hasResultType = true; break;
diff --git a/include/spirv/unified1/spirv.json b/include/spirv/unified1/spirv.json
index e80d3bd..34d157b 100644
--- a/include/spirv/unified1/spirv.json
+++ b/include/spirv/unified1/spirv.json
@@ -568,6 +568,8 @@
                     "PrefetchINTEL": 5902,
                     "StallEnableINTEL": 5905,
                     "FuseLoopsInFunctionINTEL": 5907,
+                    "AliasScopeINTEL": 5914,
+                    "NoAliasINTEL": 5915,
                     "BufferLocationINTEL": 5921,
                     "IOPipeStorageINTEL": 5944,
                     "FunctionFloatingPointModeINTEL": 6080,
@@ -786,7 +788,9 @@
                     "MakePointerVisible": 4,
                     "MakePointerVisibleKHR": 4,
                     "NonPrivatePointer": 5,
-                    "NonPrivatePointerKHR": 5
+                    "NonPrivatePointerKHR": 5,
+                    "AliasScopeINTELMask": 16,
+                    "NoAliasINTELMask": 17
                 }
             },
             {
@@ -1039,6 +1043,7 @@
                     "FPGAMemoryAccessesINTEL": 5898,
                     "FPGAClusterAttributesINTEL": 5904,
                     "LoopFuseINTEL": 5906,
+                    "MemoryAccessAliasingINTEL": 5910,
                     "FPGABufferLocationINTEL": 5920,
                     "ArbitraryPrecisionFixedPointINTEL": 5922,
                     "USMStorageClassesINTEL": 5935,
@@ -1792,6 +1797,9 @@
                     "OpArbitraryFloatPowRINTEL": 5881,
                     "OpArbitraryFloatPowNINTEL": 5882,
                     "OpLoopControlINTEL": 5887,
+                    "OpAliasDomainDeclINTEL": 5911,
+                    "OpAliasScopeDeclINTEL": 5912,
+                    "OpAliasScopeListDeclINTEL": 5913,
                     "OpFixedSqrtINTEL": 5923,
                     "OpFixedRecipINTEL": 5924,
                     "OpFixedRsqrtINTEL": 5925,
diff --git a/include/spirv/unified1/spirv.lua b/include/spirv/unified1/spirv.lua
index 2f5e803..6d512a6 100644
--- a/include/spirv/unified1/spirv.lua
+++ b/include/spirv/unified1/spirv.lua
@@ -515,6 +515,8 @@ spv = {
         PrefetchINTEL = 5902,
         StallEnableINTEL = 5905,
         FuseLoopsInFunctionINTEL = 5907,
+        AliasScopeINTEL = 5914,
+        NoAliasINTEL = 5915,
         BufferLocationINTEL = 5921,
         IOPipeStorageINTEL = 5944,
         FunctionFloatingPointModeINTEL = 6080,
@@ -767,6 +769,8 @@ spv = {
         MakePointerVisibleKHR = 4,
         NonPrivatePointer = 5,
         NonPrivatePointerKHR = 5,
+        AliasScopeINTELMask = 16,
+        NoAliasINTELMask = 17,
     },
 
     MemoryAccessMask = {
@@ -780,6 +784,8 @@ spv = {
         MakePointerVisibleKHR = 0x00000010,
         NonPrivatePointer = 0x00000020,
         NonPrivatePointerKHR = 0x00000020,
+        AliasScopeINTELMask = 0x00010000,
+        NoAliasINTELMask = 0x00020000,
     },
 
     Scope = {
@@ -1017,6 +1023,7 @@ spv = {
         FPGAMemoryAccessesINTEL = 5898,
         FPGAClusterAttributesINTEL = 5904,
         LoopFuseINTEL = 5906,
+        MemoryAccessAliasingINTEL = 5910,
         FPGABufferLocationINTEL = 5920,
         ArbitraryPrecisionFixedPointINTEL = 5922,
         USMStorageClassesINTEL = 5935,
@@ -1748,6 +1755,9 @@ spv = {
         OpArbitraryFloatPowRINTEL = 5881,
         OpArbitraryFloatPowNINTEL = 5882,
         OpLoopControlINTEL = 5887,
+        OpAliasDomainDeclINTEL = 5911,
+        OpAliasScopeDeclINTEL = 5912,
+        OpAliasScopeListDeclINTEL = 5913,
         OpFixedSqrtINTEL = 5923,
         OpFixedRecipINTEL = 5924,
         OpFixedRsqrtINTEL = 5925,
diff --git a/include/spirv/unified1/spirv.py b/include/spirv/unified1/spirv.py
index 7aee89f..66cde27 100644
--- a/include/spirv/unified1/spirv.py
+++ b/include/spirv/unified1/spirv.py
@@ -515,6 +515,8 @@ spv = {
         'PrefetchINTEL' : 5902,
         'StallEnableINTEL' : 5905,
         'FuseLoopsInFunctionINTEL' : 5907,
+        'AliasScopeINTEL' : 5914,
+        'NoAliasINTEL' : 5915,
         'BufferLocationINTEL' : 5921,
         'IOPipeStorageINTEL' : 5944,
         'FunctionFloatingPointModeINTEL' : 6080,
@@ -767,6 +769,8 @@ spv = {
         'MakePointerVisibleKHR' : 4,
         'NonPrivatePointer' : 5,
         'NonPrivatePointerKHR' : 5,
+        'AliasScopeINTELMask' : 16,
+        'NoAliasINTELMask' : 17,
     },
 
     'MemoryAccessMask' : {
@@ -780,6 +784,8 @@ spv = {
         'MakePointerVisibleKHR' : 0x00000010,
         'NonPrivatePointer' : 0x00000020,
         'NonPrivatePointerKHR' : 0x00000020,
+        'AliasScopeINTELMask' : 0x00010000,
+        'NoAliasINTELMask' : 0x00020000,
     },
 
     'Scope' : {
@@ -1017,6 +1023,7 @@ spv = {
         'FPGAMemoryAccessesINTEL' : 5898,
         'FPGAClusterAttributesINTEL' : 5904,
         'LoopFuseINTEL' : 5906,
+        'MemoryAccessAliasingINTEL' : 5910,
         'FPGABufferLocationINTEL' : 5920,
         'ArbitraryPrecisionFixedPointINTEL' : 5922,
         'USMStorageClassesINTEL' : 5935,
@@ -1748,6 +1755,9 @@ spv = {
         'OpArbitraryFloatPowRINTEL' : 5881,
         'OpArbitraryFloatPowNINTEL' : 5882,
         'OpLoopControlINTEL' : 5887,
+        'OpAliasDomainDeclINTEL' : 5911,
+        'OpAliasScopeDeclINTEL' : 5912,
+        'OpAliasScopeListDeclINTEL' : 5913,
         'OpFixedSqrtINTEL' : 5923,
         'OpFixedRecipINTEL' : 5924,
         'OpFixedRsqrtINTEL' : 5925,
diff --git a/include/spirv/unified1/spv.d b/include/spirv/unified1/spv.d
index a17e63d..c9b443c 100644
--- a/include/spirv/unified1/spv.d
+++ b/include/spirv/unified1/spv.d
@@ -543,6 +543,8 @@ enum Decoration : uint
     PrefetchINTEL = 5902,
     StallEnableINTEL = 5905,
     FuseLoopsInFunctionINTEL = 5907,
+    AliasScopeINTEL = 5914,
+    NoAliasINTEL = 5915,
     BufferLocationINTEL = 5921,
     IOPipeStorageINTEL = 5944,
     FunctionFloatingPointModeINTEL = 6080,
@@ -805,6 +807,8 @@ enum MemoryAccessShift : uint
     MakePointerVisibleKHR = 4,
     NonPrivatePointer = 5,
     NonPrivatePointerKHR = 5,
+    AliasScopeINTELMask = 16,
+    NoAliasINTELMask = 17,
 }
 
 enum MemoryAccessMask : uint
@@ -819,6 +823,8 @@ enum MemoryAccessMask : uint
     MakePointerVisibleKHR = 0x00000010,
     NonPrivatePointer = 0x00000020,
     NonPrivatePointerKHR = 0x00000020,
+    AliasScopeINTELMask = 0x00010000,
+    NoAliasINTELMask = 0x00020000,
 }
 
 enum Scope : uint
@@ -1062,6 +1068,7 @@ enum Capability : uint
     FPGAMemoryAccessesINTEL = 5898,
     FPGAClusterAttributesINTEL = 5904,
     LoopFuseINTEL = 5906,
+    MemoryAccessAliasingINTEL = 5910,
     FPGABufferLocationINTEL = 5920,
     ArbitraryPrecisionFixedPointINTEL = 5922,
     USMStorageClassesINTEL = 5935,
@@ -1806,6 +1813,9 @@ enum Op : uint
     OpArbitraryFloatPowRINTEL = 5881,
     OpArbitraryFloatPowNINTEL = 5882,
     OpLoopControlINTEL = 5887,
+    OpAliasDomainDeclINTEL = 5911,
+    OpAliasScopeDeclINTEL = 5912,
+    OpAliasScopeListDeclINTEL = 5913,
     OpFixedSqrtINTEL = 5923,
     OpFixedRecipINTEL = 5924,
     OpFixedRsqrtINTEL = 5925,