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github.com/KhronosGroup/SPIRV-Headers.git - Unnamed repository; edit this file 'description' to name the repository.
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path: root/include/spirv/spir-v.xml
AgeCommit message (Expand)Author
2022-10-04registered ID for ShadyHugo Devillers
2022-04-18Register magic number for SPIRVSmithRayan Hatout
2022-01-28Reserve enum range for MSP extensionsMikko Rasa
2022-01-17Allocate additional loop control bit for upcoming Intel extensionMichael Kinsner
2021-12-21Merge branch 'master' into add_shader_writerSylvain Doremus
2021-12-08Merge pull request #256 from jjfumero/tornadovm-generatorRaun Krisch
2021-11-30Change contact for ArmKevin Petit
2021-11-23Register TornadoVM SPIRV Beehive Tookit GeneratorJuan Fumero
2021-11-16Add ShaderWriter as SPIR-V generation tool.DragonJoker
2021-10-13reserve SPIR-V enum block for Intel extensionsBen Ashbaugh
2021-10-08Merge pull request #245 from pmistryNV/nonconstoffsetJohn Kessenich
2021-10-06Define a new Image operand bit mask for non constant offsetsPankaj Mistry
2021-10-01Register Magic Num for Skia SkSL SPIR-V Generatoregdaniel
2021-08-11Merge pull request #226 from clayengine/masterRaun Krisch
2021-06-29Clay is an internal framework of Tellusim Technologies Inc.Alexander Zapryagaev
2021-06-24reserve value rangeWyvernWang
2021-06-08Allocate additional Intel vendor extension enum blocksMichael Kinsner
2021-06-02Fix xml entry for SpvGenTwo generatorAlan Baker
2021-05-30Add SpvGenTwo to vendor IDsFabian Wahlster
2021-05-12Reserve loop control bit for upcoming trip count (min,max,avg) controlMichael Kinsner
2021-04-09Add generator ID for MSP shader compilerMikko Rasa
2021-03-25Add xml section for memory operand bit allocation tracking, and reserve two b...Michael Kinsner
2021-02-14Add Naga as SPIR-V generation toolDzmitry Malyshau
2021-01-06add function control bitfield reservation sectionBen Ashbaugh
2020-11-05Reserve additional loop control bit for Intel extension (NoFusionINTEL) (#175)Mike Kinsner
2020-11-02Add EmbarkStudios/rust-gpu to vendor list. (#174)XAMPPRocky
2020-10-12 Register the Xenia emulator as a generator (#171)Triang3l
2020-09-27Register the Messiah SPIR-V CodeGen (#169)Yuwen Wu
2020-09-10Register the ANGLE compiler (#168)Shahbaz Youssefi
2020-08-03Reserve SPIR-V token range for upcoming Intel extensions. (#165)1.5.3.reservations1Mariusz Merecki
2020-07-29Update the registry in spir-v.xml to modernize and split out opcodes. (#156)John Kessenich
2020-06-26Register the Tint compilerdan sinclair
2020-06-01spir-v.xml: Use plain ASCII quotes in commentDavid Neto
2020-05-25Propose bit allocation mechanism for the FP Fast Math Mode bitfield, followin...Michael Kinsner
2020-02-07Allocate three bits for upcoming Intel extensionMichael Kinsner
2019-11-20Off-by-one errorsTobski
2019-11-20Reserve a new block of 64 opcodesTobski
2019-07-12Reserve additional loop control bit for upcoming update to SPV_INTEL_fpga_loo...Michael Kinsner
2019-06-15Reserve ID 23 for MLIR SPIR-V SerializerLei Zhang
2019-05-27Proposed LoopControl bitfield allocation mechanism in spir-v.xmlMichael Kinsner
2019-05-23Reserve token range for CodeplayVictor Lomuller
2019-04-20Reserve generator 21 for ClspvDavid Neto
2019-03-14Update Codeplay's contact detailsVictor Lomuller
2019-02-26Reserve double SPIR-V enum block for upcoming Intel FPGA extensionMichael Kinsner
2018-11-28Add W3C WebGPU WHLSL tool identifierDean Jackson
2018-05-03Clay Shader CompilerClay Engine
2018-03-29reserve 2x SPIR-V enum blocks for upcoming Intel extensionsbashbaug
2018-01-31Register the VKD3D Shader CompilerJózef Kucia
2017-12-01Reserve token range for GoogleDavid Neto
2017-08-30Register the Khronos SPIRV-Tools LinkerDavid Neto
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