diff options
author | Ivan Maidanski <ivmai@mail.ru> | 2013-04-08 23:52:44 +0400 |
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committer | Ivan Maidanski <ivmai@mail.ru> | 2013-04-08 23:53:15 +0400 |
commit | ce4a44ca4a1acfb2f6ee44d52993d894dffe7b6f (patch) | |
tree | bc6f5e614fb3260b17eef2fd7cd222006ad5657d | |
parent | 60c203ca55d378c59b416a26570dbfdaba639b80 (diff) |
Add comment about double-wide load/store on x86_64 (GCC)
* src/atomic_ops/sysdeps/gcc/x86.h: Add comment about AO_double_load
and AO_double_store implementation in 64-bit mode; remove the
corresponding TODO item.
-rw-r--r-- | src/atomic_ops/sysdeps/gcc/x86.h | 13 |
1 files changed, 12 insertions, 1 deletions
diff --git a/src/atomic_ops/sysdeps/gcc/x86.h b/src/atomic_ops/sysdeps/gcc/x86.h index 9ce3949..62b50c9 100644 --- a/src/atomic_ops/sysdeps/gcc/x86.h +++ b/src/atomic_ops/sysdeps/gcc/x86.h @@ -282,7 +282,18 @@ AO_fetch_compare_and_swap_full(volatile AO_t *addr, AO_t old_val, } # define AO_HAVE_int_fetch_and_add_full -/* TODO: Implement double_load/store. */ + /* The Intel and AMD Architecture Programmer Manuals state roughly */ + /* the following: */ + /* - CMPXCHG16B (with a LOCK prefix) can be used to perform 16-byte */ + /* atomic accesses in 64-bit mode (with certain alignment */ + /* restrictions); */ + /* - SSE instructions that access data larger than a quadword (like */ + /* MOVDQA) may be implemented using multiple memory accesses; */ + /* - LOCK prefix causes an invalid-opcode exception when used with */ + /* 128-bit media (SSE) instructions. */ + /* Thus, currently, the only way to implement lock-free double_load */ + /* and double_store on x86_64 is to use CMPXCHG16B (if available). */ + /* TODO: Test some gcc macro to detect presence of cmpxchg16b. */ # ifdef AO_CMPXCHG16B_AVAILABLE |