diff options
author | Ivan Maidanski <ivmai@mail.ru> | 2013-08-17 11:48:59 +0400 |
---|---|---|
committer | Ivan Maidanski <ivmai@mail.ru> | 2013-08-17 13:30:32 +0400 |
commit | db2eef2f6e44c06e3a50b50a494dc242e4669d68 (patch) | |
tree | 50a3adcc7f4b0d00f00e2b9fd1b60e2b0ccc1ea2 | |
parent | 546d513d60c1612549f00590c0cc07def5385af9 (diff) |
Fix ARMv7 LDREXD/STREXD double-wide operand specification (GCC/Clang)
* src/atomic_ops/sysdeps/gcc/arm.h (AO_double_load, AO_double_store,
AO_double_compare_and_swap): Specify that LDREXD and STREXD use 2
adjacent registers (thus preventing Clang3.3 from register allocation
failures leading to "registers may not be the same" or
"even register required" GAS errors).
-rw-r--r-- | src/atomic_ops/sysdeps/gcc/arm.h | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/src/atomic_ops/sysdeps/gcc/arm.h b/src/atomic_ops/sysdeps/gcc/arm.h index 18a6355..a2cca02 100644 --- a/src/atomic_ops/sysdeps/gcc/arm.h +++ b/src/atomic_ops/sysdeps/gcc/arm.h @@ -499,7 +499,7 @@ AO_fetch_compare_and_swap(volatile AO_t *addr, AO_t old_val, AO_t new_val) /* AO_THUMB_GO_ARM is empty. */ __asm__ __volatile__("@AO_double_load\n" - " ldrexd %0, [%1]" + " ldrexd %0, %H0, [%1]" : "=&r" (result.AO_whole) : "r" (addr) /* : no clobber */); @@ -516,8 +516,8 @@ AO_fetch_compare_and_swap(volatile AO_t *addr, AO_t old_val, AO_t new_val) do { /* AO_THUMB_GO_ARM is empty. */ __asm__ __volatile__("@AO_double_store\n" - " ldrexd %0, [%3]\n" - " strexd %1, %4, [%3]" + " ldrexd %0, %H0, [%3]\n" + " strexd %1, %4, %H4, [%3]" : "=&r" (old_val.AO_whole), "=&r" (status), "+m" (*addr) : "r" (addr), "r" (new_val.AO_whole) : "cc"); @@ -535,14 +535,14 @@ AO_fetch_compare_and_swap(volatile AO_t *addr, AO_t old_val, AO_t new_val) do { /* AO_THUMB_GO_ARM is empty. */ __asm__ __volatile__("@AO_double_compare_and_swap\n" - " ldrexd %0, [%1]\n" /* get original to r1 & r2 */ + " ldrexd %0, %H0, [%1]\n" /* get original to r1 & r2 */ : "=&r"(tmp) : "r"(addr) /* : no clobber */); if (tmp != old_val.AO_whole) break; __asm__ __volatile__( - " strexd %0, %2, [%3]\n" /* store new one if matched */ + " strexd %0, %2, %H2, [%3]\n" /* store new one if matched */ : "=&r"(result), "+m"(*addr) : "r"(new_val.AO_whole), "r"(addr) : "cc"); |