diff options
| author | kobalicek <kobalicek.petr@gmail.com> | 2022-11-13 15:34:42 +0300 |
|---|---|---|
| committer | kobalicek <kobalicek.petr@gmail.com> | 2022-11-13 15:34:42 +0300 |
| commit | 5350efdc6a4953d1f62179d26c979ec879eb36a2 (patch) | |
| tree | cdfb9463d29eff05eec374d237c62edc348472f3 | |
| parent | 793206ddc6c18b5fca93e779e80a630681a9b912 (diff) | |
WIPabi_2_0
| -rw-r--r-- | db/a64data.json | 23 | ||||
| -rw-r--r-- | tools/tablegen-a32.js | 3 |
2 files changed, 20 insertions, 6 deletions
diff --git a/db/a64data.json b/db/a64data.json index 3d61d61..59f1e8c 100644 --- a/db/a64data.json +++ b/db/a64data.json @@ -9,6 +9,23 @@ }, "instructions": [ + {"inst": "adc Rd, Rn, Rm" , "a64": "X0011010|00|0|Rm|000000|Rn|Rd" , "ext": "ARMv8"}, + {"inst": "adcs Rd, Rn, Rm" , "a64": "X0111010|00|0|Rm|000000|Rn|Rd" , "ext": "ARMv8", "pstate": "NZCV=W"}, + {"inst": "add Rd, Rn, Rm, {lsl|lsr|asr #n}" , "a64": "X0001011|shift:2|0|Rm|n:6|Rn|Rd" , "ext": "ARMv8"}, + {"inst": "add Rd|SP, Rn|SP, Rm, {extend #n}" , "a64": "X0001011|00|1|Rm|extend:3|n:3|Rn|Rd" , "ext": "ARMv8"}, + {"inst": "add Rd|SP, Rn|SP, #immZ, {lsl #n=0|12}" , "a64": "X0010001|0|n:1|immZ:12|Rn|Rd" , "ext": "ARMv8"}, + {"inst": "addg Xd|SP, Xn|SP, #imm1, #imm2" , "a64": "10010001|10|imm1:6|00|imm2:4|Rn|Rd" , "ext": "MTE"}, + {"inst": "adds Rd, Rn, Rm, {lsl|lsr|asr #n}" , "a64": "X0101011|shift:2|0|Rm|n:6|Rn|Rd" , "ext": "ARMv8", "pstate": "NZCV=W"}, + {"inst": "adds Rd, Rn|SP, Rm, {extend #n}" , "a64": "X0101011|00|1|Rm|option:3|n:3|Rn|Rd" , "ext": "ARMv8", "pstate": "NZCV=W"}, + {"inst": "adds Rd|SP, Rn|SP, #immZ, {lsl #n=0|12}" , "a64": "X0110001|0|n:1|immZ:12|Rn|Rd" , "ext": "ARMv8", "pstate": "NZCV=W"}, + {"inst": "adr Xd, #relS" , "a64": "0|relS[1:0]|10000|relS[20:2]|Rd" , "ext": "ARMv8"}, + {"inst": "adrp Xd, #relS" , "a64": "1|relS[1:0]|10000|relS[20:2]|Rd" , "ext": "ARMv8"}, + + {"inst": "and Rd|SP, Rn, Rm, {sop #n}" , "a64": "X0001010|sop|0|Rm|imm:6|Rn|Rd" , "ext": "ARMv8", "imm": "ShiftImm(n, x)"}, + {"inst": "and Rd|SP, Rn, #imm" , "a64": "X0010010|0|imm:13|Rn|Rd" , "ext": "ARMv8", "imm": "LogicalImm(imm, x)"}, + {"inst": "ands Rd|SP, Rn, Rm, {sop #n}" , "a64": "X1101010|sop|0|Rm|imm:6|Rn|Rd" , "ext": "ARMv8", "imm": "ShiftImm(n, x)"}, + {"inst": "ands Rd|SP, Rn, #imm" , "a64": "X1110010|0|imm:13|Rn|Rd" , "ext": "ARMv8", "imm": "LogicalImm(imm, x)"}, + {"inst": "abs Zd.t, Pg/M, Zn.t" , "a64": "00000100|sz|0|10110101|Pg:3|Zn|Zd" , "ext": "SVE"}, {"inst": "adclb Zda.t, Pg/M, Zn.t" , "a64": "01000101|0s|0|Zm|110100|Zn|Zda" , "ext": "SVE2"}, {"inst": "adclt Zda.t, Pg/M, Zn.t" , "a64": "01000101|0s|0|Zm|110101|Zn|Zda" , "ext": "SVE2"}, @@ -20,9 +37,9 @@ {"inst": "addp Zdn.t, Pg/M, Zdn.t, Zm.t" , "a64": "01000100|sz|010001101|Pg:3|Zm|Zdn" , "ext": "SVE"}, {"inst": "addpl Xd|SP, Xn|SP, #immS" , "a64": "00000100|01|1|Rn|01010|immS:6|Rd" , "ext": "SVE"}, {"inst": "addvl Xd|SP, Xn|SP, #immS" , "a64": "00000100|00|1|Rn|01010|immS:6|Rd" , "ext": "SVE"}, - {"inst": "adr Zd.t, [Zn.t, Zm.t], {lsl #amount}]" , "a64": "00000100|1s|1|Zm|1010|msz|Zn|Zd" , "ext": "SVE"}, - {"inst": "adr Zd.D, [Zn.D, Zm.D], {sxtw #amount}]" , "a64": "00000100|00|1|Zm|1010|msz|Zn|Zd" , "ext": "SVE"}, - {"inst": "adr Zd.D, [Zn.D, Zm.D], {uxtw #amount}]" , "a64": "00000100|01|1|Zm|1010|msz|Zn|Zd" , "ext": "SVE"}, + {"inst": "adr Zd.t, [Zn.t, Zm.t], {lsl #n}]" , "a64": "00000100|1s|1|Zm|1010|msz|Zn|Zd" , "ext": "SVE"}, + {"inst": "adr Zd.D, [Zn.D, Zm.D], {sxtw #n}]" , "a64": "00000100|00|1|Zm|1010|msz|Zn|Zd" , "ext": "SVE"}, + {"inst": "adr Zd.D, [Zn.D, Zm.D], {uxtw #n}]" , "a64": "00000100|01|1|Zm|1010|msz|Zn|Zd" , "ext": "SVE"}, {"inst": "aesd Zdn.B, Zdn.B, Zm.B" , "a64": "01000101|00|100010111|001|Zm|Zdn" , "ext": "SVE2_AES"}, {"inst": "aese Zdn.B, Zdn.B, Zm.B" , "a64": "01000101|00|100010111|000|Zm|Zdn" , "ext": "SVE2_AES"}, {"inst": "aesimc Zdn.B, Zdn.B" , "a64": "01000101|00|100000111|001|00000|Zdn" , "ext": "SVE2_AES"}, diff --git a/tools/tablegen-a32.js b/tools/tablegen-a32.js index ed8eb83..49794b5 100644 --- a/tools/tablegen-a32.js +++ b/tools/tablegen-a32.js @@ -54,9 +54,6 @@ function regToOpcode(field, op, regType) { let vars = {"type": "uint32_t", "name": v, "init": `${op}.as<Reg>().id()`}; for (let value of field.values) { - const mask = ((1 << (value.size)) - 1) << value.from; - const shift = value.index - value.from; - if (value.from === 0 && value.size === 1) loHi += `Lo${value.index}`; else if (value.from === 4 && value.size === 1) |