diff options
author | kobalicek <kobalicek.petr@gmail.com> | 2022-07-02 00:53:14 +0300 |
---|---|---|
committer | kobalicek <kobalicek.petr@gmail.com> | 2022-07-02 00:53:14 +0300 |
commit | ee3d04367cfda5dd385a772baf1013250ed011b7 (patch) | |
tree | b8f0ec47e54c6b7a67f0c161d79ddba7d5a551ca | |
parent | d3fbf7c9bc7c1d1365a94a45614b91c5a3706b81 (diff) |
Use casting to suppress -Wbitwise-instead-of-logical warning instead of suppressing it globallybool_bitwise_fix
-rw-r--r-- | src/asmjit/arm/a64assembler.cpp | 20 | ||||
-rw-r--r-- | src/asmjit/arm/armoperand.h | 16 | ||||
-rw-r--r-- | src/asmjit/core/api-config.h | 10 | ||||
-rw-r--r-- | src/asmjit/core/operand.h | 4 | ||||
-rw-r--r-- | src/asmjit/x86/x86assembler.cpp | 16 | ||||
-rw-r--r-- | src/asmjit/x86/x86operand.h | 36 |
6 files changed, 46 insertions, 56 deletions
diff --git a/src/asmjit/arm/a64assembler.cpp b/src/asmjit/arm/a64assembler.cpp index 485f05f..4e39546 100644 --- a/src/asmjit/arm/a64assembler.cpp +++ b/src/asmjit/arm/a64assembler.cpp @@ -698,25 +698,25 @@ static const Support::Array<uint8_t, 32> commonHiRegIdOfType = {{ #undef V static inline bool checkValidRegs(const Operand_& o0) noexcept { - return ((o0.id() < 31) | (o0.id() == commonHiRegIdOfType[o0.as<Reg>().type()])); + return bool(unsigned(o0.id() < 31) | unsigned(o0.id() == commonHiRegIdOfType[o0.as<Reg>().type()])); } static inline bool checkValidRegs(const Operand_& o0, const Operand_& o1) noexcept { - return ((o0.id() < 31) | (o0.id() == commonHiRegIdOfType[o0.as<Reg>().type()])) & - ((o1.id() < 31) | (o1.id() == commonHiRegIdOfType[o1.as<Reg>().type()])) ; + return bool((unsigned(o0.id() < 31) | unsigned(o0.id() == commonHiRegIdOfType[o0.as<Reg>().type()])) & + (unsigned(o1.id() < 31) | unsigned(o1.id() == commonHiRegIdOfType[o1.as<Reg>().type()]))); } static inline bool checkValidRegs(const Operand_& o0, const Operand_& o1, const Operand_& o2) noexcept { - return ((o0.id() < 31) | (o0.id() == commonHiRegIdOfType[o0.as<Reg>().type()])) & - ((o1.id() < 31) | (o1.id() == commonHiRegIdOfType[o1.as<Reg>().type()])) & - ((o2.id() < 31) | (o2.id() == commonHiRegIdOfType[o2.as<Reg>().type()])) ; + return bool((unsigned(o0.id() < 31) | unsigned(o0.id() == commonHiRegIdOfType[o0.as<Reg>().type()])) & + (unsigned(o1.id() < 31) | unsigned(o1.id() == commonHiRegIdOfType[o1.as<Reg>().type()])) & + (unsigned(o2.id() < 31) | unsigned(o2.id() == commonHiRegIdOfType[o2.as<Reg>().type()]))); } static inline bool checkValidRegs(const Operand_& o0, const Operand_& o1, const Operand_& o2, const Operand_& o3) noexcept { - return ((o0.id() < 31) | (o0.id() == commonHiRegIdOfType[o0.as<Reg>().type()])) & - ((o1.id() < 31) | (o1.id() == commonHiRegIdOfType[o1.as<Reg>().type()])) & - ((o2.id() < 31) | (o2.id() == commonHiRegIdOfType[o2.as<Reg>().type()])) & - ((o3.id() < 31) | (o3.id() == commonHiRegIdOfType[o3.as<Reg>().type()])) ; + return bool((unsigned(o0.id() < 31) | unsigned(o0.id() == commonHiRegIdOfType[o0.as<Reg>().type()])) & + (unsigned(o1.id() < 31) | unsigned(o1.id() == commonHiRegIdOfType[o1.as<Reg>().type()])) & + (unsigned(o2.id() < 31) | unsigned(o2.id() == commonHiRegIdOfType[o2.as<Reg>().type()])) & + (unsigned(o3.id() < 31) | unsigned(o3.id() == commonHiRegIdOfType[o3.as<Reg>().type()]))); } // a64::Assembler - Construction & Destruction diff --git a/src/asmjit/arm/armoperand.h b/src/asmjit/arm/armoperand.h index ede829d..8d5435f 100644 --- a/src/asmjit/arm/armoperand.h +++ b/src/asmjit/arm/armoperand.h @@ -110,14 +110,14 @@ public: static inline bool isVecQ(const Operand_& op) noexcept { return op.as<Reg>().isVecQ(); } static inline bool isVecV(const Operand_& op) noexcept { return op.as<Reg>().isVecV(); } - static inline bool isGpW(const Operand_& op, uint32_t id) noexcept { return isGpW(op) & (op.id() == id); } - static inline bool isGpX(const Operand_& op, uint32_t id) noexcept { return isGpX(op) & (op.id() == id); } - static inline bool isVecB(const Operand_& op, uint32_t id) noexcept { return isVecB(op) & (op.id() == id); } - static inline bool isVecH(const Operand_& op, uint32_t id) noexcept { return isVecH(op) & (op.id() == id); } - static inline bool isVecS(const Operand_& op, uint32_t id) noexcept { return isVecS(op) & (op.id() == id); } - static inline bool isVecD(const Operand_& op, uint32_t id) noexcept { return isVecD(op) & (op.id() == id); } - static inline bool isVecQ(const Operand_& op, uint32_t id) noexcept { return isVecQ(op) & (op.id() == id); } - static inline bool isVecV(const Operand_& op, uint32_t id) noexcept { return isVecV(op) & (op.id() == id); } + static inline bool isGpW(const Operand_& op, uint32_t id) noexcept { return bool(unsigned(isGpW(op)) & unsigned(op.id() == id)); } + static inline bool isGpX(const Operand_& op, uint32_t id) noexcept { return bool(unsigned(isGpX(op)) & unsigned(op.id() == id)); } + static inline bool isVecB(const Operand_& op, uint32_t id) noexcept { return bool(unsigned(isVecB(op)) & unsigned(op.id() == id)); } + static inline bool isVecH(const Operand_& op, uint32_t id) noexcept { return bool(unsigned(isVecH(op)) & unsigned(op.id() == id)); } + static inline bool isVecS(const Operand_& op, uint32_t id) noexcept { return bool(unsigned(isVecS(op)) & unsigned(op.id() == id)); } + static inline bool isVecD(const Operand_& op, uint32_t id) noexcept { return bool(unsigned(isVecD(op)) & unsigned(op.id() == id)); } + static inline bool isVecQ(const Operand_& op, uint32_t id) noexcept { return bool(unsigned(isVecQ(op)) & unsigned(op.id() == id)); } + static inline bool isVecV(const Operand_& op, uint32_t id) noexcept { return bool(unsigned(isVecV(op)) & unsigned(op.id() == id)); } }; //! General purpose register (ARM). diff --git a/src/asmjit/core/api-config.h b/src/asmjit/core/api-config.h index 57b4a79..a0fb979 100644 --- a/src/asmjit/core/api-config.h +++ b/src/asmjit/core/api-config.h @@ -481,16 +481,6 @@ namespace asmjit { #if defined _DOXYGEN #define ASMJIT_BEGIN_NAMESPACE namespace asmjit { #define ASMJIT_END_NAMESPACE } -#elif defined(__clang_major__) && __clang_major__ >= 14 - #define ASMJIT_BEGIN_NAMESPACE \ - namespace asmjit { inline namespace ASMJIT_ABI_NAMESPACE { \ - _Pragma("clang diagnostic push") \ - _Pragma("clang diagnostic ignored \"-Wbitwise-instead-of-logical\"") \ - _Pragma("clang diagnostic ignored \"-Wconstant-logical-operand\"") \ - _Pragma("clang diagnostic ignored \"-Wunnamed-type-template-args\"") - #define ASMJIT_END_NAMESPACE \ - _Pragma("clang diagnostic pop") \ - }} #elif defined(__clang__) #define ASMJIT_BEGIN_NAMESPACE \ namespace asmjit { inline namespace ASMJIT_ABI_NAMESPACE { \ diff --git a/src/asmjit/core/operand.h b/src/asmjit/core/operand.h index 2f81a21..02a4093 100644 --- a/src/asmjit/core/operand.h +++ b/src/asmjit/core/operand.h @@ -994,9 +994,9 @@ public: } //! Tests whether the `op` is a general purpose register of the given `id`. - static inline bool isGp(const Operand_& op, uint32_t id) noexcept { return isGp(op) & (op.id() == id); } + static inline bool isGp(const Operand_& op, uint32_t id) noexcept { return bool(unsigned(isGp(op)) & unsigned(op.id() == id)); } //! Tests whether the `op` is a vector register of the given `id`. - static inline bool isVec(const Operand_& op, uint32_t id) noexcept { return isVec(op) & (op.id() == id); } + static inline bool isVec(const Operand_& op, uint32_t id) noexcept { return bool(unsigned(isVec(op)) & unsigned(op.id() == id)); } //! \} }; diff --git a/src/asmjit/x86/x86assembler.cpp b/src/asmjit/x86/x86assembler.cpp index f11fea0..2871272 100644 --- a/src/asmjit/x86/x86assembler.cpp +++ b/src/asmjit/x86/x86assembler.cpp @@ -2716,7 +2716,7 @@ CaseExtRm: case InstDB::kEncodingExtRm_P: if (isign3 == ENC_OPS2(Reg, Reg)) { - opcode.add66hIf(Reg::isXmm(o0) | Reg::isXmm(o1)); + opcode.add66hIf(unsigned(Reg::isXmm(o0)) | unsigned(Reg::isXmm(o1))); opReg = o0.id(); rbReg = o1.id(); @@ -2760,7 +2760,7 @@ CaseExtRm: case InstDB::kEncodingExtRmRi_P: if (isign3 == ENC_OPS2(Reg, Reg)) { - opcode.add66hIf(Reg::isXmm(o0) | Reg::isXmm(o1)); + opcode.add66hIf(unsigned(Reg::isXmm(o0)) | unsigned(Reg::isXmm(o1))); opReg = o0.id(); rbReg = o1.id(); @@ -2812,7 +2812,7 @@ CaseExtRm: immSize = 1; if (isign3 == ENC_OPS3(Reg, Reg, Imm)) { - opcode.add66hIf(Reg::isXmm(o0) | Reg::isXmm(o1)); + opcode.add66hIf(unsigned(Reg::isXmm(o0)) | unsigned(Reg::isXmm(o1))); opReg = o0.id(); rbReg = o1.id(); @@ -3040,7 +3040,7 @@ CaseVexMri: goto CaseVexRm; case InstDB::kEncodingVexRm_Wx: - opcode.addWIf(Reg::isGpq(o0) | Reg::isGpq(o1)); + opcode.addWIf(unsigned(Reg::isGpq(o0)) | unsigned(Reg::isGpq(o1))); goto CaseVexRm; case InstDB::kEncodingVexRm_Lx_Narrow: @@ -3110,7 +3110,7 @@ CaseVexRm: } case InstDB::kEncodingVexRmi_Wx: - opcode.addWIf(Reg::isGpq(o0) | Reg::isGpq(o1)); + opcode.addWIf(unsigned(Reg::isGpq(o0)) | unsigned(Reg::isGpq(o1))); goto CaseVexRmi; case InstDB::kEncodingVexRmi_Lx: @@ -3159,7 +3159,7 @@ CaseVexRvm_R: } case InstDB::kEncodingVexRvm_Wx: { - opcode.addWIf(Reg::isGpq(o0) | (o2.size() == 8)); + opcode.addWIf(unsigned(Reg::isGpq(o0)) | unsigned((o2.size() == 8))); goto CaseVexRvm; } @@ -3261,7 +3261,7 @@ VexRvmi: } case InstDB::kEncodingVexRmv_Wx: - opcode.addWIf(Reg::isGpq(o0) | Reg::isGpq(o2)); + opcode.addWIf(unsigned(Reg::isGpq(o0)) | unsigned(Reg::isGpq(o2))); ASMJIT_FALLTHROUGH; case InstDB::kEncodingVexRmv: @@ -3614,7 +3614,7 @@ VexRvmi: break; case InstDB::kEncodingVexVm_Wx: - opcode.addWIf(Reg::isGpq(o0) | Reg::isGpq(o1)); + opcode.addWIf(unsigned(Reg::isGpq(o0)) | unsigned(Reg::isGpq(o1))); ASMJIT_FALLTHROUGH; case InstDB::kEncodingVexVm: diff --git a/src/asmjit/x86/x86operand.h b/src/asmjit/x86/x86operand.h index 037d4af..e4c3275 100644 --- a/src/asmjit/x86/x86operand.h +++ b/src/asmjit/x86/x86operand.h @@ -174,24 +174,24 @@ public: static inline bool isTmm(const Operand_& op) noexcept { return op.as<Reg>().isTmm(); } static inline bool isRip(const Operand_& op) noexcept { return op.as<Reg>().isRip(); } - static inline bool isGpb(const Operand_& op, uint32_t rId) noexcept { return isGpb(op) & (op.id() == rId); } - static inline bool isGpbLo(const Operand_& op, uint32_t rId) noexcept { return isGpbLo(op) & (op.id() == rId); } - static inline bool isGpbHi(const Operand_& op, uint32_t rId) noexcept { return isGpbHi(op) & (op.id() == rId); } - static inline bool isGpw(const Operand_& op, uint32_t rId) noexcept { return isGpw(op) & (op.id() == rId); } - static inline bool isGpd(const Operand_& op, uint32_t rId) noexcept { return isGpd(op) & (op.id() == rId); } - static inline bool isGpq(const Operand_& op, uint32_t rId) noexcept { return isGpq(op) & (op.id() == rId); } - static inline bool isXmm(const Operand_& op, uint32_t rId) noexcept { return isXmm(op) & (op.id() == rId); } - static inline bool isYmm(const Operand_& op, uint32_t rId) noexcept { return isYmm(op) & (op.id() == rId); } - static inline bool isZmm(const Operand_& op, uint32_t rId) noexcept { return isZmm(op) & (op.id() == rId); } - static inline bool isMm(const Operand_& op, uint32_t rId) noexcept { return isMm(op) & (op.id() == rId); } - static inline bool isKReg(const Operand_& op, uint32_t rId) noexcept { return isKReg(op) & (op.id() == rId); } - static inline bool isSReg(const Operand_& op, uint32_t rId) noexcept { return isSReg(op) & (op.id() == rId); } - static inline bool isCReg(const Operand_& op, uint32_t rId) noexcept { return isCReg(op) & (op.id() == rId); } - static inline bool isDReg(const Operand_& op, uint32_t rId) noexcept { return isDReg(op) & (op.id() == rId); } - static inline bool isSt(const Operand_& op, uint32_t rId) noexcept { return isSt(op) & (op.id() == rId); } - static inline bool isBnd(const Operand_& op, uint32_t rId) noexcept { return isBnd(op) & (op.id() == rId); } - static inline bool isTmm(const Operand_& op, uint32_t rId) noexcept { return isTmm(op) & (op.id() == rId); } - static inline bool isRip(const Operand_& op, uint32_t rId) noexcept { return isRip(op) & (op.id() == rId); } + static inline bool isGpb(const Operand_& op, uint32_t rId) noexcept { return bool(unsigned(isGpb(op)) & unsigned(op.id() == rId)); } + static inline bool isGpbLo(const Operand_& op, uint32_t rId) noexcept { return bool(unsigned(isGpbLo(op)) & unsigned(op.id() == rId)); } + static inline bool isGpbHi(const Operand_& op, uint32_t rId) noexcept { return bool(unsigned(isGpbHi(op)) & unsigned(op.id() == rId)); } + static inline bool isGpw(const Operand_& op, uint32_t rId) noexcept { return bool(unsigned(isGpw(op)) & unsigned(op.id() == rId)); } + static inline bool isGpd(const Operand_& op, uint32_t rId) noexcept { return bool(unsigned(isGpd(op)) & unsigned(op.id() == rId)); } + static inline bool isGpq(const Operand_& op, uint32_t rId) noexcept { return bool(unsigned(isGpq(op)) & unsigned(op.id() == rId)); } + static inline bool isXmm(const Operand_& op, uint32_t rId) noexcept { return bool(unsigned(isXmm(op)) & unsigned(op.id() == rId)); } + static inline bool isYmm(const Operand_& op, uint32_t rId) noexcept { return bool(unsigned(isYmm(op)) & unsigned(op.id() == rId)); } + static inline bool isZmm(const Operand_& op, uint32_t rId) noexcept { return bool(unsigned(isZmm(op)) & unsigned(op.id() == rId)); } + static inline bool isMm(const Operand_& op, uint32_t rId) noexcept { return bool(unsigned(isMm(op)) & unsigned(op.id() == rId)); } + static inline bool isKReg(const Operand_& op, uint32_t rId) noexcept { return bool(unsigned(isKReg(op)) & unsigned(op.id() == rId)); } + static inline bool isSReg(const Operand_& op, uint32_t rId) noexcept { return bool(unsigned(isSReg(op)) & unsigned(op.id() == rId)); } + static inline bool isCReg(const Operand_& op, uint32_t rId) noexcept { return bool(unsigned(isCReg(op)) & unsigned(op.id() == rId)); } + static inline bool isDReg(const Operand_& op, uint32_t rId) noexcept { return bool(unsigned(isDReg(op)) & unsigned(op.id() == rId)); } + static inline bool isSt(const Operand_& op, uint32_t rId) noexcept { return bool(unsigned(isSt(op)) & unsigned(op.id() == rId)); } + static inline bool isBnd(const Operand_& op, uint32_t rId) noexcept { return bool(unsigned(isBnd(op)) & unsigned(op.id() == rId)); } + static inline bool isTmm(const Operand_& op, uint32_t rId) noexcept { return bool(unsigned(isTmm(op)) & unsigned(op.id() == rId)); } + static inline bool isRip(const Operand_& op, uint32_t rId) noexcept { return bool(unsigned(isRip(op)) & unsigned(op.id() == rId)); } }; //! General purpose register (X86). |