diff options
| author | aegistudio <aegistudio@users.noreply.github.com> | 2022-11-10 12:11:05 +0300 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2022-11-10 12:11:05 +0300 |
| commit | 5af57595a909bbd5114e3503ae88bdbb6169c7ea (patch) | |
| tree | a1f373f51801d34b4ebbac56841980c72be3d286 | |
| parent | ae63ced6dd3bc281a959edd32704b27778622be0 (diff) | |
[Bug] Fixed LDURSW instruction on AArch64 (#389)
The instruction was wrongly described as supporting both W/X registers, however, it only supports X register.
| -rw-r--r-- | src/asmjit/arm/a64instdb.cpp | 4 | ||||
| -rw-r--r-- | test/asmjit_test_assembler_a64.cpp | 4 |
2 files changed, 6 insertions, 2 deletions
diff --git a/src/asmjit/arm/a64instdb.cpp b/src/asmjit/arm/a64instdb.cpp index 5b722b4..a3ea629 100644 --- a/src/asmjit/arm/a64instdb.cpp +++ b/src/asmjit/arm/a64instdb.cpp @@ -300,7 +300,7 @@ const InstInfo _instInfoTable[] = { INST(Ldurh , BaseRM_SImm9 , (0b0111100001000000000000, 0b0000000000000000000000, kW , kZR, 0 , 0) , kRWI_W , 0 , 9 , 2153), // #230 INST(Ldursb , BaseRM_SImm9 , (0b0011100011000000000000, 0b0000000000000000000000, kWX, kZR, 22, 0) , kRWI_W , 0 , 10 , 2159), // #231 INST(Ldursh , BaseRM_SImm9 , (0b0111100011000000000000, 0b0000000000000000000000, kWX, kZR, 22, 0) , kRWI_W , 0 , 11 , 2166), // #232 - INST(Ldursw , BaseRM_SImm9 , (0b1011100010000000000000, 0b0000000000000000000000, kWX, kZR, 0 , 0) , kRWI_W , 0 , 12 , 2173), // #233 + INST(Ldursw , BaseRM_SImm9 , (0b1011100010000000000000, 0b0000000000000000000000, kX, kZR, 0 , 0) , kRWI_W , 0 , 12 , 2173), // #233 INST(Ldxp , BaseLdxp , (0b1000100001111111000000, kWX, 30) , kRWI_WW , 0 , 1 , 2180), // #234 INST(Ldxr , BaseRM_NoImm , (0b1000100001011111011111, kWX, kZR, 30) , kRWI_W , 0 , 10 , 2185), // #235 INST(Ldxrb , BaseRM_NoImm , (0b0000100001011111011111, kW , kZR, 0 ) , kRWI_W , 0 , 11 , 2190), // #236 @@ -1275,7 +1275,7 @@ const BaseRM_SImm9 baseRM_SImm9[23] = { { 0b0111100001000000000000, 0b0000000000000000000000, kW , kZR, 0 , 0 }, // ldurh { 0b0011100011000000000000, 0b0000000000000000000000, kWX, kZR, 22, 0 }, // ldursb { 0b0111100011000000000000, 0b0000000000000000000000, kWX, kZR, 22, 0 }, // ldursh - { 0b1011100010000000000000, 0b0000000000000000000000, kWX, kZR, 0 , 0 }, // ldursw + { 0b1011100010000000000000, 0b0000000000000000000000, kX, kZR, 0 , 0 }, // ldursw { 0b1101100110100000000010, 0b1101100110100000000001, kX, kSP, 0, 4 }, // st2g { 0b1101100100100000000010, 0b1101100100100000000001, kX, kSP, 0, 4 }, // stg { 0b1011100000000000000010, 0b0000000000000000000000, kWX, kZR, 30, 0 }, // sttr diff --git a/test/asmjit_test_assembler_a64.cpp b/test/asmjit_test_assembler_a64.cpp index 9b9a925..bbba4b6 100644 --- a/test/asmjit_test_assembler_a64.cpp +++ b/test/asmjit_test_assembler_a64.cpp @@ -746,6 +746,10 @@ static void ASMJIT_NOINLINE testA64AssemblerBase(AssemblerTester<a64::Assembler> TEST_INSTRUCTION("411088B8", ldursw(x1, ptr(x2, 129))); TEST_INSTRUCTION("E10380B8", ldursw(x1, ptr(sp))); TEST_INSTRUCTION("E11388B8", ldursw(x1, ptr(sp, 129))); + TEST_INSTRUCTION("420080B8", ldursw(x2, ptr(x2))); + TEST_INSTRUCTION("421088B8", ldursw(x2, ptr(x2, 129))); + TEST_INSTRUCTION("E20380B8", ldursw(x2, ptr(sp))); + TEST_INSTRUCTION("E21388B8", ldursw(x2, ptr(sp, 129))); TEST_INSTRUCTION("61087F88", ldxp(w1, w2, ptr(x3))); TEST_INSTRUCTION("E10B7F88", ldxp(w1, w2, ptr(sp))); TEST_INSTRUCTION("61087FC8", ldxp(x1, x2, ptr(x3))); |