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authorkobalicek <kobalicek.petr@gmail.com>2020-06-30 21:42:22 +0300
committerkobalicek <kobalicek.petr@gmail.com>2020-07-01 02:07:37 +0300
commitba30278d66438815981b7c0ca9ed4ebb11266d3a (patch)
tree19c3d42dcfbeccb21575b07e7077c7b7e439012e
parent3535263419c214448d90781c698dc70f95528e75 (diff)
Added support for more X86 extensions (AMX, AVX512_VP2INTERSECT, MCOMMIT, RDPRU, SERIALIZE, SNP, TSXLDTRK)
Diffstat
-rw-r--r--README.md6
-rw-r--r--src/asmjit/core/builder.cpp2
-rw-r--r--src/asmjit/core/builder.h7
-rw-r--r--src/asmjit/core/operand.h2
-rw-r--r--src/asmjit/x86/x86assembler.cpp214
-rw-r--r--src/asmjit/x86/x86builder.cpp2
-rw-r--r--src/asmjit/x86/x86compiler.cpp2
-rw-r--r--src/asmjit/x86/x86emitter.h797
-rw-r--r--src/asmjit/x86/x86features.cpp22
-rw-r--r--src/asmjit/x86/x86features.h16
-rw-r--r--src/asmjit/x86/x86formatter.cpp32
-rw-r--r--src/asmjit/x86/x86globals.h27
-rw-r--r--src/asmjit/x86/x86instapi.cpp19
-rw-r--r--src/asmjit/x86/x86instdb.cpp5052
-rw-r--r--src/asmjit/x86/x86instdb.h25
-rw-r--r--src/asmjit/x86/x86instdb_p.h15
-rw-r--r--src/asmjit/x86/x86opcode_p.h3
-rw-r--r--src/asmjit/x86/x86operand.h147
-rw-r--r--tools/tablegen-x86.js42
19 files changed, 3605 insertions, 2827 deletions
diff --git a/README.md b/README.md
index abe51bb..167884f 100644
--- a/README.md
+++ b/README.md
@@ -44,7 +44,11 @@ TODO
----
* [ ] Core:
- * [ ] Add support for user external buffers in CodeHolder.
+ * [ ] Add support for user external buffers in CodeBuffer / CodeHolder.
+ * [ ] Register allocator doesn't understand register pairs, affected instructions:
+ * [ ] v4fmaddps, v4fmaddss, v4fnmaddps, v4fnmaddss
+ * [ ] vp4dpwssd, vp4dpwssds
+ * [ ] vp2intersectd, vp2intersectq
* [ ] Ports:
* [ ] ARM/Thumb/AArch64 support.
diff --git a/src/asmjit/core/builder.cpp b/src/asmjit/core/builder.cpp
index 8455dc8..a582e96 100644
--- a/src/asmjit/core/builder.cpp
+++ b/src/asmjit/core/builder.cpp
@@ -789,7 +789,7 @@ Error BaseBuilder::comment(const char* data, size_t size) {
// [asmjit::BaseBuilder - Serialize]
// ============================================================================
-Error BaseBuilder::serialize(BaseEmitter* dst) {
+Error BaseBuilder::serializeTo(BaseEmitter* dst) {
Error err = kErrorOk;
BaseNode* node_ = _firstNode;
diff --git a/src/asmjit/core/builder.h b/src/asmjit/core/builder.h
index ee3c78b..d6d7d22 100644
--- a/src/asmjit/core/builder.h
+++ b/src/asmjit/core/builder.h
@@ -357,7 +357,7 @@ public:
//! Although not explicitly required the emitter will most probably be of
//! Assembler type. The reason is that there is no known use of serializing
//! nodes held by Builder/Compiler into another Builder-like emitter.
- ASMJIT_API Error serialize(BaseEmitter* dst);
+ ASMJIT_API Error serializeTo(BaseEmitter* dst);
//! \}
@@ -370,6 +370,11 @@ public:
//! \}
#ifndef ASMJIT_NO_DEPRECATED
+ ASMJIT_DEPRECATED("Use serializeTo() instead, serialize() is now also an instruction.")
+ inline Error serialize(BaseEmitter* dst) {
+ return serializeTo(dst);
+ }
+
#ifndef ASMJIT_NO_LOGGING
ASMJIT_DEPRECATED("Use Formatter::formatNodeList(sb, formatFlags, builder)")
inline Error dump(String& sb, uint32_t formatFlags = 0) const noexcept {
diff --git a/src/asmjit/core/operand.h b/src/asmjit/core/operand.h
index 01cc1ea..1faaeca 100644
--- a/src/asmjit/core/operand.h
+++ b/src/asmjit/core/operand.h
@@ -674,7 +674,7 @@ public:
kTypeIP = 15,
//! Start of platform dependent register types (must be honored).
kTypeCustom = 16,
- //! Maximum possible register id of all architectures.
+ //! Maximum possible register type value.
kTypeMax = 31
};
diff --git a/src/asmjit/x86/x86assembler.cpp b/src/asmjit/x86/x86assembler.cpp
index 879fb2f..2f1dad8 100644
--- a/src/asmjit/x86/x86assembler.cpp
+++ b/src/asmjit/x86/x86assembler.cpp
@@ -669,6 +669,13 @@ ASMJIT_FAVOR_SPEED Error Assembler::_emit(uint32_t instId, const Operand_& o0, c
// [Encoding Scope]
// --------------------------------------------------------------------------
+ // How it works? Each case here represents a unique encoding of a group of
+ // instructions, which is handled separately. The handlers check instruction
+ // signature, possibly register types, etc, and process this information by
+ // writing some bits to opcode, opReg/rbReg, immValue/immSize, etc, and then
+ // at the end of the sequence it uses goto to jump into a lower level handler,
+ // that actually encodes the instruction.
+
switch (instInfo->_encoding) {
case InstDB::kEncodingNone:
goto EmitDone;
@@ -854,6 +861,32 @@ CaseX86M_GPB_MulDiv:
}
break;
+ case InstDB::kEncodingX86R_FromM:
+ if (isign3 == ENC_OPS1(Mem)) {
+ rmRel = &o0;
+ rbReg = o0.id();
+ goto EmitX86RFromM;
+ }
+ break;
+
+ case InstDB::kEncodingX86R32_EDX_EAX:
+ // Explicit form: R32, EDX, EAX.
+ if (isign3 == ENC_OPS3(Reg, Reg, Reg)) {
+ if (!Reg::isGpd(o1, Gp::kIdDx) || !Reg::isGpd(o2, Gp::kIdAx))
+ goto InvalidInstruction;
+ rbReg = o0.id();
+ goto EmitX86R;
+ }
+
+ // Implicit form: R32.
+ if (isign3 == ENC_OPS1(Reg)) {
+ if (!Reg::isGpd(o0))
+ goto InvalidInstruction;
+ rbReg = o0.id();
+ goto EmitX86R;
+ }
+ break;
+
case InstDB::kEncodingX86R_Native:
if (isign3 == ENC_OPS1(Reg)) {
rbReg = o0.id();
@@ -2767,6 +2800,10 @@ CaseExtRm:
case InstDB::kEncodingVexOp:
goto EmitVexEvexOp;
+ case InstDB::kEncodingVexOpMod:
+ rbReg = 0;
+ goto EmitVexEvexR;
+
case InstDB::kEncodingVexKmov:
if (isign3 == ENC_OPS2(Reg, Reg)) {
opReg = o0.id();
@@ -3007,6 +3044,33 @@ CaseVexRvm_R:
goto CaseVexRvm;
}
+ case InstDB::kEncodingVexRvm_Lx_2xK: {
+ if (isign3 == ENC_OPS3(Reg, Reg, Reg)) {
+ // Two registers are encoded as a single register.
+ // - First K register must be even.
+ // - Second K register must be first+1.
+ if ((o0.id() & 1) != 0 || o0.id() + 1 != o1.id())
+ goto InvalidPhysId;
+
+ const Operand_& o3 = opExt[EmitterUtils::kOp3];
+
+ opcode |= x86OpcodeLBySize(o2.size());
+ opReg = x86PackRegAndVvvvv(o0.id(), o2.id());
+
+ if (o3.isReg()) {
+ rbReg = o3.id();
+ goto EmitVexEvexR;
+ }
+
+ if (o3.isMem()) {
+ rmRel = &o3;
+ goto EmitVexEvexM;
+
+ }
+ }
+ break;
+ }
+
case InstDB::kEncodingVexRvmr_Lx: {
opcode |= x86OpcodeLBySize(o0.size() | o1.size());
ASMJIT_FALLTHROUGH;
@@ -3598,6 +3662,49 @@ CaseVexVmi_AfterImm:
}
break;
}
+
+ // ------------------------------------------------------------------------
+ // [AMX]
+ // ------------------------------------------------------------------------
+
+ case InstDB::kEncodingAmxCfg:
+ if (isign3 == ENC_OPS1(Mem)) {
+ rmRel = &o0;
+ goto EmitVexEvexM;
+ }
+ break;
+
+ case InstDB::kEncodingAmxR:
+ if (isign3 == ENC_OPS1(Reg)) {
+ opReg = o0.id();
+ rbReg = 0;
+ goto EmitVexEvexR;
+ }
+ break;
+
+ case InstDB::kEncodingAmxRm:
+ if (isign3 == ENC_OPS2(Reg, Mem)) {
+ opReg = o0.id();
+ rmRel = &o1;
+ goto EmitVexEvexM;
+ }
+ break;
+
+ case InstDB::kEncodingAmxMr:
+ if (isign3 == ENC_OPS2(Mem, Reg)) {
+ opReg = o1.id();
+ rmRel = &o0;
+ goto EmitVexEvexM;
+ }
+ break;
+
+ case InstDB::kEncodingAmxRmv:
+ if (isign3 == ENC_OPS3(Reg, Reg, Reg)) {
+ opReg = x86PackRegAndVvvvv(o0.id(), o2.id());
+ rbReg = o1.id();
+ goto EmitVexEvexR;
+ }
+ break;
}
goto InvalidInstruction;
@@ -3628,6 +3735,10 @@ EmitX86Op:
writer.emitImmediate(uint64_t(immValue), immSize);
goto EmitDone;
+ // --------------------------------------------------------------------------
+ // [Emit - X86 - Opcode + Reg]
+ // --------------------------------------------------------------------------
+
EmitX86OpReg:
// Emit mandatory instruction prefix.
writer.emitPP(opcode.v);
@@ -3649,8 +3760,11 @@ EmitX86OpReg:
writer.emitImmediate(uint64_t(immValue), immSize);
goto EmitDone;
+ // --------------------------------------------------------------------------
+ // [Emit - X86 - Opcode with implicit <mem> operand]
+ // --------------------------------------------------------------------------
+
EmitX86OpImplicitMem:
- // NOTE: Don't change the emit order here, it's compatible with KeyStone/LLVM.
rmInfo = x86MemInfo[rmRel->as<Mem>().baseAndIndexTypes()];
if (ASMJIT_UNLIKELY(rmRel->as<Mem>().hasOffset() || (rmInfo & kX86MemInfo_Index)))
goto InvalidInstruction;
@@ -3667,19 +3781,26 @@ EmitX86OpImplicitMem:
writer.emit8If(rex | kX86ByteRex, rex != 0);
}
+ // Emit override prefixes.
writer.emitSegmentOverride(rmRel->as<Mem>().segmentId());
writer.emitAddressOverride((rmInfo & _addressOverrideMask()) != 0);
// Emit instruction opcodes.
writer.emitMMAndOpcode(opcode.v);
+
+ // Emit immediate value.
writer.emitImmediate(uint64_t(immValue), immSize);
goto EmitDone;
+ // --------------------------------------------------------------------------
+ // [Emit - X86 - Opcode /r - register]
+ // --------------------------------------------------------------------------
+
EmitX86R:
// Mandatory instruction prefix.
writer.emitPP(opcode.v);
- // Rex prefix (64-bit only).
+ // Emit REX prefix (64-bit only).
{
uint32_t rex = opcode.extractRex(options) |
((opReg & 0x08) >> 1) | // REX.R (0x04).
@@ -3694,32 +3815,80 @@ EmitX86R:
rbReg &= 0x07;
}
- // Instruction opcodes.
+ // Emit instruction opcodes.
writer.emitMMAndOpcode(opcode.v);
- // ModR.
+
+ // Emit ModR.
writer.emit8(x86EncodeMod(3, opReg, rbReg));
+ // Emit immediate value.
+
writer.emitImmediate(uint64_t(immValue), immSize);
goto EmitDone;
+ // --------------------------------------------------------------------------
+ // [Emit - X86 - Opcode /r - memory base]
+ // --------------------------------------------------------------------------
+
+EmitX86RFromM:
+ rmInfo = x86MemInfo[rmRel->as<Mem>().baseAndIndexTypes()];
+ if (ASMJIT_UNLIKELY(rmRel->as<Mem>().hasOffset() || (rmInfo & kX86MemInfo_Index)))
+ goto InvalidInstruction;
+
+ // Emit mandatory instruction prefix.
+ writer.emitPP(opcode.v);
+
+ // Emit REX prefix (64-bit only).
+ {
+ uint32_t rex = opcode.extractRex(options) |
+ ((opReg & 0x08) >> 1) | // REX.R (0x04).
+ ((rbReg ) >> 3) ; // REX.B (0x01).
+
+ if (ASMJIT_UNLIKELY(x86IsRexInvalid(rex)))
+ goto InvalidRexPrefix;
+ rex &= ~kX86ByteInvalidRex & 0xFF;
+ writer.emit8If(rex | kX86ByteRex, rex != 0);
+
+ opReg &= 0x07;
+ rbReg &= 0x07;
+ }
+
+ // Emit override prefixes.
+ writer.emitSegmentOverride(rmRel->as<Mem>().segmentId());
+ writer.emitAddressOverride((rmInfo & _addressOverrideMask()) != 0);
+
+ // Emit instruction opcodes.
+ writer.emitMMAndOpcode(opcode.v);
+
+ // Emit ModR/M.
+ writer.emit8(x86EncodeMod(3, opReg, rbReg));
+
+ // Emit immediate value.
+ writer.emitImmediate(uint64_t(immValue), immSize);
+ goto EmitDone;
+
+ // --------------------------------------------------------------------------
+ // [Emit - X86 - Opcode /r - memory operand]
+ // --------------------------------------------------------------------------
+
EmitX86M:
// `rmRel` operand must be memory.
ASMJIT_ASSERT(rmRel != nullptr);
ASMJIT_ASSERT(rmRel->opType() == Operand::kOpMem);
ASMJIT_ASSERT((opcode & Opcode::kCDSHL_Mask) == 0);
+ // Emit override prefixes.
rmInfo = x86MemInfo[rmRel->as<Mem>().baseAndIndexTypes()];
writer.emitSegmentOverride(rmRel->as<Mem>().segmentId());
memOpAOMark = writer.cursor();
writer.emitAddressOverride((rmInfo & _addressOverrideMask()) != 0);
- // Mandatory instruction prefix.
+ // Emit mandatory instruction prefix.
writer.emitPP(opcode.v);
+ // Emit REX prefix (64-bit only).
rbReg = rmRel->as<Mem>().baseId();
rxReg = rmRel->as<Mem>().indexId();
-
- // REX prefix (64-bit only).
{
uint32_t rex;
@@ -3738,8 +3907,9 @@ EmitX86M:
opReg &= 0x07;
}
- // Instruction opcodes.
+ // Emit instruction opcodes.
writer.emitMMAndOpcode(opcode.v);
+
// ... Fall through ...
// --------------------------------------------------------------------------
@@ -3754,25 +3924,28 @@ EmitModSib:
relOffset = rmRel->as<Mem>().offsetLo32();
uint32_t mod = x86EncodeMod(0, opReg, rbReg);
- if (rbReg == Gp::kIdSp) {
- // [XSP|R12].
- if (relOffset == 0) {
+ bool forceSIB = commonInfo->isTsibOp();
+
+ if (rbReg == Gp::kIdSp || forceSIB) {
+ // TSIB or [XSP|R12].
+ mod = (mod & 0xF8u) | 0x04u;
+ if (rbReg != Gp::kIdBp && relOffset == 0) {
writer.emit8(mod);
- writer.emit8(x86EncodeSib(0, 4, 4));
+ writer.emit8(x86EncodeSib(0, 4, rbReg));
}
- // [XSP|R12 + DISP8|DISP32].
+ // TSIB or [XSP|R12 + DISP8|DISP32].
else {
uint32_t cdShift = (opcode & Opcode::kCDSHL_Mask) >> Opcode::kCDSHL_Shift;
int32_t cdOffset = relOffset >> cdShift;
if (Support::isInt8(cdOffset) && relOffset == int32_t(uint32_t(cdOffset) << cdShift)) {
writer.emit8(mod + 0x40); // <- MOD(1, opReg, rbReg).
- writer.emit8(x86EncodeSib(0, 4, 4));
+ writer.emit8(x86EncodeSib(0, 4, rbReg));
writer.emit8(cdOffset & 0xFF);
}
else {
writer.emit8(mod + 0x80); // <- MOD(2, opReg, rbReg).
- writer.emit8(x86EncodeSib(0, 4, 4));
+ writer.emit8(x86EncodeSib(0, 4, rbReg));
writer.emit32uLE(uint32_t(relOffset));
}
}
@@ -4144,7 +4317,7 @@ EmitFpuOp:
goto EmitDone;
// --------------------------------------------------------------------------
- // [Emit - VEX / EVEX]
+ // [Emit - VEX|EVEX]
// --------------------------------------------------------------------------
EmitVexEvexOp:
@@ -4181,6 +4354,10 @@ EmitVexEvexOp:
}
}
+ // --------------------------------------------------------------------------
+ // [Emit - VEX|EVEX - /r (Register)]
+ // --------------------------------------------------------------------------
+
EmitVexEvexR:
{
// Construct `x` - a complete EVEX|VEX prefix.
@@ -4288,6 +4465,10 @@ EmitVexEvexR:
}
}
+ // --------------------------------------------------------------------------
+ // [Emit - VEX|EVEX - /r (Memory)]
+ // --------------------------------------------------------------------------
+
EmitVexEvexM:
ASMJIT_ASSERT(rmRel != nullptr);
ASMJIT_ASSERT(rmRel->opType() == Operand::kOpMem);
@@ -4623,6 +4804,7 @@ EmitDone:
ERROR_HANDLER(InvalidAddressIndex)
ERROR_HANDLER(InvalidAddress64Bit)
ERROR_HANDLER(InvalidDisplacement)
+ ERROR_HANDLER(InvalidPhysId)
ERROR_HANDLER(InvalidSegment)
ERROR_HANDLER(InvalidImmediate)
ERROR_HANDLER(OperandSizeMismatch)
diff --git a/src/asmjit/x86/x86builder.cpp b/src/asmjit/x86/x86builder.cpp
index b3c0b26..8f9c63c 100644
--- a/src/asmjit/x86/x86builder.cpp
+++ b/src/asmjit/x86/x86builder.cpp
@@ -48,7 +48,7 @@ Error Builder::finalize() {
Assembler a(_code);
a.addEncodingOptions(encodingOptions());
a.addValidationOptions(validationOptions());
- return serialize(&a);
+ return serializeTo(&a);
}
// ============================================================================
diff --git a/src/asmjit/x86/x86compiler.cpp b/src/asmjit/x86/x86compiler.cpp
index 33377e9..c087548 100644
--- a/src/asmjit/x86/x86compiler.cpp
+++ b/src/asmjit/x86/x86compiler.cpp
@@ -49,7 +49,7 @@ Error Compiler::finalize() {
Assembler a(_code);
a.addEncodingOptions(encodingOptions());
a.addValidationOptions(validationOptions());
- return serialize(&a);
+ return serializeTo(&a);
}
// ============================================================================
// [asmjit::x86::Compiler - Events]
diff --git a/src/asmjit/x86/x86emitter.h b/src/asmjit/x86/x86emitter.h
index 561acdd..e984244 100644
--- a/src/asmjit/x86/x86emitter.h
+++ b/src/asmjit/x86/x86emitter.h
@@ -506,7 +506,7 @@ public:
//! \}
- //! \name Base Instructions & GP Extensions
+ //! \name Core Instructions
//! \{
ASMJIT_INST_2x(adc, Adc, Gp, Gp) // ANY
@@ -524,8 +524,6 @@ public:
ASMJIT_INST_2i(and_, And, Gp, Imm) // ANY
ASMJIT_INST_2x(and_, And, Mem, Gp) // ANY
ASMJIT_INST_2i(and_, And, Mem, Imm) // ANY
- ASMJIT_INST_2x(arpl, Arpl, Gp, Gp) // X86
- ASMJIT_INST_2x(arpl, Arpl, Mem, Gp) // X86
ASMJIT_INST_2x(bound, Bound, Gp, Mem) // X86
ASMJIT_INST_2x(bsf, Bsf, Gp, Gp) // ANY
ASMJIT_INST_2x(bsf, Bsf, Gp, Mem) // ANY
@@ -548,21 +546,16 @@ public:
ASMJIT_INST_2i(bts, Bts, Gp, Imm) // ANY
ASMJIT_INST_2x(bts, Bts, Mem, Gp) // ANY
ASMJIT_INST_2i(bts, Bts, Mem, Imm) // ANY
- ASMJIT_INST_1x(cbw, Cbw, AX) // ANY [EXPLICIT] AX <- Sign Extend AL
- ASMJIT_INST_2x(cdq, Cdq, EDX, EAX) // ANY [EXPLICIT] EDX:EAX <- Sign Extend EAX
- ASMJIT_INST_1x(cdqe, Cdqe, EAX) // X64 [EXPLICIT] RAX <- Sign Extend EAX
- ASMJIT_INST_2x(cqo, Cqo, RDX, RAX) // X64 [EXPLICIT] RDX:RAX <- Sign Extend RAX
- ASMJIT_INST_2x(cwd, Cwd, DX, AX) // ANY [EXPLICIT] DX:AX <- Sign Extend AX
- ASMJIT_INST_1x(cwde, Cwde, EAX) // ANY [EXPLICIT] EAX <- Sign Extend AX
+ ASMJIT_INST_1x(cbw, Cbw, AX) // ANY [EXPLICIT] AX <- Sign Extend AL
+ ASMJIT_INST_2x(cdq, Cdq, EDX, EAX) // ANY [EXPLICIT] EDX:EAX <- Sign Extend EAX
+ ASMJIT_INST_1x(cdqe, Cdqe, EAX) // X64 [EXPLICIT] RAX <- Sign Extend EAX
+ ASMJIT_INST_2x(cqo, Cqo, RDX, RAX) // X64 [EXPLICIT] RDX:RAX <- Sign Extend RAX
+ ASMJIT_INST_2x(cwd, Cwd, DX, AX) // ANY [EXPLICIT] DX:AX <- Sign Extend AX
+ ASMJIT_INST_1x(cwde, Cwde, EAX) // ANY [EXPLICIT] EAX <- Sign Extend AX
ASMJIT_INST_1x(call, Call, Gp) // ANY
ASMJIT_INST_1x(call, Call, Mem) // ANY
ASMJIT_INST_1x(call, Call, Label) // ANY
ASMJIT_INST_1i(call, Call, Imm) // ANY
- ASMJIT_INST_0x(clc, Clc) // ANY
- ASMJIT_INST_0x(cld, Cld) // ANY
- ASMJIT_INST_0x(cli, Cli) // ANY
- ASMJIT_INST_0x(clts, Clts) // ANY
- ASMJIT_INST_0x(cmc, Cmc) // ANY
ASMJIT_INST_2c(cmov, Cmov, Condition::toCmovcc, Gp, Gp) // CMOV
ASMJIT_INST_2c(cmov, Cmov, Condition::toCmovcc, Gp, Mem) // CMOV
ASMJIT_INST_2x(cmp, Cmp, Gp, Gp) // ANY
@@ -570,89 +563,52 @@ public:
ASMJIT_INST_2i(cmp, Cmp, Gp, Imm) // ANY
ASMJIT_INST_2x(cmp, Cmp, Mem, Gp) // ANY
ASMJIT_INST_2i(cmp, Cmp, Mem, Imm) // ANY
- ASMJIT_INST_2x(cmps, Cmps, DS_ZSI, ES_ZDI) // ANY [EXPLICIT]
- ASMJIT_INST_3x(cmpxchg, Cmpxchg, Gp, Gp, ZAX) // I486 [EXPLICIT]
- ASMJIT_INST_3x(cmpxchg, Cmpxchg, Mem, Gp, ZAX) // I486 [EXPLICIT]
- ASMJIT_INST_5x(cmpxchg16b, Cmpxchg16b, Mem, RDX, RAX, RCX, RBX); // CMPXCHG16B[EXPLICIT] m == EDX:EAX ? m <- ECX:EBX
+ ASMJIT_INST_2x(cmps, Cmps, DS_ZSI, ES_ZDI) // ANY [EXPLICIT]
+ ASMJIT_INST_3x(cmpxchg, Cmpxchg, Gp, Gp, ZAX) // I486 [EXPLICIT]
+ ASMJIT_INST_3x(cmpxchg, Cmpxchg, Mem, Gp, ZAX) // I486 [EXPLICIT]
+ ASMJIT_INST_5x(cmpxchg16b, Cmpxchg16b, Mem, RDX, RAX, RCX, RBX); // CMPXCHG16B [EXPLICIT] m == EDX:EAX ? m <- ECX:EBX
ASMJIT_INST_5x(cmpxchg8b, Cmpxchg8b, Mem, EDX, EAX, ECX, EBX); // CMPXCHG8B [EXPLICIT] m == RDX:RAX ? m <- RCX:RBX
- ASMJIT_INST_4x(cpuid, Cpuid, EAX, EBX, ECX, EDX) // I486 [EXPLICIT] EAX:EBX:ECX:EDX <- CPUID[EAX:ECX]
- ASMJIT_INST_1x(daa, Daa, Gp) // X86 [EXPLICIT]
- ASMJIT_INST_1x(das, Das, Gp) // X86 [EXPLICIT]
ASMJIT_INST_1x(dec, Dec, Gp) // ANY
ASMJIT_INST_1x(dec, Dec, Mem) // ANY
- ASMJIT_INST_2x(div, Div, Gp, Gp) // ANY [EXPLICIT] AH[Rem]: AL[Quot] <- AX / r8
- ASMJIT_INST_2x(div, Div, Gp, Mem) // ANY [EXPLICIT] AH[Rem]: AL[Quot] <- AX / m8
- ASMJIT_INST_3x(div, Div, Gp, Gp, Gp) // ANY [EXPLICIT] xDX[Rem]:xAX[Quot] <- xDX:xAX / r16|r32|r64
- ASMJIT_INST_3x(div, Div, Gp, Gp, Mem) // ANY [EXPLICIT] xDX[Rem]:xAX[Quot] <- xDX:xAX / m16|m32|m64
- ASMJIT_INST_0x(emms, Emms) // MMX
- ASMJIT_INST_2x(enter, Enter, Imm, Imm) // ANY
- ASMJIT_INST_0x(hlt, Hlt) // ANY
- ASMJIT_INST_2x(idiv, Idiv, Gp, Gp) // ANY [EXPLICIT] AH[Rem]: AL[Quot] <- AX / r8
- ASMJIT_INST_2x(idiv, Idiv, Gp, Mem) // ANY [EXPLICIT] AH[Rem]: AL[Quot] <- AX / m8
- ASMJIT_INST_3x(idiv, Idiv, Gp, Gp, Gp) // ANY [EXPLICIT] xDX[Rem]:xAX[Quot] <- xDX:xAX / r16|r32|r64
- ASMJIT_INST_3x(idiv, Idiv, Gp, Gp, Mem) // ANY [EXPLICIT] xDX[Rem]:xAX[Quot] <- xDX:xAX / m16|m32|m64
- ASMJIT_INST_2x(imul, Imul, Gp, Gp) // ANY [EXPLICIT] AX <- AL * r8 | ra <- ra * rb
- ASMJIT_INST_2x(imul, Imul, Gp, Mem) // ANY [EXPLICIT] AX <- AL * m8 | ra <- ra * m16|m32|m64
+ ASMJIT_INST_2x(div, Div, Gp, Gp) // ANY [EXPLICIT] AH[Rem]: AL[Quot] <- AX / r8
+ ASMJIT_INST_2x(div, Div, Gp, Mem) // ANY [EXPLICIT] AH[Rem]: AL[Quot] <- AX / m8
+ ASMJIT_INST_3x(div, Div, Gp, Gp, Gp) // ANY [EXPLICIT] xDX[Rem]:xAX[Quot] <- xDX:xAX / r16|r32|r64
+ ASMJIT_INST_3x(div, Div, Gp, Gp, Mem) // ANY [EXPLICIT] xDX[Rem]:xAX[Quot] <- xDX:xAX / m16|m32|m64
+ ASMJIT_INST_2x(idiv, Idiv, Gp, Gp) // ANY [EXPLICIT] AH[Rem]: AL[Quot] <- AX / r8
+ ASMJIT_INST_2x(idiv, Idiv, Gp, Mem) // ANY [EXPLICIT] AH[Rem]: AL[Quot] <- AX / m8
+ ASMJIT_INST_3x(idiv, Idiv, Gp, Gp, Gp) // ANY [EXPLICIT] xDX[Rem]:xAX[Quot] <- xDX:xAX / r16|r32|r64
+ ASMJIT_INST_3x(idiv, Idiv, Gp, Gp, Mem) // ANY [EXPLICIT] xDX[Rem]:xAX[Quot] <- xDX:xAX / m16|m32|m64
+ ASMJIT_INST_2x(imul, Imul, Gp, Gp) // ANY [EXPLICIT] AX <- AL * r8 | ra <- ra * rb
+ ASMJIT_INST_2x(imul, Imul, Gp, Mem) // ANY [EXPLICIT] AX <- AL * m8 | ra <- ra * m16|m32|m64
ASMJIT_INST_2i(imul, Imul, Gp, Imm) // ANY
ASMJIT_INST_3i(imul, Imul, Gp, Gp, Imm) // ANY
ASMJIT_INST_3i(imul, Imul, Gp, Mem, Imm) // ANY
- ASMJIT_INST_3x(imul, Imul, Gp, Gp, Gp) // ANY [EXPLICIT] xDX:xAX <- xAX * r16|r32|r64
- ASMJIT_INST_3x(imul, Imul, Gp, Gp, Mem) // ANY [EXPLICIT] xDX:xAX <- xAX * m16|m32|m64
- ASMJIT_INST_2i(in, In, ZAX, Imm) // ANY
- ASMJIT_INST_2x(in, In, ZAX, DX) // ANY
+ ASMJIT_INST_3x(imul, Imul, Gp, Gp, Gp) // ANY [EXPLICIT] xDX:xAX <- xAX * r16|r32|r64
+ ASMJIT_INST_3x(imul, Imul, Gp, Gp, Mem) // ANY [EXPLICIT] xDX:xAX <- xAX * m16|m32|m64
ASMJIT_INST_1x(inc, Inc, Gp) // ANY
ASMJIT_INST_1x(inc, Inc, Mem) // ANY
- ASMJIT_INST_2x(ins, Ins, ES_ZDI, DX) // ANY
- ASMJIT_INST_1i(int_, Int, Imm) // ANY
- ASMJIT_INST_0x(int3, Int3) // ANY
- ASMJIT_INST_0x(into, Into) // ANY
- ASMJIT_INST_0x(invd, Invd) // ANY
- ASMJIT_INST_1x(invlpg, Invlpg, Mem) // ANY
- ASMJIT_INST_2x(invpcid, Invpcid, Gp, Mem) // ANY
ASMJIT_INST_1c(j, J, Condition::toJcc, Label) // ANY
ASMJIT_INST_1c(j, J, Condition::toJcc, Imm) // ANY
ASMJIT_INST_1c(j, J, Condition::toJcc, uint64_t) // ANY
- ASMJIT_INST_2x(jecxz, Jecxz, Gp, Label) // ANY [EXPLICIT] Short jump if CX/ECX/RCX is zero.
- ASMJIT_INST_2x(jecxz, Jecxz, Gp, Imm) // ANY [EXPLICIT] Short jump if CX/ECX/RCX is zero.
- ASMJIT_INST_2x(jecxz, Jecxz, Gp, uint64_t) // ANY [EXPLICIT] Short jump if CX/ECX/RCX is zero.
+ ASMJIT_INST_2x(jecxz, Jecxz, Gp, Label) // ANY [EXPLICIT] Short jump if CX/ECX/RCX is zero.
+ ASMJIT_INST_2x(jecxz, Jecxz, Gp, Imm) // ANY [EXPLICIT] Short jump if CX/ECX/RCX is zero.
+ ASMJIT_INST_2x(jecxz, Jecxz, Gp, uint64_t) // ANY [EXPLICIT] Short jump if CX/ECX/RCX is zero.
ASMJIT_INST_1x(jmp, Jmp, Gp) // ANY
ASMJIT_INST_1x(jmp, Jmp, Mem) // ANY
ASMJIT_INST_1x(jmp, Jmp, Label) // ANY
ASMJIT_INST_1x(jmp, Jmp, Imm) // ANY
ASMJIT_INST_1x(jmp, Jmp, uint64_t) // ANY
- ASMJIT_INST_1x(lahf, Lahf, AH) // LAHFSAHF [EXPLICIT] AH <- EFL
- ASMJIT_INST_2x(lar, Lar, Gp, Gp) // ANY
- ASMJIT_INST_2x(lar, Lar, Gp, Mem) // ANY
- ASMJIT_INST_1x(ldmxcsr, Ldmxcsr, Mem) // SSE
- ASMJIT_INST_2x(lds, Lds, Gp, Mem) // X86
ASMJIT_INST_2x(lea, Lea, Gp, Mem) // ANY
- ASMJIT_INST_0x(leave, Leave) // ANY
- ASMJIT_INST_2x(les, Les, Gp, Mem) // X86
- ASMJIT_INST_0x(lfence, Lfence) // SSE2
- ASMJIT_INST_2x(lfs, Lfs, Gp, Mem) // ANY
- ASMJIT_INST_1x(lgdt, Lgdt, Mem) // ANY
- ASMJIT_INST_2x(lgs, Lgs, Gp, Mem) // ANY
- ASMJIT_INST_1x(lidt, Lidt, Mem) // ANY
- ASMJIT_INST_1x(lldt, Lldt, Gp) // ANY
- ASMJIT_INST_1x(lldt, Lldt, Mem) // ANY
- ASMJIT_INST_1x(lmsw, Lmsw, Gp) // ANY
- ASMJIT_INST_1x(lmsw, Lmsw, Mem) // ANY
- ASMJIT_INST_2x(lods, Lods, ZAX, DS_ZSI) // ANY [EXPLICIT]
- ASMJIT_INST_2x(loop, Loop, ZCX, Label) // ANY [EXPLICIT] Decrement xCX; short jump if xCX != 0.
- ASMJIT_INST_2x(loop, Loop, ZCX, Imm) // ANY [EXPLICIT] Decrement xCX; short jump if xCX != 0.
- ASMJIT_INST_2x(loop, Loop, ZCX, uint64_t) // ANY [EXPLICIT] Decrement xCX; short jump if xCX != 0.
- ASMJIT_INST_2x(loope, Loope, ZCX, Label) // ANY [EXPLICIT] Decrement xCX; short jump if xCX != 0 && ZF == 1.
- ASMJIT_INST_2x(loope, Loope, ZCX, Imm) // ANY [EXPLICIT] Decrement xCX; short jump if xCX != 0 && ZF == 1.
- ASMJIT_INST_2x(loope, Loope, ZCX, uint64_t) // ANY [EXPLICIT] Decrement xCX; short jump if xCX != 0 && ZF == 1.
- ASMJIT_INST_2x(loopne, Loopne, ZCX, Label) // ANY [EXPLICIT] Decrement xCX; short jump if xCX != 0 && ZF == 0.
- ASMJIT_INST_2x(loopne, Loopne, ZCX, Imm) // ANY [EXPLICIT] Decrement xCX; short jump if xCX != 0 && ZF == 0.
- ASMJIT_INST_2x(loopne, Loopne, ZCX, uint64_t) // ANY [EXPLICIT] Decrement xCX; short jump if xCX != 0 && ZF == 0.
- ASMJIT_INST_2x(lsl, Lsl, Gp, Gp) // ANY
- ASMJIT_INST_2x(lsl, Lsl, Gp, Mem) // ANY
- ASMJIT_INST_2x(lss, Lss, Gp, Mem) // ANY
- ASMJIT_INST_1x(ltr, Ltr, Gp) // ANY
- ASMJIT_INST_1x(ltr, Ltr, Mem) // ANY
- ASMJIT_INST_0x(mfence, Mfence) // SSE2
+ ASMJIT_INST_2x(lods, Lods, ZAX, DS_ZSI) // ANY [EXPLICIT]
+ ASMJIT_INST_2x(loop, Loop, ZCX, Label) // ANY [EXPLICIT] Decrement xCX; short jump if xCX != 0.
+ ASMJIT_INST_2x(loop, Loop, ZCX, Imm) // ANY [EXPLICIT] Decrement xCX; short jump if xCX != 0.
+ ASMJIT_INST_2x(loop, Loop, ZCX, uint64_t) // ANY [EXPLICIT] Decrement xCX; short jump if xCX != 0.
+ ASMJIT_INST_2x(loope, Loope, ZCX, Label) // ANY [EXPLICIT] Decrement xCX; short jump if xCX != 0 && ZF == 1.
+ ASMJIT_INST_2x(loope, Loope, ZCX, Imm) // ANY [EXPLICIT] Decrement xCX; short jump if xCX != 0 && ZF == 1.
+ ASMJIT_INST_2x(loope, Loope, ZCX, uint64_t) // ANY [EXPLICIT] Decrement xCX; short jump if xCX != 0 && ZF == 1.
+ ASMJIT_INST_2x(loopne, Loopne, ZCX, Label) // ANY [EXPLICIT] Decrement xCX; short jump if xCX != 0 && ZF == 0.
+ ASMJIT_INST_2x(loopne, Loopne, ZCX, Imm) // ANY [EXPLICIT] Decrement xCX; short jump if xCX != 0 && ZF == 0.
+ ASMJIT_INST_2x(loopne, Loopne, ZCX, uint64_t) // ANY [EXPLICIT] Decrement xCX; short jump if xCX != 0 && ZF == 0.
ASMJIT_INST_2x(mov, Mov, Gp, Gp) // ANY
ASMJIT_INST_2x(mov, Mov, Gp, Mem) // ANY
ASMJIT_INST_2i(mov, Mov, Gp, Imm) // ANY
@@ -667,17 +623,17 @@ public:
ASMJIT_INST_2x(mov, Mov, SReg, Gp) // ANY
ASMJIT_INST_2x(mov, Mov, SReg, Mem) // ANY
ASMJIT_INST_2x(movnti, Movnti, Mem, Gp) // SSE2
- ASMJIT_INST_2x(movs, Movs, ES_ZDI, DS_ZSI) // ANY [EXPLICIT]
+ ASMJIT_INST_2x(movs, Movs, ES_ZDI, DS_ZSI) // ANY [EXPLICIT]
ASMJIT_INST_2x(movsx, Movsx, Gp, Gp) // ANY
ASMJIT_INST_2x(movsx, Movsx, Gp, Mem) // ANY
ASMJIT_INST_2x(movsxd, Movsxd, Gp, Gp) // X64
ASMJIT_INST_2x(movsxd, Movsxd, Gp, Mem) // X64
ASMJIT_INST_2x(movzx, Movzx, Gp, Gp) // ANY
ASMJIT_INST_2x(movzx, Movzx, Gp, Mem) // ANY
- ASMJIT_INST_2x(mul, Mul, AX, Gp) // ANY [EXPLICIT] AX <- AL * r8
- ASMJIT_INST_2x(mul, Mul, AX, Mem) // ANY [EXPLICIT] AX <- AL * m8
- ASMJIT_INST_3x(mul, Mul, ZDX, ZAX, Gp) // ANY [EXPLICIT] xDX:xAX <- xAX * r16|r32|r64
- ASMJIT_INST_3x(mul, Mul, ZDX, ZAX, Mem) // ANY [EXPLICIT] xDX:xAX <- xAX * m16|m32|m64
+ ASMJIT_INST_2x(mul, Mul, AX, Gp) // ANY [EXPLICIT] AX <- AL * r8
+ ASMJIT_INST_2x(mul, Mul, AX, Mem) // ANY [EXPLICIT] AX <- AL * m8
+ ASMJIT_INST_3x(mul, Mul, ZDX, ZAX, Gp) // ANY [EXPLICIT] xDX:xAX <- xAX * r16|r32|r64
+ ASMJIT_INST_3x(mul, Mul, ZDX, ZAX, Mem) // ANY [EXPLICIT] xDX:xAX <- xAX * m16|m32|m64
ASMJIT_INST_1x(neg, Neg, Gp) // ANY
ASMJIT_INST_1x(neg, Neg, Mem) // ANY
ASMJIT_INST_0x(nop, Nop) // ANY
@@ -690,10 +646,6 @@ public:
ASMJIT_INST_2i(or_, Or, Gp, Imm) // ANY
ASMJIT_INST_2x(or_, Or, Mem, Gp) // ANY
ASMJIT_INST_2i(or_, Or, Mem, Imm) // ANY
- ASMJIT_INST_2x(out, Out, Imm, ZAX) // ANY
- ASMJIT_INST_2i(out, Out, DX, ZAX) // ANY
- ASMJIT_INST_2i(outs, Outs, DX, DS_ZSI) // ANY
- ASMJIT_INST_0x(pause, Pause) // SSE2
ASMJIT_INST_1x(pop, Pop, Gp) // ANY
ASMJIT_INST_1x(pop, Pop, Mem) // ANY
ASMJIT_INST_1x(pop, Pop, SReg); // ANY
@@ -702,13 +654,6 @@ public:
ASMJIT_INST_0x(popf, Popf) // ANY
ASMJIT_INST_0x(popfd, Popfd) // X86
ASMJIT_INST_0x(popfq, Popfq) // X64
- ASMJIT_INST_1x(prefetch, Prefetch, Mem) // 3DNOW
- ASMJIT_INST_1x(prefetchnta, Prefetchnta, Mem) // SSE
- ASMJIT_INST_1x(prefetcht0, Prefetcht0, Mem) // SSE
- ASMJIT_INST_1x(prefetcht1, Prefetcht1, Mem) // SSE
- ASMJIT_INST_1x(prefetcht2, Prefetcht2, Mem) // SSE
- ASMJIT_INST_1x(prefetchw, Prefetchw, Mem) // PREFETCHW
- ASMJIT_INST_1x(prefetchwt1, Prefetchwt1, Mem) // PREFETCHW1
ASMJIT_INST_1x(push, Push, Gp) // ANY
ASMJIT_INST_1x(push, Push, Mem) // ANY
ASMJIT_INST_1x(push, Push, SReg) // ANY
@@ -726,10 +671,6 @@ public:
ASMJIT_INST_2x(rcr, Rcr, Mem, CL) // ANY
ASMJIT_INST_2i(rcr, Rcr, Gp, Imm) // ANY
ASMJIT_INST_2i(rcr, Rcr, Mem, Imm) // ANY
- ASMJIT_INST_3x(rdmsr, Rdmsr, EDX, EAX, ECX) // MSR [EXPLICIT] RDX:EAX <- MSR[ECX]
- ASMJIT_INST_3x(rdpmc, Rdpmc, EDX, EAX, ECX) // ANY [EXPLICIT] RDX:EAX <- PMC[ECX]
- ASMJIT_INST_2x(rdtsc, Rdtsc, EDX, EAX) // RDTSC [EXPLICIT] EDX:EAX <- Counter
- ASMJIT_INST_3x(rdtscp, Rdtscp, EDX, EAX, ECX) // RDTSCP [EXPLICIT] EDX:EAX:EXC <- Counter
ASMJIT_INST_2x(rol, Rol, Gp, CL) // ANY
ASMJIT_INST_2x(rol, Rol, Mem, CL) // ANY
ASMJIT_INST_2i(rol, Rol, Gp, Imm) // ANY
@@ -738,13 +679,11 @@ public:
ASMJIT_INST_2x(ror, Ror, Mem, CL) // ANY
ASMJIT_INST_2i(ror, Ror, Gp, Imm) // ANY
ASMJIT_INST_2i(ror, Ror, Mem, Imm) // ANY
- ASMJIT_INST_0x(rsm, Rsm) // X86
ASMJIT_INST_2x(sbb, Sbb, Gp, Gp) // ANY
ASMJIT_INST_2x(sbb, Sbb, Gp, Mem) // ANY
ASMJIT_INST_2i(sbb, Sbb, Gp, Imm) // ANY
ASMJIT_INST_2x(sbb, Sbb, Mem, Gp) // ANY
ASMJIT_INST_2i(sbb, Sbb, Mem, Imm) // ANY
- ASMJIT_INST_1x(sahf, Sahf, AH) // LAHFSAHF [EXPLICIT] EFL <- AH
ASMJIT_INST_2x(sal, Sal, Gp, CL) // ANY
ASMJIT_INST_2x(sal, Sal, Mem, CL) // ANY
ASMJIT_INST_2i(sal, Sal, Gp, Imm) // ANY
@@ -753,11 +692,9 @@ public:
ASMJIT_INST_2x(sar, Sar, Mem, CL) // ANY
ASMJIT_INST_2i(sar, Sar, Gp, Imm) // ANY
ASMJIT_INST_2i(sar, Sar, Mem, Imm) // ANY
- ASMJIT_INST_2x(scas, Scas, ZAX, ES_ZDI) // ANY [EXPLICIT]
+ ASMJIT_INST_2x(scas, Scas, ZAX, ES_ZDI) // ANY [EXPLICIT]
ASMJIT_INST_1c(set, Set, Condition::toSetcc, Gp) // ANY
ASMJIT_INST_1c(set, Set, Condition::toSetcc, Mem) // ANY
- ASMJIT_INST_0x(sfence, Sfence) // SSE
- ASMJIT_INST_1x(sgdt, Sgdt, Mem) // ANY
ASMJIT_INST_2x(shl, Shl, Gp, CL) // ANY
ASMJIT_INST_2x(shl, Shl, Mem, CL) // ANY
ASMJIT_INST_2i(shl, Shl, Gp, Imm) // ANY
@@ -774,34 +711,17 @@ public:
ASMJIT_INST_3x(shrd, Shrd, Mem, Gp, CL) // ANY
ASMJIT_INST_3i(shrd, Shrd, Gp, Gp, Imm) // ANY
ASMJIT_INST_3i(shrd, Shrd, Mem, Gp, Imm) // ANY
- ASMJIT_INST_1x(sidt, Sidt, Mem) // ANY
- ASMJIT_INST_1x(sldt, Sldt, Gp) // ANY
- ASMJIT_INST_1x(sldt, Sldt, Mem) // ANY
- ASMJIT_INST_1x(smsw, Smsw, Gp) // ANY
- ASMJIT_INST_1x(smsw, Smsw, Mem) // ANY
- ASMJIT_INST_0x(stc, Stc) // ANY
- ASMJIT_INST_0x(std, Std) // ANY
- ASMJIT_INST_0x(sti, Sti) // ANY
- ASMJIT_INST_1x(stmxcsr, Stmxcsr, Mem) // SSE
- ASMJIT_INST_2x(stos, Stos, ES_ZDI, ZAX) // ANY [EXPLICIT]
- ASMJIT_INST_1x(str, Str, Gp) // ANY
- ASMJIT_INST_1x(str, Str, Mem) // ANY
+ ASMJIT_INST_2x(stos, Stos, ES_ZDI, ZAX) // ANY [EXPLICIT]
ASMJIT_INST_2x(sub, Sub, Gp, Gp) // ANY
ASMJIT_INST_2x(sub, Sub, Gp, Mem) // ANY
ASMJIT_INST_2i(sub, Sub, Gp, Imm) // ANY
ASMJIT_INST_2x(sub, Sub, Mem, Gp) // ANY
ASMJIT_INST_2i(sub, Sub, Mem, Imm) // ANY
- ASMJIT_INST_0x(swapgs, Swapgs) // X64
ASMJIT_INST_2x(test, Test, Gp, Gp) // ANY
ASMJIT_INST_2i(test, Test, Gp, Imm) // ANY
ASMJIT_INST_2x(test, Test, Mem, Gp) // ANY
ASMJIT_INST_2i(test, Test, Mem, Imm) // ANY
ASMJIT_INST_0x(ud2, Ud2) // ANY
- ASMJIT_INST_1x(verr, Verr, Gp) // ANY
- ASMJIT_INST_1x(verr, Verr, Mem) // ANY
- ASMJIT_INST_1x(verw, Verw, Gp) // ANY
- ASMJIT_INST_1x(verw, Verw, Mem) // ANY
- ASMJIT_INST_3x(wrmsr, Wrmsr, EDX, EAX, ECX) // MSR [EXPLICIT] RDX:EAX -> MSR[ECX]
ASMJIT_INST_2x(xadd, Xadd, Gp, Gp) // ANY
ASMJIT_INST_2x(xadd, Xadd, Mem, Gp) // ANY
ASMJIT_INST_2x(xchg, Xchg, Gp, Gp) // ANY
@@ -815,6 +735,57 @@ public:
//! \}
+ //! \name Deprecated 32-bit Instructions
+ //! \{
+
+ ASMJIT_INST_1x(aaa, Aaa, Gp) // X86 [EXPLICIT]
+ ASMJIT_INST_2i(aad, Aad, Gp, Imm) // X86 [EXPLICIT]
+ ASMJIT_INST_2i(aam, Aam, Gp, Imm) // X86 [EXPLICIT]
+ ASMJIT_INST_1x(aas, Aas, Gp) // X86 [EXPLICIT]
+ ASMJIT_INST_1x(daa, Daa, Gp) // X86 [EXPLICIT]
+ ASMJIT_INST_1x(das, Das, Gp) // X86 [EXPLICIT]
+
+ //! \}
+
+ //! \name ENTER/LEAVE Instructions
+ //! \{
+
+ ASMJIT_INST_2x(enter, Enter, Imm, Imm) // ANY
+ ASMJIT_INST_0x(leave, Leave) // ANY
+
+ //! \}
+
+ //! \name In/Out Instructions
+ //! \{
+
+ ASMJIT_INST_2i(in, In, ZAX, Imm) // ANY
+ ASMJIT_INST_2x(in, In, ZAX, DX) // ANY
+ ASMJIT_INST_2x(ins, Ins, ES_ZDI, DX) // ANY
+ ASMJIT_INST_2x(out, Out, Imm, ZAX) // ANY
+ ASMJIT_INST_2i(out, Out, DX, ZAX) // ANY
+ ASMJIT_INST_2i(outs, Outs, DX, DS_ZSI) // ANY
+
+ //! \}
+
+ //! \name Clear/Set CL/DF Instructions
+ //! \{
+
+ ASMJIT_INST_0x(clc, Clc) // ANY
+ ASMJIT_INST_0x(cld, Cld) // ANY
+ ASMJIT_INST_0x(cmc, Cmc) // ANY
+ ASMJIT_INST_0x(stc, Stc) // ANY
+ ASMJIT_INST_0x(std, Std) // ANY
+
+ //! \}
+
+ //! \name LAHF/SAHF Instructions
+ //! \{
+
+ ASMJIT_INST_1x(lahf, Lahf, AH) // LAHFSAHF [EXPLICIT] AH <- EFL
+ ASMJIT_INST_1x(sahf, Sahf, AH) // LAHFSAHF [EXPLICIT] EFL <- AH
+
+ //! \}
+
//! \name ADX Instructions
//! \{
@@ -825,6 +796,16 @@ public:
//! \}
+ //! \name LZCNT/POPCNT Instructions
+ //! \{
+
+ ASMJIT_INST_2x(lzcnt, Lzcnt, Gp, Gp) // LZCNT
+ ASMJIT_INST_2x(lzcnt, Lzcnt, Gp, Mem) // LZCNT
+ ASMJIT_INST_2x(popcnt, Popcnt, Gp, Gp) // POPCNT
+ ASMJIT_INST_2x(popcnt, Popcnt, Gp, Mem) // POPCNT
+
+ //! \}
+
//! \name BMI Instructions
//! \{
@@ -865,89 +846,192 @@ public:
//! \}
- //! \name CL Instructions
+ //! \name TBM Instructions
+ //! \{
+
+ ASMJIT_INST_2x(blcfill, Blcfill, Gp, Gp) // TBM
+ ASMJIT_INST_2x(blcfill, Blcfill, Gp, Mem) // TBM
+ ASMJIT_INST_2x(blci, Blci, Gp, Gp) // TBM
+ ASMJIT_INST_2x(blci, Blci, Gp, Mem) // TBM
+ ASMJIT_INST_2x(blcic, Blcic, Gp, Gp) // TBM
+ ASMJIT_INST_2x(blcic, Blcic, Gp, Mem) // TBM
+ ASMJIT_INST_2x(blcmsk, Blcmsk, Gp, Gp) // TBM
+ ASMJIT_INST_2x(blcmsk, Blcmsk, Gp, Mem) // TBM
+ ASMJIT_INST_2x(blcs, Blcs, Gp, Gp) // TBM
+ ASMJIT_INST_2x(blcs, Blcs, Gp, Mem) // TBM
+ ASMJIT_INST_2x(blsfill, Blsfill, Gp, Gp) // TBM
+ ASMJIT_INST_2x(blsfill, Blsfill, Gp, Mem) // TBM
+ ASMJIT_INST_2x(blsic, Blsic, Gp, Gp) // TBM
+ ASMJIT_INST_2x(blsic, Blsic, Gp, Mem) // TBM
+ ASMJIT_INST_2x(t1mskc, T1mskc, Gp, Gp) // TBM
+ ASMJIT_INST_2x(t1mskc, T1mskc, Gp, Mem) // TBM
+ ASMJIT_INST_2x(tzmsk, Tzmsk, Gp, Gp) // TBM
+ ASMJIT_INST_2x(tzmsk, Tzmsk, Gp, Mem) // TBM
+
+ //! \}
+
+ //! \name CRC32 Instructions (SSE4.2)
+ //! \{
+
+ ASMJIT_INST_2x(crc32, Crc32, Gp, Gp) // SSE4_2
+ ASMJIT_INST_2x(crc32, Crc32, Gp, Mem) // SSE4_2
+
+ //! \}
+
+ //! \name MOVBE Instructions
+ //! \{
+
+ ASMJIT_INST_2x(movbe, Movbe, Gp, Mem) // MOVBE
+ ASMJIT_INST_2x(movbe, Movbe, Mem, Gp) // MOVBE
+
+ //! \}
+
+ //! \name MOVDIRI & MOVDIR64B Instructions
+ //! \{
+
+ ASMJIT_INST_2x(movdiri, Movdiri, Mem, Gp) // MOVDIRI
+ ASMJIT_INST_2x(movdir64b, Movdir64b, Mem, Mem) // MOVDIR64B
+
+ //! \}
+
+ //! \name MXCSR Instructions (SSE)
+ //! \{
+
+ ASMJIT_INST_1x(ldmxcsr, Ldmxcsr, Mem) // SSE
+ ASMJIT_INST_1x(stmxcsr, Stmxcsr, Mem) // SSE
+
+ //! \}
+
+ //! \name FENCE Instructions (SSE and SSE2)
+ //! \{
+
+ ASMJIT_INST_0x(lfence, Lfence) // SSE2
+ ASMJIT_INST_0x(mfence, Mfence) // SSE2
+ ASMJIT_INST_0x(sfence, Sfence) // SSE
+
+ //! \}
+
+ //! \name PREFETCH Instructions
+ //! \{
+
+ ASMJIT_INST_1x(prefetch, Prefetch, Mem) // 3DNOW
+ ASMJIT_INST_1x(prefetchnta, Prefetchnta, Mem) // SSE
+ ASMJIT_INST_1x(prefetcht0, Prefetcht0, Mem) // SSE
+ ASMJIT_INST_1x(prefetcht1, Prefetcht1, Mem) // SSE
+ ASMJIT_INST_1x(prefetcht2, Prefetcht2, Mem) // SSE
+ ASMJIT_INST_1x(prefetchw, Prefetchw, Mem) // PREFETCHW
+ ASMJIT_INST_1x(prefetchwt1, Prefetchwt1, Mem) // PREFETCHW1
+
+ //! \}
+
+ //! \name CPUID Instruction
+ //! \{
+
+ ASMJIT_INST_4x(cpuid, Cpuid, EAX, EBX, ECX, EDX) // I486 [EXPLICIT] EAX:EBX:ECX:EDX <- CPUID[EAX:ECX]
+
+ //! \}
+
+ //! \name CacheLine Instructions
//! \{
ASMJIT_INST_1x(cldemote, Cldemote, Mem) // CLDEMOTE
ASMJIT_INST_1x(clflush, Clflush, Mem) // CLFLUSH
ASMJIT_INST_1x(clflushopt, Clflushopt, Mem) // CLFLUSH_OPT
ASMJIT_INST_1x(clwb, Clwb, Mem) // CLWB
- ASMJIT_INST_1x(clzero, Clzero, DS_ZAX) // CLZERO [EXPLICIT]
- ASMJIT_INST_0x(wbnoinvd, Wbnoinvd) // WBNOINVD
+ ASMJIT_INST_1x(clzero, Clzero, DS_ZAX) // CLZERO [EXPLICIT]
//! \}
- //! \name CRC32 Instructions
+ //! \name SERIALIZE Instruction
//! \{
- ASMJIT_INST_2x(crc32, Crc32, Gp, Gp) // SSE4_2
- ASMJIT_INST_2x(crc32, Crc32, Gp, Mem) // SSE4_2
+ ASMJIT_INST_0x(serialize, Serialize) // SERIALIZE
//! \}
- //! \name ENQCMD Instructions
+ //! \name RDPID Instruction
//! \{
- ASMJIT_INST_2x(enqcmd, Enqcmd, Mem, Mem) // ENQCMD
- ASMJIT_INST_2x(enqcmds, Enqcmds, Mem, Mem) // ENQCMD
+ ASMJIT_INST_1x(rdpid, Rdpid, Gp) // RDPID
//! \}
- //! \name FSGSBASE Instructions
+ //! \name RDPRU Instruction
//! \{
- ASMJIT_INST_1x(rdfsbase, Rdfsbase, Gp) // FSGSBASE
- ASMJIT_INST_1x(rdgsbase, Rdgsbase, Gp) // FSGSBASE
- ASMJIT_INST_1x(wrfsbase, Wrfsbase, Gp) // FSGSBASE
- ASMJIT_INST_1x(wrgsbase, Wrgsbase, Gp) // FSGSBASE
+ ASMJIT_INST_3x(rdpru, Rdpru, ECX, EDX, EAX) // RDPRU [EXPLICIT] EDX:EAX <- PRU[ECX]
//! \}
- //! \name FXSR & XSAVE Instructions
+ //! \name RDTSC/RDTSCP Instructions
//! \{
- ASMJIT_INST_1x(fxrstor, Fxrstor, Mem) // FXSR
- ASMJIT_INST_1x(fxrstor64, Fxrstor64, Mem) // FXSR
- ASMJIT_INST_1x(fxsave, Fxsave, Mem) // FXSR
- ASMJIT_INST_1x(fxsave64, Fxsave64, Mem) // FXSR
- ASMJIT_INST_3x(xgetbv, Xgetbv, EDX, EAX, ECX) // XSAVE [EXPLICIT] EDX:EAX <- XCR[ECX]
- ASMJIT_INST_3x(xsetbv, Xsetbv, EDX, EAX, ECX) // XSAVE [EXPLICIT] XCR[ECX] <- EDX:EAX
+ ASMJIT_INST_2x(rdtsc, Rdtsc, EDX, EAX) // RDTSC [EXPLICIT] EDX:EAX <- Counter
+ ASMJIT_INST_3x(rdtscp, Rdtscp, EDX, EAX, ECX) // RDTSCP [EXPLICIT] EDX:EAX:EXC <- Counter
//! \}
- //! \name LWP Instructions
+ //! \name Other User-Mode Instructions
//! \{
- ASMJIT_INST_1x(llwpcb, Llwpcb, Gp) // LWP
- ASMJIT_INST_3i(lwpins, Lwpins, Gp, Gp, Imm) // LWP
- ASMJIT_INST_3i(lwpins, Lwpins, Gp, Mem, Imm) // LWP
- ASMJIT_INST_3i(lwpval, Lwpval, Gp, Gp, Imm) // LWP
- ASMJIT_INST_3i(lwpval, Lwpval, Gp, Mem, Imm) // LWP
- ASMJIT_INST_1x(slwpcb, Slwpcb, Gp) // LWP
+ ASMJIT_INST_2x(arpl, Arpl, Gp, Gp) // X86
+ ASMJIT_INST_2x(arpl, Arpl, Mem, Gp) // X86
+ ASMJIT_INST_0x(cli, Cli) // ANY
+ ASMJIT_INST_0x(getsec, Getsec) // SMX
+ ASMJIT_INST_1i(int_, Int, Imm) // ANY
+ ASMJIT_INST_0x(int3, Int3) // ANY
+ ASMJIT_INST_0x(into, Into) // ANY
+ ASMJIT_INST_2x(lar, Lar, Gp, Gp) // ANY
+ ASMJIT_INST_2x(lar, Lar, Gp, Mem) // ANY
+ ASMJIT_INST_2x(lds, Lds, Gp, Mem) // X86
+ ASMJIT_INST_2x(les, Les, Gp, Mem) // X86
+ ASMJIT_INST_2x(lfs, Lfs, Gp, Mem) // ANY
+ ASMJIT_INST_2x(lgs, Lgs, Gp, Mem) // ANY
+ ASMJIT_INST_2x(lsl, Lsl, Gp, Gp) // ANY
+ ASMJIT_INST_2x(lsl, Lsl, Gp, Mem) // ANY
+ ASMJIT_INST_2x(lss, Lss, Gp, Mem) // ANY
+ ASMJIT_INST_0x(pause, Pause) // SSE2
+ ASMJIT_INST_0x(rsm, Rsm) // X86
+ ASMJIT_INST_1x(sgdt, Sgdt, Mem) // ANY
+ ASMJIT_INST_1x(sidt, Sidt, Mem) // ANY
+ ASMJIT_INST_1x(sldt, Sldt, Gp) // ANY
+ ASMJIT_INST_1x(sldt, Sldt, Mem) // ANY
+ ASMJIT_INST_1x(smsw, Smsw, Gp) // ANY
+ ASMJIT_INST_1x(smsw, Smsw, Mem) // ANY
+ ASMJIT_INST_0x(sti, Sti) // ANY
+ ASMJIT_INST_1x(str, Str, Gp) // ANY
+ ASMJIT_INST_1x(str, Str, Mem) // ANY
+ ASMJIT_INST_1x(verr, Verr, Gp) // ANY
+ ASMJIT_INST_1x(verr, Verr, Mem) // ANY
+ ASMJIT_INST_1x(verw, Verw, Gp) // ANY
+ ASMJIT_INST_1x(verw, Verw, Mem) // ANY
//! \}
- //! \name LZCNT Instructions
+ //! \name FSGSBASE Instructions
//! \{
- ASMJIT_INST_2x(lzcnt, Lzcnt, Gp, Gp) // LZCNT
- ASMJIT_INST_2x(lzcnt, Lzcnt, Gp, Mem) // LZCNT
+ ASMJIT_INST_1x(rdfsbase, Rdfsbase, Gp) // FSGSBASE
+ ASMJIT_INST_1x(rdgsbase, Rdgsbase, Gp) // FSGSBASE
+ ASMJIT_INST_1x(wrfsbase, Wrfsbase, Gp) // FSGSBASE
+ ASMJIT_INST_1x(wrgsbase, Wrgsbase, Gp) // FSGSBASE
//! \}
- //! \name MOVBE Instructions
+ //! \name FXSR Instructions
//! \{
- ASMJIT_INST_2x(movbe, Movbe, Gp, Mem) // MOVBE
- ASMJIT_INST_2x(movbe, Movbe, Mem, Gp) // MOVBE
+ ASMJIT_INST_1x(fxrstor, Fxrstor, Mem) // FXSR
+ ASMJIT_INST_1x(fxrstor64, Fxrstor64, Mem) // FXSR
+ ASMJIT_INST_1x(fxsave, Fxsave, Mem) // FXSR
+ ASMJIT_INST_1x(fxsave64, Fxsave64, Mem) // FXSR
//! \}
- //! \name MOVDIRI & MOVDIR64B Instructions
+ //! \name XSAVE Instructions
//! \{
- ASMJIT_INST_2x(movdiri, Movdiri, Mem, Gp) // MOVDIRI
- ASMJIT_INST_2x(movdir64b, Movdir64b, Mem, Mem) // MOVDIR64B
+ ASMJIT_INST_3x(xgetbv, Xgetbv, EDX, EAX, ECX) // XSAVE [EXPLICIT] EDX:EAX <- XCR[ECX]
//! \}
@@ -969,11 +1053,36 @@ public:
//! \}
- //! \name POPCNT Instructions
+ //! \name MONITORX Instructions
//! \{
- ASMJIT_INST_2x(popcnt, Popcnt, Gp, Gp) // POPCNT
- ASMJIT_INST_2x(popcnt, Popcnt, Gp, Mem) // POPCNT
+ ASMJIT_INST_3x(monitorx, Monitorx, Mem, Gp, Gp)
+ ASMJIT_INST_3x(mwaitx, Mwaitx, Gp, Gp, Gp)
+
+ //! \}
+
+ //! \name PCOMMIT/MCOMMIT Instructions
+ //! \{
+
+ ASMJIT_INST_0x(pcommit, Pcommit) // PCOMMIT
+ ASMJIT_INST_0x(mcommit, Mcommit) // MCOMMIT
+
+ //! \}
+
+ //! \name ENQCMD Instructions
+ //! \{
+
+ ASMJIT_INST_2x(enqcmd, Enqcmd, Mem, Mem) // ENQCMD
+ ASMJIT_INST_2x(enqcmds, Enqcmds, Mem, Mem) // ENQCMD
+
+ //! \}
+
+ //! \name WAITPKG Instructions
+ //! \{
+
+ ASMJIT_INST_3x(tpause, Tpause, Gp, Gp, Gp)
+ ASMJIT_INST_1x(umonitor, Umonitor, Mem)
+ ASMJIT_INST_3x(umwait, Umwait, Gp, Gp, Gp)
//! \}
@@ -985,6 +1094,18 @@ public:
//! \}
+ //! \name LWP Instructions
+ //! \{
+
+ ASMJIT_INST_1x(llwpcb, Llwpcb, Gp) // LWP
+ ASMJIT_INST_3i(lwpins, Lwpins, Gp, Gp, Imm) // LWP
+ ASMJIT_INST_3i(lwpins, Lwpins, Gp, Mem, Imm) // LWP
+ ASMJIT_INST_3i(lwpval, Lwpval, Gp, Gp, Imm) // LWP
+ ASMJIT_INST_3i(lwpval, Lwpval, Gp, Mem, Imm) // LWP
+ ASMJIT_INST_1x(slwpcb, Slwpcb, Gp) // LWP
+
+ //! \}
+
//! \name RTM & TSX Instructions
//! \{
@@ -997,7 +1118,49 @@ public:
//! \}
- //! \name SMAP Instructions
+ //! \name TSXLDTRK Instructions
+ //! \{
+
+ ASMJIT_INST_0x(xresldtrk, Xresldtrk)
+ ASMJIT_INST_0x(xsusldtrk, Xsusldtrk)
+
+ //! \}
+
+ //! \name Core Privileged Instructions
+ //! \{
+
+ ASMJIT_INST_0x(clts, Clts) // ANY
+ ASMJIT_INST_0x(hlt, Hlt) // ANY
+ ASMJIT_INST_0x(invd, Invd) // ANY
+ ASMJIT_INST_1x(invlpg, Invlpg, Mem) // ANY
+ ASMJIT_INST_2x(invpcid, Invpcid, Gp, Mem) // ANY
+ ASMJIT_INST_1x(lgdt, Lgdt, Mem) // ANY
+ ASMJIT_INST_1x(lidt, Lidt, Mem) // ANY
+ ASMJIT_INST_1x(lldt, Lldt, Gp) // ANY
+ ASMJIT_INST_1x(lldt, Lldt, Mem) // ANY
+ ASMJIT_INST_1x(lmsw, Lmsw, Gp) // ANY
+ ASMJIT_INST_1x(lmsw, Lmsw, Mem) // ANY
+ ASMJIT_INST_1x(ltr, Ltr, Gp) // ANY
+ ASMJIT_INST_1x(ltr, Ltr, Mem) // ANY
+ ASMJIT_INST_3x(rdmsr, Rdmsr, EDX, EAX, ECX) // MSR [EXPLICIT] RDX:EAX <- MSR[ECX]
+ ASMJIT_INST_3x(rdpmc, Rdpmc, EDX, EAX, ECX) // ANY [EXPLICIT] RDX:EAX <- PMC[ECX]
+ ASMJIT_INST_0x(swapgs, Swapgs) // X64
+ ASMJIT_INST_0x(wbinvd, Wbinvd) // ANY
+ ASMJIT_INST_0x(wbnoinvd, Wbnoinvd) // WBNOINVD
+ ASMJIT_INST_3x(wrmsr, Wrmsr, EDX, EAX, ECX) // MSR [EXPLICIT] RDX:EAX -> MSR[ECX]
+ ASMJIT_INST_3x(xsetbv, Xsetbv, EDX, EAX, ECX) // XSAVE [EXPLICIT] XCR[ECX] <- EDX:EAX
+
+ //! \}
+
+ //! \name MONITOR Instructions (Privileged)
+ //! \{
+
+ ASMJIT_INST_3x(monitor, Monitor, Mem, Gp, Gp) // MONITOR
+ ASMJIT_INST_2x(mwait, Mwait, Gp, Gp) // MONITOR
+
+ //! \}
+
+ //! \name SMAP Instructions (Privileged)
//! \{
ASMJIT_INST_0x(clac, Clac) // SMAP
@@ -1005,45 +1168,25 @@ public:
//! \}
- //! \name SVM Instructions
+ //! \name SKINIT Instructions (Privileged)
//! \{
- ASMJIT_INST_0x(clgi, Clgi) // SVM
- ASMJIT_INST_2x(invlpga, Invlpga, Gp, Gp) // SVM [EXPLICIT] <eax|rax, ecx>
ASMJIT_INST_1x(skinit, Skinit, Gp) // SKINIT [EXPLICIT] <eax>
ASMJIT_INST_0x(stgi, Stgi) // SKINIT
- ASMJIT_INST_1x(vmload, Vmload, Gp) // SVM [EXPLICIT] <zax>
- ASMJIT_INST_0x(vmmcall, Vmmcall) // SVM
- ASMJIT_INST_1x(vmrun, Vmrun, Gp) // SVM [EXPLICIT] <zax>
- ASMJIT_INST_1x(vmsave, Vmsave, Gp) // SVM [EXPLICIT] <zax>
//! \}
- //! \name TBM Instructions
+ //! \name SNP Instructions (Privileged)
//! \{
- ASMJIT_INST_2x(blcfill, Blcfill, Gp, Gp) // TBM
- ASMJIT_INST_2x(blcfill, Blcfill, Gp, Mem) // TBM
- ASMJIT_INST_2x(blci, Blci, Gp, Gp) // TBM
- ASMJIT_INST_2x(blci, Blci, Gp, Mem) // TBM
- ASMJIT_INST_2x(blcic, Blcic, Gp, Gp) // TBM
- ASMJIT_INST_2x(blcic, Blcic, Gp, Mem) // TBM
- ASMJIT_INST_2x(blcmsk, Blcmsk, Gp, Gp) // TBM
- ASMJIT_INST_2x(blcmsk, Blcmsk, Gp, Mem) // TBM
- ASMJIT_INST_2x(blcs, Blcs, Gp, Gp) // TBM
- ASMJIT_INST_2x(blcs, Blcs, Gp, Mem) // TBM
- ASMJIT_INST_2x(blsfill, Blsfill, Gp, Gp) // TBM
- ASMJIT_INST_2x(blsfill, Blsfill, Gp, Mem) // TBM
- ASMJIT_INST_2x(blsic, Blsic, Gp, Gp) // TBM
- ASMJIT_INST_2x(blsic, Blsic, Gp, Mem) // TBM
- ASMJIT_INST_2x(t1mskc, T1mskc, Gp, Gp) // TBM
- ASMJIT_INST_2x(t1mskc, T1mskc, Gp, Mem) // TBM
- ASMJIT_INST_2x(tzmsk, Tzmsk, Gp, Gp) // TBM
- ASMJIT_INST_2x(tzmsk, Tzmsk, Gp, Mem) // TBM
+ ASMJIT_INST_0x(psmash, Psmash) // SNP
+ ASMJIT_INST_0x(pvalidate, Pvalidate) // SNP
+ ASMJIT_INST_0x(rmpadjust, Rmpadjust) // SNP
+ ASMJIT_INST_0x(rmpupdate, Rmpupdate) // SNP
//! \}
- //! \name VMX Instructions
+ //! \name VMX Instructions (All privileged except vmfunc)
//! \{
ASMJIT_INST_2x(invept, Invept, Gp, Mem) // VMX
@@ -1061,15 +1204,25 @@ public:
//! \}
- //! \name Other GP Instructions
+ //! \name SVM Instructions (All privileged except vmmcall)
//! \{
- ASMJIT_INST_0x(getsec, Getsec) // SMX
- ASMJIT_INST_0x(pcommit, Pcommit) // PCOMMIT
- ASMJIT_INST_1x(rdpid, Rdpid, Gp) // RDPID
+ ASMJIT_INST_0x(clgi, Clgi) // SVM
+ ASMJIT_INST_2x(invlpga, Invlpga, Gp, Gp) // SVM [EXPLICIT] <eax|rax, ecx>
+ ASMJIT_INST_1x(vmload, Vmload, Gp) // SVM [EXPLICIT] <zax>
+ ASMJIT_INST_0x(vmmcall, Vmmcall) // SVM
+ ASMJIT_INST_1x(vmrun, Vmrun, Gp) // SVM [EXPLICIT] <zax>
+ ASMJIT_INST_1x(vmsave, Vmsave, Gp) // SVM [EXPLICIT] <zax>
+
+ //! \}
+
+ //! \name SYSCALL & SYSENTER Instructions
+ //! \{
//! \}
+
+
//! \name FPU Instructions
//! \{
@@ -1295,12 +1448,6 @@ public:
ASMJIT_INST_3i(extractps, Extractps, Mem, Xmm, Imm) // SSE4_1
ASMJIT_INST_2x(extrq, Extrq, Xmm, Xmm) // SSE4A
ASMJIT_INST_3ii(extrq, Extrq, Xmm, Imm, Imm) // SSE4A
- ASMJIT_INST_3i(gf2p8affineinvqb, Gf2p8affineinvqb, Xmm, Xmm, Imm) // GFNI
- ASMJIT_INST_3i(gf2p8affineinvqb, Gf2p8affineinvqb, Xmm, Mem, Imm) // GFNI
- ASMJIT_INST_3i(gf2p8affineqb, Gf2p8affineqb, Xmm, Xmm, Imm) // GFNI
- ASMJIT_INST_3i(gf2p8affineqb, Gf2p8affineqb, Xmm, Mem, Imm) // GFNI
- ASMJIT_INST_2x(gf2p8mulb, Gf2p8mulb, Xmm, Xmm) // GFNI
- ASMJIT_INST_2x(gf2p8mulb, Gf2p8mulb, Xmm, Mem) // GFNI
ASMJIT_INST_2x(haddpd, Haddpd, Xmm, Xmm) // SSE3
ASMJIT_INST_2x(haddpd, Haddpd, Xmm, Mem) // SSE3
ASMJIT_INST_2x(haddps, Haddps, Xmm, Xmm) // SSE3
@@ -1928,6 +2075,13 @@ public:
ASMJIT_INST_2x(pmulhrw, Pmulhrw, Mm, Mem) // 3DNOW
ASMJIT_INST_2x(pswapd, Pswapd, Mm, Mm) // 3DNOW
ASMJIT_INST_2x(pswapd, Pswapd, Mm, Mem) // 3DNOW
+
+ //! \}
+
+ //! \name EMMS/FEMMS Instructions
+ //! \{
+
+ ASMJIT_INST_0x(emms, Emms) // MMX
ASMJIT_INST_0x(femms, Femms) // 3DNOW
//! \}
@@ -1970,6 +2124,18 @@ public:
//! \}
+ //! \name GFNI Instructions
+ //! \{
+
+ ASMJIT_INST_3i(gf2p8affineinvqb, Gf2p8affineinvqb, Xmm, Xmm, Imm) // GFNI
+ ASMJIT_INST_3i(gf2p8affineinvqb, Gf2p8affineinvqb, Xmm, Mem, Imm) // GFNI
+ ASMJIT_INST_3i(gf2p8affineqb, Gf2p8affineqb, Xmm, Xmm, Imm) // GFNI
+ ASMJIT_INST_3i(gf2p8affineqb, Gf2p8affineqb, Xmm, Mem, Imm) // GFNI
+ ASMJIT_INST_2x(gf2p8mulb, Gf2p8mulb, Xmm, Xmm) // GFNI
+ ASMJIT_INST_2x(gf2p8mulb, Gf2p8mulb, Xmm, Mem) // GFNI
+
+ //! \}
+
//! \name AVX, FMA, and AVX512 Instructions
//! \{
@@ -2592,8 +2758,12 @@ public:
ASMJIT_INST_3x(vorpd, Vorpd, Vec, Vec, Mem) // AVX AVX512_DQ{kz|b64}
ASMJIT_INST_3x(vorps, Vorps, Vec, Vec, Vec) // AVX AVX512_F{kz|b32}
ASMJIT_INST_3x(vorps, Vorps, Vec, Vec, Mem) // AVX AVX512_F{kz|b32}
- ASMJIT_INST_6x(vp4dpwssd, Vp4dpwssd, Zmm, Zmm, Zmm, Zmm, Zmm, Mem) // AVX512_4FMAPS{kz}
- ASMJIT_INST_6x(vp4dpwssds, Vp4dpwssds, Zmm, Zmm, Zmm, Zmm, Zmm, Mem) // AVX512_4FMAPS{kz}
+ ASMJIT_INST_4x(vp2intersectd, Vp2intersectd, KReg, KReg, Vec, Vec) // AVX512_VP2INTERSECT{kz}
+ ASMJIT_INST_4x(vp2intersectd, Vp2intersectd, KReg, KReg, Vec, Mem) // AVX512_VP2INTERSECT{kz}
+ ASMJIT_INST_4x(vp2intersectq, Vp2intersectq, KReg, KReg, Vec, Vec) // AVX512_VP2INTERSECT{kz}
+ ASMJIT_INST_4x(vp2intersectq, Vp2intersectq, KReg, KReg, Vec, Mem) // AVX512_VP2INTERSECT{kz}
+ ASMJIT_INST_6x(vp4dpwssd, Vp4dpwssd, Zmm, Zmm, Zmm, Zmm, Zmm, Mem) // AVX512_4FMAPS{kz}
+ ASMJIT_INST_6x(vp4dpwssds, Vp4dpwssds, Zmm, Zmm, Zmm, Zmm, Zmm, Mem) // AVX512_4FMAPS{kz}
ASMJIT_INST_2x(vpabsb, Vpabsb, Vec, Vec) // AVX+ AVX512_BW{kz}
ASMJIT_INST_2x(vpabsb, Vpabsb, Vec, Mem) // AVX+ AVX512_BW{kz}
ASMJIT_INST_2x(vpabsd, Vpabsd, Vec, Vec) // AVX+ AVX512_F{kz}
@@ -3512,6 +3682,25 @@ public:
ASMJIT_INST_3x(vpshlw, Vpshlw, Xmm, Xmm, Mem) // XOP
//! \}
+
+ //! \name AMX Instructions
+ //! \{
+
+ ASMJIT_INST_1x(ldtilecfg, Ldtilecfg, Mem) // AMX_TILE
+ ASMJIT_INST_1x(sttilecfg, Sttilecfg, Mem) // AMX_TILE
+ ASMJIT_INST_2x(tileloadd, Tileloadd, Tmm, Mem) // AMX_TILE
+ ASMJIT_INST_2x(tileloaddt1, Tileloaddt1, Tmm, Mem) // AMX_TILE
+ ASMJIT_INST_0x(tilerelease, Tilerelease) // AMX_TILE
+ ASMJIT_INST_2x(tilestored, Tilestored, Mem, Tmm) // AMX_TILE
+ ASMJIT_INST_1x(tilezero, Tilezero, Tmm) // AMX_TILE
+
+ ASMJIT_INST_3x(tdpbf16ps, Tdpbf16ps, Tmm, Tmm, Tmm) // AMX_BF16
+ ASMJIT_INST_3x(tdpbssd, Tdpbssd, Tmm, Tmm, Tmm) // AMX_INT8
+ ASMJIT_INST_3x(tdpbsud, Tdpbsud, Tmm, Tmm, Tmm) // AMX_INT8
+ ASMJIT_INST_3x(tdpbusd, Tdpbusd, Tmm, Tmm, Tmm) // AMX_INT8
+ ASMJIT_INST_3x(tdpbuud, Tdpbuud, Tmm, Tmm, Tmm) // AMX_INT8
+
+ //! \}
};
// ============================================================================
@@ -3520,6 +3709,10 @@ public:
template<typename This>
struct EmitterImplicitT : public EmitterExplicitT<This> {
+ //! \cond
+ using EmitterExplicitT<This>::_emitter;
+ //! \endcond
+
//! \name Prefix Options
//! \{
@@ -3537,17 +3730,13 @@ struct EmitterImplicitT : public EmitterExplicitT<This> {
//! \}
- //! \name Base Instructions & GP Extensions
+ //! \name Core Instructions
//! \{
//! \cond
- using EmitterExplicitT<This>::_emitter;
-
- // TODO: xrstor and xsave don't have explicit variants yet.
using EmitterExplicitT<This>::cbw;
using EmitterExplicitT<This>::cdq;
using EmitterExplicitT<This>::cdqe;
- using EmitterExplicitT<This>::clzero;
using EmitterExplicitT<This>::cqo;
using EmitterExplicitT<This>::cwd;
using EmitterExplicitT<This>::cwde;
@@ -3555,23 +3744,14 @@ struct EmitterImplicitT : public EmitterExplicitT<This> {
using EmitterExplicitT<This>::cmpxchg;
using EmitterExplicitT<This>::cmpxchg8b;
using EmitterExplicitT<This>::cmpxchg16b;
- using EmitterExplicitT<This>::cpuid;
using EmitterExplicitT<This>::div;
using EmitterExplicitT<This>::idiv;
using EmitterExplicitT<This>::imul;
using EmitterExplicitT<This>::jecxz;
- using EmitterExplicitT<This>::lahf;
- using EmitterExplicitT<This>::mulx;
- using EmitterExplicitT<This>::movsd;
+ using EmitterExplicitT<This>::loop;
+ using EmitterExplicitT<This>::loope;
+ using EmitterExplicitT<This>::loopne;
using EmitterExplicitT<This>::mul;
- using EmitterExplicitT<This>::rdmsr;
- using EmitterExplicitT<This>::rdpmc;
- using EmitterExplicitT<This>::rdtsc;
- using EmitterExplicitT<This>::rdtscp;
- using EmitterExplicitT<This>::sahf;
- using EmitterExplicitT<This>::wrmsr;
- using EmitterExplicitT<This>::xgetbv;
- using EmitterExplicitT<This>::xsetbv;
//! \endcond
ASMJIT_INST_0x(cbw, Cbw) // ANY [IMPLICIT] AX <- Sign Extend AL
@@ -3581,12 +3761,9 @@ struct EmitterImplicitT : public EmitterExplicitT<This> {
ASMJIT_INST_2x(cmpxchg, Cmpxchg, Mem, Gp) // I486 [IMPLICIT]
ASMJIT_INST_1x(cmpxchg16b, Cmpxchg16b, Mem) // CMPXCHG8B [IMPLICIT] m == RDX:RAX ? m <- RCX:RBX
ASMJIT_INST_1x(cmpxchg8b, Cmpxchg8b, Mem) // CMPXCHG16B[IMPLICIT] m == EDX:EAX ? m <- ECX:EBX
- ASMJIT_INST_0x(cpuid, Cpuid) // I486 [IMPLICIT] EAX:EBX:ECX:EDX <- CPUID[EAX:ECX]
ASMJIT_INST_0x(cqo, Cqo) // X64 [IMPLICIT] RDX:RAX <- Sign Extend RAX
ASMJIT_INST_0x(cwd, Cwd) // ANY [IMPLICIT] DX:AX <- Sign Extend AX
ASMJIT_INST_0x(cwde, Cwde) // ANY [IMPLICIT] EAX <- Sign Extend AX
- ASMJIT_INST_0x(daa, Daa)
- ASMJIT_INST_0x(das, Das)
ASMJIT_INST_1x(div, Div, Gp) // ANY [IMPLICIT] {AH[Rem]: AL[Quot] <- AX / r8} {xDX[Rem]:xAX[Quot] <- DX:AX / r16|r32|r64}
ASMJIT_INST_1x(div, Div, Mem) // ANY [IMPLICIT] {AH[Rem]: AL[Quot] <- AX / m8} {xDX[Rem]:xAX[Quot] <- DX:AX / m16|m32|m64}
ASMJIT_INST_1x(idiv, Idiv, Gp) // ANY [IMPLICIT] {AH[Rem]: AL[Quot] <- AX / r8} {xDX[Rem]:xAX[Quot] <- DX:AX / r16|r32|r64}
@@ -3600,7 +3777,6 @@ struct EmitterImplicitT : public EmitterExplicitT<This> {
ASMJIT_INST_1x(jecxz, Jecxz, Label) // ANY [IMPLICIT] Short jump if CX/ECX/RCX is zero.
ASMJIT_INST_1x(jecxz, Jecxz, Imm) // ANY [IMPLICIT] Short jump if CX/ECX/RCX is zero.
ASMJIT_INST_1x(jecxz, Jecxz, uint64_t) // ANY [IMPLICIT] Short jump if CX/ECX/RCX is zero.
- ASMJIT_INST_0x(lahf, Lahf) // LAHFSAHF [IMPLICIT] AH <- EFL
ASMJIT_INST_1x(loop, Loop, Label) // ANY [IMPLICIT] Decrement xCX; short jump if xCX != 0.
ASMJIT_INST_1x(loop, Loop, Imm) // ANY [IMPLICIT] Decrement xCX; short jump if xCX != 0.
ASMJIT_INST_1x(loop, Loop, uint64_t) // ANY [IMPLICIT] Decrement xCX; short jump if xCX != 0.
@@ -3612,20 +3788,8 @@ struct EmitterImplicitT : public EmitterExplicitT<This> {
ASMJIT_INST_1x(loopne, Loopne, uint64_t) // ANY [IMPLICIT] Decrement xCX; short jump if xCX != 0 && ZF == 0.
ASMJIT_INST_1x(mul, Mul, Gp) // ANY [IMPLICIT] {AX <- AL * r8} {xDX:xAX <- xAX * r16|r32|r64}
ASMJIT_INST_1x(mul, Mul, Mem) // ANY [IMPLICIT] {AX <- AL * m8} {xDX:xAX <- xAX * m16|m32|m64}
- ASMJIT_INST_0x(rdmsr, Rdmsr) // ANY [IMPLICIT]
- ASMJIT_INST_0x(rdpmc, Rdpmc) // ANY [IMPLICIT]
- ASMJIT_INST_0x(rdtsc, Rdtsc) // RDTSC [IMPLICIT] EDX:EAX <- CNT
- ASMJIT_INST_0x(rdtscp, Rdtscp) // RDTSCP [IMPLICIT] EDX:EAX:EXC <- CNT
ASMJIT_INST_0x(ret, Ret)
ASMJIT_INST_1i(ret, Ret, Imm)
- ASMJIT_INST_0x(sahf, Sahf) // LAHFSAHF [IMPLICIT] EFL <- AH
- ASMJIT_INST_0x(syscall, Syscall) // X64 [IMPLICIT]
- ASMJIT_INST_0x(sysenter, Sysenter) // X64 [IMPLICIT]
- ASMJIT_INST_0x(sysexit, Sysexit) // X64 [IMPLICIT]
- ASMJIT_INST_0x(sysexit64, Sysexit64) // X64 [IMPLICIT]
- ASMJIT_INST_0x(sysret, Sysret) // X64 [IMPLICIT]
- ASMJIT_INST_0x(sysret64, Sysret64) // X64 [IMPLICIT]
- ASMJIT_INST_0x(wrmsr, Wrmsr) // ANY [IMPLICIT]
ASMJIT_INST_0x(xlatb, Xlatb) // ANY [IMPLICIT]
//! \}
@@ -3633,6 +3797,10 @@ struct EmitterImplicitT : public EmitterExplicitT<This> {
//! \name String Instruction Aliases
//! \{
+ //! \cond
+ using EmitterExplicitT<This>::movsd;
+ //! \endcond
+
inline Error cmpsb() { return _emitter()->emit(Inst::kIdCmps, EmitterExplicitT<This>::ptr_zsi(0, 1), EmitterExplicitT<This>::ptr_zdi(0, 1)); }
inline Error cmpsd() { return _emitter()->emit(Inst::kIdCmps, EmitterExplicitT<This>::ptr_zsi(0, 4), EmitterExplicitT<This>::ptr_zdi(0, 4)); }
inline Error cmpsq() { return _emitter()->emit(Inst::kIdCmps, EmitterExplicitT<This>::ptr_zsi(0, 8), EmitterExplicitT<This>::ptr_zdi(0, 8)); }
@@ -3660,24 +3828,106 @@ struct EmitterImplicitT : public EmitterExplicitT<This> {
//! \}
- //! \name CL Instructions
+ //! \name Deprecated 32-bit Instructions
//! \{
+ //! \cond
+ using EmitterExplicitT<This>::aaa;
+ using EmitterExplicitT<This>::aad;
+ using EmitterExplicitT<This>::aam;
+ using EmitterExplicitT<This>::aas;
+ using EmitterExplicitT<This>::daa;
+ using EmitterExplicitT<This>::das;
+ //! \endcond
+
+ ASMJIT_INST_0x(aaa, Aaa) // X86 [IMPLICIT]
+ ASMJIT_INST_1i(aad, Aad, Imm) // X86 [IMPLICIT]
+ ASMJIT_INST_1i(aam, Aam, Imm) // X86 [IMPLICIT]
+ ASMJIT_INST_0x(aas, Aas) // X86 [IMPLICIT]
+ ASMJIT_INST_0x(daa, Daa) // X86 [IMPLICIT]
+ ASMJIT_INST_0x(das, Das) // X86 [IMPLICIT]
+
+ //! \}
+
+ //! \name LAHF/SAHF Instructions
+ //! \{
+
+ //! \cond
+ using EmitterExplicitT<This>::lahf;
+ using EmitterExplicitT<This>::sahf;
+ //! \endcond
+
+ ASMJIT_INST_0x(lahf, Lahf) // LAHFSAHF [IMPLICIT] AH <- EFL
+ ASMJIT_INST_0x(sahf, Sahf) // LAHFSAHF [IMPLICIT] EFL <- AH
+
+ //! \}
+
+ //! \name CPUID Instruction
+
+ //! \cond
+ using EmitterExplicitT<This>::cpuid;
+ //! \endcond
+
+ ASMJIT_INST_0x(cpuid, Cpuid) // I486 [IMPLICIT] EAX:EBX:ECX:EDX <- CPUID[EAX:ECX]
+
+ //! \}
+
+ //! \name CacheLine Instructions
+ //! \{
+
+ //! \cond
+ using EmitterExplicitT<This>::clzero;
+ //! \endcond
+
ASMJIT_INST_0x(clzero, Clzero) // CLZERO [IMPLICIT]
//! \}
+ //! \name RDPRU Instruction
+ //! \{
+
+ //! \cond
+ using EmitterExplicitT<This>::rdpru;
+ //! \endcond
+
+ ASMJIT_INST_0x(rdpru, Rdpru) // RDPRU [IMPLICIT] EDX:EAX <- PRU[ECX]
+
+ //! \}
+
+ //! \name RDTSC/RDTSCP Instructions
+ //! \{
+
+ //! \cond
+ using EmitterExplicitT<This>::rdtsc;
+ using EmitterExplicitT<This>::rdtscp;
+ //! \endcond
+
+ ASMJIT_INST_0x(rdtsc, Rdtsc) // RDTSC [IMPLICIT] EDX:EAX <- CNT
+ ASMJIT_INST_0x(rdtscp, Rdtscp) // RDTSCP [IMPLICIT] EDX:EAX:EXC <- CNT
+
+ //! \}
+
//! \name BMI2 Instructions
//! \{
+ //! \cond
+ using EmitterExplicitT<This>::mulx;
+ //! \endcond
+
ASMJIT_INST_3x(mulx, Mulx, Gp, Gp, Gp) // BMI2 [IMPLICIT]
ASMJIT_INST_3x(mulx, Mulx, Gp, Gp, Mem) // BMI2 [IMPLICIT]
//! \}
- //! \name FXSR & XSAVE Instructions
+ //! \name XSAVE Instructions
//! \{
+ // TODO: xrstor and xsave don't have explicit variants yet.
+
+ //! \cond
+ using EmitterExplicitT<This>::xgetbv;
+ //! \endcond
+
ASMJIT_INST_0x(xgetbv, Xgetbv) // XSAVE [IMPLICIT] EDX:EAX <- XCR[ECX]
ASMJIT_INST_1x(xrstor, Xrstor, Mem) // XSAVE [IMPLICIT]
ASMJIT_INST_1x(xrstor64, Xrstor64, Mem) // XSAVE+X64 [IMPLICIT]
@@ -3691,6 +3941,35 @@ struct EmitterImplicitT : public EmitterExplicitT<This> {
ASMJIT_INST_1x(xsaveopt64, Xsaveopt64, Mem) // XSAVE+X64 [IMPLICIT]
ASMJIT_INST_1x(xsaves, Xsaves, Mem) // XSAVE [IMPLICIT]
ASMJIT_INST_1x(xsaves64, Xsaves64, Mem) // XSAVE+X64 [IMPLICIT]
+
+ //! \}
+
+ //! \name SYSCALL/SYSENTER Instructions
+ //! \{
+
+ ASMJIT_INST_0x(syscall, Syscall) // X64 [IMPLICIT]
+ ASMJIT_INST_0x(sysenter, Sysenter) // X64 [IMPLICIT]
+
+ //! \}
+
+ //! \name Privileged Instructions
+ //! \{
+
+ //! \cond
+ using EmitterExplicitT<This>::rdmsr;
+ using EmitterExplicitT<This>::rdpmc;
+ using EmitterExplicitT<This>::wrmsr;
+ using EmitterExplicitT<This>::xsetbv;
+ //! \endcond
+
+ ASMJIT_INST_0x(pconfig, Pconfig) // PCONFIG [IMPLICIT]
+ ASMJIT_INST_0x(rdmsr, Rdmsr) // ANY [IMPLICIT]
+ ASMJIT_INST_0x(rdpmc, Rdpmc) // ANY [IMPLICIT]
+ ASMJIT_INST_0x(sysexit, Sysexit) // X64 [IMPLICIT]
+ ASMJIT_INST_0x(sysexit64, Sysexit64) // X64 [IMPLICIT]
+ ASMJIT_INST_0x(sysret, Sysret) // X64 [IMPLICIT]
+ ASMJIT_INST_0x(sysret64, Sysret64) // X64 [IMPLICIT]
+ ASMJIT_INST_0x(wrmsr, Wrmsr) // ANY [IMPLICIT]
ASMJIT_INST_0x(xsetbv, Xsetbv) // XSAVE [IMPLICIT] XCR[ECX] <- EDX:EAX
//! \}
@@ -3698,6 +3977,13 @@ struct EmitterImplicitT : public EmitterExplicitT<This> {
//! \name Monitor & MWait Instructions
//! \{
+ //! \cond
+ using EmitterExplicitT<This>::monitor;
+ using EmitterExplicitT<This>::monitorx;
+ using EmitterExplicitT<This>::mwait;
+ using EmitterExplicitT<This>::mwaitx;
+ //! \endcond
+
ASMJIT_INST_0x(monitor, Monitor)
ASMJIT_INST_0x(monitorx, Monitorx)
ASMJIT_INST_0x(mwait, Mwait)
@@ -3705,6 +3991,19 @@ struct EmitterImplicitT : public EmitterExplicitT<This> {
//! \}
+ //! \name WAITPKG Instructions
+ //! \{
+
+ //! \cond
+ using EmitterExplicitT<This>::tpause;
+ using EmitterExplicitT<This>::umwait;
+ //! \endcond
+
+ ASMJIT_INST_1x(tpause, Tpause, Gp)
+ ASMJIT_INST_1x(umwait, Umwait, Gp)
+
+ //! \}
+
//! \name MMX & SSE Instructions
//! \{
@@ -3742,7 +4041,9 @@ struct EmitterImplicitT : public EmitterExplicitT<This> {
//! \name SHA Instructions
//! \{
+ //! \cond
using EmitterExplicitT<This>::sha256rnds2;
+ //! \endcond
ASMJIT_INST_2x(sha256rnds2, Sha256rnds2, Xmm, Xmm) // SHA [IMPLICIT]
ASMJIT_INST_2x(sha256rnds2, Sha256rnds2, Xmm, Mem) // SHA [IMPLICIT]
@@ -3752,21 +4053,23 @@ struct EmitterImplicitT : public EmitterExplicitT<This> {
//! \name AVX, FMA, and AVX512 Instructions
//! \{
+ //! \cond
using EmitterExplicitT<This>::vmaskmovdqu;
using EmitterExplicitT<This>::vpcmpestri;
using EmitterExplicitT<This>::vpcmpestrm;
using EmitterExplicitT<This>::vpcmpistri;
using EmitterExplicitT<This>::vpcmpistrm;
+ //! \endcond
- ASMJIT_INST_2x(vmaskmovdqu, Vmaskmovdqu, Xmm, Xmm) // AVX [IMPLICIT]
- ASMJIT_INST_3i(vpcmpestri, Vpcmpestri, Xmm, Xmm, Imm) // AVX [IMPLICIT]
- ASMJIT_INST_3i(vpcmpestri, Vpcmpestri, Xmm, Mem, Imm) // AVX [IMPLICIT]
- ASMJIT_INST_3i(vpcmpestrm, Vpcmpestrm, Xmm, Xmm, Imm) // AVX [IMPLICIT]
- ASMJIT_INST_3i(vpcmpestrm, Vpcmpestrm, Xmm, Mem, Imm) // AVX [IMPLICIT]
- ASMJIT_INST_3i(vpcmpistri, Vpcmpistri, Xmm, Xmm, Imm) // AVX [IMPLICIT]
- ASMJIT_INST_3i(vpcmpistri, Vpcmpistri, Xmm, Mem, Imm) // AVX [IMPLICIT]
- ASMJIT_INST_3i(vpcmpistrm, Vpcmpistrm, Xmm, Xmm, Imm) // AVX [IMPLICIT]
- ASMJIT_INST_3i(vpcmpistrm, Vpcmpistrm, Xmm, Mem, Imm) // AVX [IMPLICIT]
+ ASMJIT_INST_2x(vmaskmovdqu, Vmaskmovdqu, Xmm, Xmm) // AVX [IMPLICIT]
+ ASMJIT_INST_3i(vpcmpestri, Vpcmpestri, Xmm, Xmm, Imm) // AVX [IMPLICIT]
+ ASMJIT_INST_3i(vpcmpestri, Vpcmpestri, Xmm, Mem, Imm) // AVX [IMPLICIT]
+ ASMJIT_INST_3i(vpcmpestrm, Vpcmpestrm, Xmm, Xmm, Imm) // AVX [IMPLICIT]
+ ASMJIT_INST_3i(vpcmpestrm, Vpcmpestrm, Xmm, Mem, Imm) // AVX [IMPLICIT]
+ ASMJIT_INST_3i(vpcmpistri, Vpcmpistri, Xmm, Xmm, Imm) // AVX [IMPLICIT]
+ ASMJIT_INST_3i(vpcmpistri, Vpcmpistri, Xmm, Mem, Imm) // AVX [IMPLICIT]
+ ASMJIT_INST_3i(vpcmpistrm, Vpcmpistrm, Xmm, Xmm, Imm) // AVX [IMPLICIT]
+ ASMJIT_INST_3i(vpcmpistrm, Vpcmpistrm, Xmm, Mem, Imm) // AVX [IMPLICIT]
//! \}
};
diff --git a/src/asmjit/x86/x86features.cpp b/src/asmjit/x86/x86features.cpp
index 7c9505d..99f2444 100644
--- a/src/asmjit/x86/x86features.cpp
+++ b/src/asmjit/x86/x86features.cpp
@@ -259,7 +259,12 @@ ASMJIT_FAVOR_SIZE void detectCpu(CpuInfo& cpu) noexcept {
if (bitTest(regs.ecx, 27)) features.add(Features::kMOVDIRI);
if (bitTest(regs.ecx, 28)) features.add(Features::kMOVDIR64B);
if (bitTest(regs.ecx, 29)) features.add(Features::kENQCMD);
+ if (bitTest(regs.edx, 14)) features.add(Features::kSERIALIZE);
+ if (bitTest(regs.edx, 16)) features.add(Features::kTSXLDTRK);
if (bitTest(regs.edx, 18)) features.add(Features::kPCONFIG);
+ if (bitTest(regs.edx, 22)) features.add(Features::kAMX_BF16);
+ if (bitTest(regs.edx, 24)) features.add(Features::kAMX_TILE);
+ if (bitTest(regs.edx, 25)) features.add(Features::kAMX_INT8);
// Detect 'TSX' - Requires at least one of `HLE` and `RTM` features.
if (features.hasHLE() || features.hasRTM())
@@ -330,7 +335,7 @@ ASMJIT_FAVOR_SIZE void detectCpu(CpuInfo& cpu) noexcept {
uint32_t i = maxId;
// The highest EAX that we understand.
- uint32_t kHighestProcessedEAX = 0x80000008u;
+ uint32_t kHighestProcessedEAX = 0x8000001Fu;
// Several CPUID calls are required to get the whole branc string. It's easy
// to copy one DWORD at a time instead of performing a byte copy.
@@ -357,8 +362,9 @@ ASMJIT_FAVOR_SIZE void detectCpu(CpuInfo& cpu) noexcept {
if (bitTest(regs.edx, 21)) features.add(Features::kFXSROPT);
if (bitTest(regs.edx, 22)) features.add(Features::kMMX2);
if (bitTest(regs.edx, 27)) features.add(Features::kRDTSCP);
+ if (bitTest(regs.edx, 29)) features.add(Features::kPREFETCHW);
if (bitTest(regs.edx, 30)) features.add(Features::k3DNOW2, Features::kMMX2);
- if (bitTest(regs.edx, 31)) features.add(Features::k3DNOW);
+ if (bitTest(regs.edx, 31)) features.add(Features::kPREFETCHW);
if (cpu.hasFeature(Features::kAVX)) {
if (bitTest(regs.ecx, 11)) features.add(Features::kXOP);
@@ -379,12 +385,22 @@ ASMJIT_FAVOR_SIZE void detectCpu(CpuInfo& cpu) noexcept {
*brand++ = regs.ecx;
*brand++ = regs.edx;
- // Go directly to the last one.
+ // Go directly to the next one we are interested in.
if (i == 0x80000004u) i = 0x80000008u - 1;
break;
case 0x80000008u:
if (bitTest(regs.ebx, 0)) features.add(Features::kCLZERO);
+ if (bitTest(regs.ebx, 0)) features.add(Features::kRDPRU);
+ if (bitTest(regs.ebx, 8)) features.add(Features::kMCOMMIT);
+ if (bitTest(regs.ebx, 9)) features.add(Features::kWBNOINVD);
+
+ // Go directly to the next one we are interested in.
+ i = 0x8000001Fu - 1;
+ break;
+
+ case 0x8000001Fu:
+ if (bitTest(regs.eax, 4)) features.add(Features::kSNP);
break;
}
} while (++i <= maxId);
diff --git a/src/asmjit/x86/x86features.h b/src/asmjit/x86/x86features.h
index b26b524..e8de8d8 100644
--- a/src/asmjit/x86/x86features.h
+++ b/src/asmjit/x86/x86features.h
@@ -52,6 +52,9 @@ public:
kADX, //!< CPU has ADX (multi-precision add-carry instruction extensions).
kAESNI, //!< CPU has AESNI (AES encode/decode instructions).
kALTMOVCR8, //!< CPU has LOCK MOV R<->CR0 (supports `MOV R<->CR8` via `LOCK MOV R<->CR0` in 32-bit mode) [AMD].
+ kAMX_BF16, //!< CPU has AMX_BF16 (advanced matrix extensions - BF16 instructions).
+ kAMX_INT8, //!< CPU has AMX_INT8 (advanced matrix extensions - INT8 instructions).
+ kAMX_TILE, //!< CPU has AMX_TILE (advanced matrix extensions).
kAVX, //!< CPU has AVX (advanced vector extensions).
kAVX2, //!< CPU has AVX2 (advanced vector extensions 2).
kAVX512_4FMAPS, //!< CPU has AVX512_FMAPS (FMA packed single).
@@ -98,6 +101,7 @@ public:
kLAHFSAHF, //!< CPU has LAHF/SAHF (LAHF/SAHF in 64-bit mode) [X86_64].
kLWP, //!< CPU has LWP (lightweight profiling) [AMD].
kLZCNT, //!< CPU has LZCNT (LZCNT instruction).
+ kMCOMMIT, //!< CPU has MCOMMIT (MCOMMIT instruction).
kMMX, //!< CPU has MMX (MMX base instructions).
kMMX2, //!< CPU has MMX2 (MMX extensions or MMX2).
kMONITOR, //!< CPU has MONITOR (MONITOR/MWAIT instructions).
@@ -116,16 +120,19 @@ public:
kPREFETCHW, //!< CPU has PREFETCHW.
kPREFETCHWT1, //!< CPU has PREFETCHWT1.
kRDPID, //!< CPU has RDPID.
+ kRDPRU, //!< CPU has RDPRU.
kRDRAND, //!< CPU has RDRAND.
kRDSEED, //!< CPU has RDSEED.
kRDTSC, //!< CPU has RDTSC.
kRDTSCP, //!< CPU has RDTSCP.
kRTM, //!< CPU has RTM.
+ kSERIALIZE, //!< CPU has SERIALIZE.
kSHA, //!< CPU has SHA (SHA-1 and SHA-256 instructions).
kSKINIT, //!< CPU has SKINIT (SKINIT/STGI instructions) [AMD].
kSMAP, //!< CPU has SMAP (supervisor-mode access prevention).
kSMEP, //!< CPU has SMEP (supervisor-mode execution prevention).
kSMX, //!< CPU has SMX (safer mode extensions).
+ kSNP, //!< CPU has SNP.
kSSE, //!< CPU has SSE.
kSSE2, //!< CPU has SSE2.
kSSE3, //!< CPU has SSE3.
@@ -136,6 +143,7 @@ public:
kSVM, //!< CPU has SVM (virtualization) [AMD].
kTBM, //!< CPU has TBM (trailing bit manipulation) [AMD].
kTSX, //!< CPU has TSX.
+ kTSXLDTRK, //!< CPU has TSXLDTRK.
kVAES, //!< CPU has VAES (vector AES 256|512 bit support).
kVMX, //!< CPU has VMX (virtualization) [INTEL].
kVPCLMULQDQ, //!< CPU has VPCLMULQDQ (vector PCLMULQDQ 256|512-bit support).
@@ -183,6 +191,9 @@ public:
ASMJIT_X86_FEATURE(ADX)
ASMJIT_X86_FEATURE(AESNI)
ASMJIT_X86_FEATURE(ALTMOVCR8)
+ ASMJIT_X86_FEATURE(AMX_BF16)
+ ASMJIT_X86_FEATURE(AMX_INT8)
+ ASMJIT_X86_FEATURE(AMX_TILE)
ASMJIT_X86_FEATURE(AVX)
ASMJIT_X86_FEATURE(AVX2)
ASMJIT_X86_FEATURE(AVX512_4FMAPS)
@@ -229,6 +240,7 @@ public:
ASMJIT_X86_FEATURE(LAHFSAHF)
ASMJIT_X86_FEATURE(LWP)
ASMJIT_X86_FEATURE(LZCNT)
+ ASMJIT_X86_FEATURE(MCOMMIT)
ASMJIT_X86_FEATURE(MMX)
ASMJIT_X86_FEATURE(MMX2)
ASMJIT_X86_FEATURE(MONITOR)
@@ -247,16 +259,19 @@ public:
ASMJIT_X86_FEATURE(PREFETCHW)
ASMJIT_X86_FEATURE(PREFETCHWT1)
ASMJIT_X86_FEATURE(RDPID)
+ ASMJIT_X86_FEATURE(RDPRU)
ASMJIT_X86_FEATURE(RDRAND)
ASMJIT_X86_FEATURE(RDSEED)
ASMJIT_X86_FEATURE(RDTSC)
ASMJIT_X86_FEATURE(RDTSCP)
ASMJIT_X86_FEATURE(RTM)
+ ASMJIT_X86_FEATURE(SERIALIZE)
ASMJIT_X86_FEATURE(SHA)
ASMJIT_X86_FEATURE(SKINIT)
ASMJIT_X86_FEATURE(SMAP)
ASMJIT_X86_FEATURE(SMEP)
ASMJIT_X86_FEATURE(SMX)
+ ASMJIT_X86_FEATURE(SNP)
ASMJIT_X86_FEATURE(SSE)
ASMJIT_X86_FEATURE(SSE2)
ASMJIT_X86_FEATURE(SSE3)
@@ -267,6 +282,7 @@ public:
ASMJIT_X86_FEATURE(SVM)
ASMJIT_X86_FEATURE(TBM)
ASMJIT_X86_FEATURE(TSX)
+ ASMJIT_X86_FEATURE(TSXLDTRK)
ASMJIT_X86_FEATURE(XSAVE)
ASMJIT_X86_FEATURE(XSAVEC)
ASMJIT_X86_FEATURE(XSAVEOPT)
diff --git a/src/asmjit/x86/x86formatter.cpp b/src/asmjit/x86/x86formatter.cpp
index 06553e4..a14d341 100644
--- a/src/asmjit/x86/x86formatter.cpp
+++ b/src/asmjit/x86/x86formatter.cpp
@@ -78,6 +78,7 @@ struct RegFormatInfo_T {
X == Reg::kTypeDReg ? 62 :
X == Reg::kTypeSt ? 47 :
X == Reg::kTypeBnd ? 55 :
+ X == Reg::kTypeTmm ? 65 :
X == Reg::kTypeRip ? 39 : 0,
kFormatIndex = X == Reg::kTypeGpbLo ? 1 :
@@ -95,6 +96,7 @@ struct RegFormatInfo_T {
X == Reg::kTypeDReg ? 80 :
X == Reg::kTypeSt ? 55 :
X == Reg::kTypeBnd ? 69 :
+ X == Reg::kTypeTmm ? 89 :
X == Reg::kTypeRip ? 43 : 0,
kSpecialIndex = X == Reg::kTypeGpbLo ? 96 :
@@ -146,7 +148,9 @@ static const RegFormatInfo x86RegFormatInfo = {
"k\0" // #53
"bnd\0" // #55
"cr\0" // #59
- "dr\0", // #62
+ "dr\0" // #62
+ "tmm\0" // #65
+ ,
// Register name entries and strings.
{ ASMJIT_LOOKUP_TABLE_32(ASMJIT_REG_NAME_ENTRY, 0) },
@@ -170,7 +174,8 @@ static const RegFormatInfo x86RegFormatInfo = {
"dr%u\0" // #80
"rip\0" // #85
- "\0\0\0\0\0\0\0" // #89
+ "tmm%u\0" // #89
+ "\0" // #95
"al\0\0" "cl\0\0" "dl\0\0" "bl\0\0" "spl\0" "bpl\0" "sil\0" "dil\0" // #96
"ah\0\0" "ch\0\0" "dh\0\0" "bh\0\0" "n/a\0" "n/a\0" "n/a\0" "n/a\0" // #128
@@ -211,6 +216,9 @@ Error FormatterInternal::formatFeature(String& sb, uint32_t featureId) noexcept
"ADX\0"
"AESNI\0"
"ALTMOVCR8\0"
+ "AMX_BF16\0"
+ "AMX_INT8\0"
+ "AMX_TILE\0"
"AVX\0"
"AVX2\0"
"AVX512_4FMAPS\0"
@@ -257,6 +265,7 @@ Error FormatterInternal::formatFeature(String& sb, uint32_t featureId) noexcept
"LAHFSAHF\0"
"LWP\0"
"LZCNT\0"
+ "MCOMMIT\0"
"MMX\0"
"MMX2\0"
"MONITOR\0"
@@ -275,16 +284,19 @@ Error FormatterInternal::formatFeature(String& sb, uint32_t featureId) noexcept
"PREFETCHW\0"
"PREFETCHWT1\0"
"RDPID\0"
+ "RDPRU\0"
"RDRAND\0"
"RDSEED\0"
"RDTSC\0"
"RDTSCP\0"
"RTM\0"
+ "SERIALIZE\0"
"SHA\0"
"SKINIT\0"
"SMAP\0"
"SMEP\0"
"SMX\0"
+ "SNP\0"
"SSE\0"
"SSE2\0"
"SSE3\0"
@@ -295,6 +307,7 @@ Error FormatterInternal::formatFeature(String& sb, uint32_t featureId) noexcept
"SVM\0"
"TBM\0"
"TSX\0"
+ "TSXLDTRK\0"
"VAES\0"
"VMX\0"
"VPCLMULQDQ\0"
@@ -308,13 +321,14 @@ Error FormatterInternal::formatFeature(String& sb, uint32_t featureId) noexcept
"<Unknown>\0";
static const uint16_t sFeatureIndex[] = {
- 0, 5, 8, 11, 17, 24, 28, 34, 44, 48, 53, 67, 81, 93, 107, 117, 128, 138,
- 149, 158, 170, 181, 193, 206, 216, 228, 248, 265, 269, 274, 283, 291, 302,
- 307, 314, 319, 330, 340, 346, 353, 358, 363, 367, 372, 376, 385, 390, 398,
- 404, 409, 413, 418, 427, 431, 437, 441, 446, 454, 463, 469, 479, 487, 491,
- 495, 500, 508, 518, 526, 534, 541, 551, 563, 569, 576, 583, 589, 596, 600,
- 604, 611, 616, 621, 625, 629, 634, 639, 646, 653, 659, 665, 669, 673, 677,
- 682, 686, 697, 705, 714, 718, 724, 731, 740, 747
+ 0, 5, 8, 11, 17, 24, 28, 34, 44, 53, 62, 71, 75, 80, 94, 108, 120, 134, 144,
+ 155, 165, 176, 185, 197, 208, 220, 233, 243, 255, 275, 292, 296, 301, 310,
+ 318, 329, 334, 341, 346, 357, 367, 373, 380, 385, 390, 394, 399, 403, 412,
+ 417, 425, 431, 436, 440, 445, 454, 458, 464, 472, 476, 481, 489, 498, 504,
+ 514, 522, 526, 530, 535, 543, 553, 561, 569, 576, 586, 598, 604, 610, 617,
+ 624, 630, 637, 641, 651, 655, 662, 667, 672, 676, 680, 684, 689, 694, 701,
+ 708, 714, 720, 724, 728, 732, 741, 746, 750, 761, 769, 778, 782, 788, 795,
+ 804, 811
};
// @EnumStringEnd@
diff --git a/src/asmjit/x86/x86globals.h b/src/asmjit/x86/x86globals.h
index f7d258f..21da129 100644
--- a/src/asmjit/x86/x86globals.h
+++ b/src/asmjit/x86/x86globals.h
@@ -422,6 +422,7 @@ struct Inst : public BaseInst {
kIdLddqu, //!< Instruction 'lddqu' {SSE3}.
kIdLdmxcsr, //!< Instruction 'ldmxcsr' {SSE}.
kIdLds, //!< Instruction 'lds' (X86).
+ kIdLdtilecfg, //!< Instruction 'ldtilecfg' {AMX_TILE} (X64).
kIdLea, //!< Instruction 'lea'.
kIdLeave, //!< Instruction 'leave'.
kIdLes, //!< Instruction 'les' (X86).
@@ -449,6 +450,7 @@ struct Inst : public BaseInst {
kIdMaxps, //!< Instruction 'maxps' {SSE}.
kIdMaxsd, //!< Instruction 'maxsd' {SSE2}.
kIdMaxss, //!< Instruction 'maxss' {SSE}.
+ kIdMcommit, //!< Instruction 'mcommit' {MCOMMIT}.
kIdMfence, //!< Instruction 'mfence' {SSE2}.
kIdMinpd, //!< Instruction 'minpd' {SSE2}.
kIdMinps, //!< Instruction 'minps' {SSE}.
@@ -550,6 +552,7 @@ struct Inst : public BaseInst {
kIdPcmpistri, //!< Instruction 'pcmpistri' {SSE4_2}.
kIdPcmpistrm, //!< Instruction 'pcmpistrm' {SSE4_2}.
kIdPcommit, //!< Instruction 'pcommit' {PCOMMIT}.
+ kIdPconfig, //!< Instruction 'pconfig' {PCONFIG}.
kIdPdep, //!< Instruction 'pdep' {BMI2}.
kIdPext, //!< Instruction 'pext' {BMI2}.
kIdPextrb, //!< Instruction 'pextrb' {SSE4_1}.
@@ -653,6 +656,7 @@ struct Inst : public BaseInst {
kIdPslldq, //!< Instruction 'pslldq' {SSE2}.
kIdPsllq, //!< Instruction 'psllq' {MMX|SSE2}.
kIdPsllw, //!< Instruction 'psllw' {MMX|SSE2}.
+ kIdPsmash, //!< Instruction 'psmash' {SNP} (X64).
kIdPsrad, //!< Instruction 'psrad' {MMX|SSE2}.
kIdPsraw, //!< Instruction 'psraw' {MMX|SSE2}.
kIdPsrld, //!< Instruction 'psrld' {MMX|SSE2}.
@@ -683,6 +687,7 @@ struct Inst : public BaseInst {
kIdPushf, //!< Instruction 'pushf'.
kIdPushfd, //!< Instruction 'pushfd' (X86).
kIdPushfq, //!< Instruction 'pushfq' (X64).
+ kIdPvalidate, //!< Instruction 'pvalidate' {SNP}.
kIdPxor, //!< Instruction 'pxor' {MMX|SSE2}.
kIdRcl, //!< Instruction 'rcl'.
kIdRcpps, //!< Instruction 'rcpps' {SSE}.
@@ -693,11 +698,14 @@ struct Inst : public BaseInst {
kIdRdmsr, //!< Instruction 'rdmsr' {MSR}.
kIdRdpid, //!< Instruction 'rdpid' {RDPID}.
kIdRdpmc, //!< Instruction 'rdpmc'.
+ kIdRdpru, //!< Instruction 'rdpru' {RDPRU}.
kIdRdrand, //!< Instruction 'rdrand' {RDRAND}.
kIdRdseed, //!< Instruction 'rdseed' {RDSEED}.
kIdRdtsc, //!< Instruction 'rdtsc' {RDTSC}.
kIdRdtscp, //!< Instruction 'rdtscp' {RDTSCP}.
kIdRet, //!< Instruction 'ret'.
+ kIdRmpadjust, //!< Instruction 'rmpadjust' {SNP} (X64).
+ kIdRmpupdate, //!< Instruction 'rmpupdate' {SNP} (X64).
kIdRol, //!< Instruction 'rol'.
kIdRor, //!< Instruction 'ror'.
kIdRorx, //!< Instruction 'rorx' {BMI2}.
@@ -714,6 +722,7 @@ struct Inst : public BaseInst {
kIdSarx, //!< Instruction 'sarx' {BMI2}.
kIdSbb, //!< Instruction 'sbb'.
kIdScas, //!< Instruction 'scas'.
+ kIdSerialize, //!< Instruction 'serialize' {SERIALIZE}.
kIdSeta, //!< Instruction 'seta'.
kIdSetae, //!< Instruction 'setae'.
kIdSetb, //!< Instruction 'setb'.
@@ -778,6 +787,7 @@ struct Inst : public BaseInst {
kIdStmxcsr, //!< Instruction 'stmxcsr' {SSE}.
kIdStos, //!< Instruction 'stos'.
kIdStr, //!< Instruction 'str'.
+ kIdSttilecfg, //!< Instruction 'sttilecfg' {AMX_TILE} (X64).
kIdSub, //!< Instruction 'sub'.
kIdSubpd, //!< Instruction 'subpd' {SSE2}.
kIdSubps, //!< Instruction 'subps' {SSE}.
@@ -791,12 +801,25 @@ struct Inst : public BaseInst {
kIdSysret, //!< Instruction 'sysret' (X64).
kIdSysret64, //!< Instruction 'sysret64' (X64).
kIdT1mskc, //!< Instruction 't1mskc' {TBM}.
+ kIdTdpbf16ps, //!< Instruction 'tdpbf16ps' {AMX_BF16} (X64).
+ kIdTdpbssd, //!< Instruction 'tdpbssd' {AMX_INT8} (X64).
+ kIdTdpbsud, //!< Instruction 'tdpbsud' {AMX_INT8} (X64).
+ kIdTdpbusd, //!< Instruction 'tdpbusd' {AMX_INT8} (X64).
+ kIdTdpbuud, //!< Instruction 'tdpbuud' {AMX_INT8} (X64).
kIdTest, //!< Instruction 'test'.
+ kIdTileloadd, //!< Instruction 'tileloadd' {AMX_TILE} (X64).
+ kIdTileloaddt1, //!< Instruction 'tileloaddt1' {AMX_TILE} (X64).
+ kIdTilerelease, //!< Instruction 'tilerelease' {AMX_TILE} (X64).
+ kIdTilestored, //!< Instruction 'tilestored' {AMX_TILE} (X64).
+ kIdTilezero, //!< Instruction 'tilezero' {AMX_TILE} (X64).
+ kIdTpause, //!< Instruction 'tpause' {WAITPKG}.
kIdTzcnt, //!< Instruction 'tzcnt' {BMI}.
kIdTzmsk, //!< Instruction 'tzmsk' {TBM}.
kIdUcomisd, //!< Instruction 'ucomisd' {SSE2}.
kIdUcomiss, //!< Instruction 'ucomiss' {SSE}.
kIdUd2, //!< Instruction 'ud2'.
+ kIdUmonitor, //!< Instruction 'umonitor' {WAITPKG}.
+ kIdUmwait, //!< Instruction 'umwait' {WAITPKG}.
kIdUnpckhpd, //!< Instruction 'unpckhpd' {SSE2}.
kIdUnpckhps, //!< Instruction 'unpckhps' {SSE}.
kIdUnpcklpd, //!< Instruction 'unpcklpd' {SSE2}.
@@ -1119,6 +1142,8 @@ struct Inst : public BaseInst {
kIdVmxon, //!< Instruction 'vmxon' {VMX}.
kIdVorpd, //!< Instruction 'vorpd' {AVX|AVX512_DQ+VL}.
kIdVorps, //!< Instruction 'vorps' {AVX|AVX512_DQ+VL}.
+ kIdVp2intersectd, //!< Instruction 'vp2intersectd' {AVX512_VP2INTERSECT}.
+ kIdVp2intersectq, //!< Instruction 'vp2intersectq' {AVX512_VP2INTERSECT}.
kIdVp4dpwssd, //!< Instruction 'vp4dpwssd' {AVX512_4VNNIW}.
kIdVp4dpwssds, //!< Instruction 'vp4dpwssds' {AVX512_4VNNIW}.
kIdVpabsb, //!< Instruction 'vpabsb' {AVX|AVX2|AVX512_BW+VL}.
@@ -1538,6 +1563,7 @@ struct Inst : public BaseInst {
kIdXor, //!< Instruction 'xor'.
kIdXorpd, //!< Instruction 'xorpd' {SSE2}.
kIdXorps, //!< Instruction 'xorps' {SSE}.
+ kIdXresldtrk, //!< Instruction 'xresldtrk' {TSXLDTRK}.
kIdXrstor, //!< Instruction 'xrstor' {XSAVE}.
kIdXrstor64, //!< Instruction 'xrstor64' {XSAVE} (X64).
kIdXrstors, //!< Instruction 'xrstors' {XSAVES}.
@@ -1551,6 +1577,7 @@ struct Inst : public BaseInst {
kIdXsaves, //!< Instruction 'xsaves' {XSAVES}.
kIdXsaves64, //!< Instruction 'xsaves64' {XSAVES} (X64).
kIdXsetbv, //!< Instruction 'xsetbv' {XSAVE}.
+ kIdXsusldtrk, //!< Instruction 'xsusldtrk' {TSXLDTRK}.
kIdXtest, //!< Instruction 'xtest' {TSX}.
_kIdCount
// ${InstId:End}
diff --git a/src/asmjit/x86/x86instapi.cpp b/src/asmjit/x86/x86instapi.cpp
index 2dfd25f..f6c3bdd 100644
--- a/src/asmjit/x86/x86instapi.cpp
+++ b/src/asmjit/x86/x86instapi.cpp
@@ -142,6 +142,7 @@ struct X86ValidationData {
(X == Reg::kTypeDReg ) ? InstDB::kOpDReg : \
(X == Reg::kTypeSt ) ? InstDB::kOpSt : \
(X == Reg::kTypeBnd ) ? InstDB::kOpBnd : \
+ (X == Reg::kTypeTmm ) ? InstDB::kOpTmm : \
(X == Reg::kTypeRip ) ? InstDB::kOpNone : InstDB::kOpNone
static const uint32_t _x86OpFlagFromRegType[Reg::kTypeMax + 1] = { ASMJIT_LOOKUP_TABLE_32(VALUE, 0) };
#undef VALUE
@@ -162,6 +163,7 @@ static const uint32_t _x86OpFlagFromRegType[Reg::kTypeMax + 1] = { ASMJIT_LOOKUP
(X == Reg::kTypeDReg ) ? 0x000000FFu : \
(X == Reg::kTypeSt ) ? 0x000000FFu : \
(X == Reg::kTypeBnd ) ? 0x0000000Fu : \
+ (X == Reg::kTypeTmm ) ? 0x000000FFu : \
(X == Reg::kTypeRip ) ? 0x00000001u : 0u
#define REG_MASK_FROM_REG_TYPE_X64(X) \
@@ -180,6 +182,7 @@ static const uint32_t _x86OpFlagFromRegType[Reg::kTypeMax + 1] = { ASMJIT_LOOKUP
(X == Reg::kTypeDReg ) ? 0x0000FFFFu : \
(X == Reg::kTypeSt ) ? 0x000000FFu : \
(X == Reg::kTypeBnd ) ? 0x0000000Fu : \
+ (X == Reg::kTypeTmm ) ? 0x000000FFu : \
(X == Reg::kTypeRip ) ? 0x00000001u : 0u
static const X86ValidationData _x86ValidationData = {
@@ -821,13 +824,15 @@ Error InstInternal::queryRWInfo(uint32_t arch, const BaseInst& inst, const Opera
const InstDB::CommonInfoTableB& tabB = InstDB::_commonInfoTableB[InstDB::_instInfoTable[instId]._commonInfoIndexB];
const InstDB::RWFlagsInfoTable& rwFlags = InstDB::_rwFlagsInfoTable[tabB._rwFlagsIndex];
- // Each RWInfo contains two indexes
- // [0] - OpCount == 2
- // [1] - OpCount != 2
- // They are used this way as there are instructions that have 2 and 3
- // operand overloads that use different semantics. So instead of adding
- // more special cases we just separated their data tables.
- const InstDB::RWInfo& instRwInfo = InstDB::rwInfo[InstDB::rwInfoIndex[instId * 2u + uint32_t(opCount != 2)]];
+
+ // There are two data tables, one for `opCount == 2` and the second for
+ // `opCount != 2`. There are two reasons for that:
+ // - There are instructions that share the same name that have both 2
+ // or 3 operands, which have different RW information / semantics.
+ // - There must be 2 tables otherwise the lookup index won't fit into
+ // 8 bits (there is more than 256 records of combined rwInfo A and B).
+ const InstDB::RWInfo& instRwInfo = opCount == 2 ? InstDB::rwInfoA[InstDB::rwInfoIndexA[instId]]
+ : InstDB::rwInfoB[InstDB::rwInfoIndexB[instId]];
const InstDB::RWInfoRm& instRmInfo = InstDB::rwInfoRm[instRwInfo.rmInfo];
out->_instFlags = 0;
diff --git a/src/asmjit/x86/x86instdb.cpp b/src/asmjit/x86/x86instdb.cpp
index 72ad098..4ec5ea2 100644
--- a/src/asmjit/x86/x86instdb.cpp
+++ b/src/asmjit/x86/x86instdb.cpp
@@ -101,26 +101,26 @@ const InstDB::InstInfo InstDB::_instInfoTable[] = {
INST(Aas , X86Op_xAX , O(000000,3F,_,_,_,_,_,_ ), 0 , 0 , 0 , 13 , 1 , 1 ), // #4
INST(Adc , X86Arith , O(000000,10,2,_,x,_,_,_ ), 0 , 1 , 0 , 17 , 3 , 2 ), // #5
INST(Adcx , X86Rm , O(660F38,F6,_,_,x,_,_,_ ), 0 , 2 , 0 , 21 , 4 , 3 ), // #6
- INST(Add , X86Arith , O(000000,00,0,_,x,_,_,_ ), 0 , 0 , 0 , 761 , 3 , 1 ), // #7
- INST(Addpd , ExtRm , O(660F00,58,_,_,_,_,_,_ ), 0 , 3 , 0 , 4814 , 5 , 4 ), // #8
- INST(Addps , ExtRm , O(000F00,58,_,_,_,_,_,_ ), 0 , 4 , 0 , 4826 , 5 , 5 ), // #9
- INST(Addsd , ExtRm , O(F20F00,58,_,_,_,_,_,_ ), 0 , 5 , 0 , 5048 , 6 , 4 ), // #10
- INST(Addss , ExtRm , O(F30F00,58,_,_,_,_,_,_ ), 0 , 6 , 0 , 2955 , 7 , 5 ), // #11
- INST(Addsubpd , ExtRm , O(660F00,D0,_,_,_,_,_,_ ), 0 , 3 , 0 , 4553 , 5 , 6 ), // #12
- INST(Addsubps , ExtRm , O(F20F00,D0,_,_,_,_,_,_ ), 0 , 5 , 0 , 4565 , 5 , 6 ), // #13
+ INST(Add , X86Arith , O(000000,00,0,_,x,_,_,_ ), 0 , 0 , 0 , 3020 , 3 , 1 ), // #7
+ INST(Addpd , ExtRm , O(660F00,58,_,_,_,_,_,_ ), 0 , 3 , 0 , 5002 , 5 , 4 ), // #8
+ INST(Addps , ExtRm , O(000F00,58,_,_,_,_,_,_ ), 0 , 4 , 0 , 5014 , 5 , 5 ), // #9
+ INST(Addsd , ExtRm , O(F20F00,58,_,_,_,_,_,_ ), 0 , 5 , 0 , 5236 , 6 , 4 ), // #10
+ INST(Addss , ExtRm , O(F30F00,58,_,_,_,_,_,_ ), 0 , 6 , 0 , 3143 , 7 , 5 ), // #11
+ INST(Addsubpd , ExtRm , O(660F00,D0,_,_,_,_,_,_ ), 0 , 3 , 0 , 4741 , 5 , 6 ), // #12
+ INST(Addsubps , ExtRm , O(F20F00,D0,_,_,_,_,_,_ ), 0 , 5 , 0 , 4753 , 5 , 6 ), // #13
INST(Adox , X86Rm , O(F30F38,F6,_,_,x,_,_,_ ), 0 , 7 , 0 , 26 , 4 , 7 ), // #14
- INST(Aesdec , ExtRm , O(660F38,DE,_,_,_,_,_,_ ), 0 , 2 , 0 , 3010 , 5 , 8 ), // #15
- INST(Aesdeclast , ExtRm , O(660F38,DF,_,_,_,_,_,_ ), 0 , 2 , 0 , 3018 , 5 , 8 ), // #16
- INST(Aesenc , ExtRm , O(660F38,DC,_,_,_,_,_,_ ), 0 , 2 , 0 , 3030 , 5 , 8 ), // #17
- INST(Aesenclast , ExtRm , O(660F38,DD,_,_,_,_,_,_ ), 0 , 2 , 0 , 3038 , 5 , 8 ), // #18
- INST(Aesimc , ExtRm , O(660F38,DB,_,_,_,_,_,_ ), 0 , 2 , 0 , 3050 , 5 , 8 ), // #19
- INST(Aeskeygenassist , ExtRmi , O(660F3A,DF,_,_,_,_,_,_ ), 0 , 8 , 0 , 3058 , 8 , 8 ), // #20
- INST(And , X86Arith , O(000000,20,4,_,x,_,_,_ ), 0 , 9 , 0 , 2433 , 9 , 1 ), // #21
- INST(Andn , VexRvm_Wx , V(000F38,F2,_,0,x,_,_,_ ), 0 , 10 , 0 , 6494 , 10 , 9 ), // #22
- INST(Andnpd , ExtRm , O(660F00,55,_,_,_,_,_,_ ), 0 , 3 , 0 , 3091 , 5 , 4 ), // #23
- INST(Andnps , ExtRm , O(000F00,55,_,_,_,_,_,_ ), 0 , 4 , 0 , 3099 , 5 , 5 ), // #24
- INST(Andpd , ExtRm , O(660F00,54,_,_,_,_,_,_ ), 0 , 3 , 0 , 4067 , 11 , 4 ), // #25
- INST(Andps , ExtRm , O(000F00,54,_,_,_,_,_,_ ), 0 , 4 , 0 , 4077 , 11 , 5 ), // #26
+ INST(Aesdec , ExtRm , O(660F38,DE,_,_,_,_,_,_ ), 0 , 2 , 0 , 3198 , 5 , 8 ), // #15
+ INST(Aesdeclast , ExtRm , O(660F38,DF,_,_,_,_,_,_ ), 0 , 2 , 0 , 3206 , 5 , 8 ), // #16
+ INST(Aesenc , ExtRm , O(660F38,DC,_,_,_,_,_,_ ), 0 , 2 , 0 , 3218 , 5 , 8 ), // #17
+ INST(Aesenclast , ExtRm , O(660F38,DD,_,_,_,_,_,_ ), 0 , 2 , 0 , 3226 , 5 , 8 ), // #18
+ INST(Aesimc , ExtRm , O(660F38,DB,_,_,_,_,_,_ ), 0 , 2 , 0 , 3238 , 5 , 8 ), // #19
+ INST(Aeskeygenassist , ExtRmi , O(660F3A,DF,_,_,_,_,_,_ ), 0 , 8 , 0 , 3246 , 8 , 8 ), // #20
+ INST(And , X86Arith , O(000000,20,4,_,x,_,_,_ ), 0 , 9 , 0 , 2462 , 9 , 1 ), // #21
+ INST(Andn , VexRvm_Wx , V(000F38,F2,_,0,x,_,_,_ ), 0 , 10 , 0 , 6710 , 10 , 9 ), // #22
+ INST(Andnpd , ExtRm , O(660F00,55,_,_,_,_,_,_ ), 0 , 3 , 0 , 3279 , 5 , 4 ), // #23
+ INST(Andnps , ExtRm , O(000F00,55,_,_,_,_,_,_ ), 0 , 4 , 0 , 3287 , 5 , 5 ), // #24
+ INST(Andpd , ExtRm , O(660F00,54,_,_,_,_,_,_ ), 0 , 3 , 0 , 4255 , 11 , 4 ), // #25
+ INST(Andps , ExtRm , O(000F00,54,_,_,_,_,_,_ ), 0 , 4 , 0 , 4265 , 11 , 5 ), // #26
INST(Arpl , X86Mr_NoSize , O(000000,63,_,_,_,_,_,_ ), 0 , 0 , 0 , 31 , 12 , 10 ), // #27
INST(Bextr , VexRmv_Wx , V(000F38,F7,_,0,x,_,_,_ ), 0 , 10 , 0 , 36 , 13 , 9 ), // #28
INST(Blcfill , VexVm_Wx , V(XOP_M9,01,1,0,x,_,_,_ ), 0 , 11 , 0 , 42 , 14 , 11 ), // #29
@@ -128,10 +128,10 @@ const InstDB::InstInfo InstDB::_instInfoTable[] = {
INST(Blcic , VexVm_Wx , V(XOP_M9,01,5,0,x,_,_,_ ), 0 , 13 , 0 , 55 , 14 , 11 ), // #31
INST(Blcmsk , VexVm_Wx , V(XOP_M9,02,1,0,x,_,_,_ ), 0 , 11 , 0 , 61 , 14 , 11 ), // #32
INST(Blcs , VexVm_Wx , V(XOP_M9,01,3,0,x,_,_,_ ), 0 , 14 , 0 , 68 , 14 , 11 ), // #33
- INST(Blendpd , ExtRmi , O(660F3A,0D,_,_,_,_,_,_ ), 0 , 8 , 0 , 3177 , 8 , 12 ), // #34
- INST(Blendps , ExtRmi , O(660F3A,0C,_,_,_,_,_,_ ), 0 , 8 , 0 , 3186 , 8 , 12 ), // #35
- INST(Blendvpd , ExtRm_XMM0 , O(660F38,15,_,_,_,_,_,_ ), 0 , 2 , 0 , 3195 , 15 , 12 ), // #36
- INST(Blendvps , ExtRm_XMM0 , O(660F38,14,_,_,_,_,_,_ ), 0 , 2 , 0 , 3205 , 15 , 12 ), // #37
+ INST(Blendpd , ExtRmi , O(660F3A,0D,_,_,_,_,_,_ ), 0 , 8 , 0 , 3365 , 8 , 12 ), // #34
+ INST(Blendps , ExtRmi , O(660F3A,0C,_,_,_,_,_,_ ), 0 , 8 , 0 , 3374 , 8 , 12 ), // #35
+ INST(Blendvpd , ExtRm_XMM0 , O(660F38,15,_,_,_,_,_,_ ), 0 , 2 , 0 , 3383 , 15 , 12 ), // #36
+ INST(Blendvps , ExtRm_XMM0 , O(660F38,14,_,_,_,_,_,_ ), 0 , 2 , 0 , 3393 , 15 , 12 ), // #37
INST(Blsfill , VexVm_Wx , V(XOP_M9,01,2,0,x,_,_,_ ), 0 , 15 , 0 , 73 , 14 , 11 ), // #38
INST(Blsi , VexVm_Wx , V(000F38,F3,3,0,x,_,_,_ ), 0 , 16 , 0 , 81 , 14 , 9 ), // #39
INST(Blsic , VexVm_Wx , V(XOP_M9,01,6,0,x,_,_,_ ), 0 , 12 , 0 , 86 , 14 , 11 ), // #40
@@ -153,7 +153,7 @@ const InstDB::InstInfo InstDB::_instInfoTable[] = {
INST(Btr , X86Bt , O(000F00,B3,_,_,x,_,_,_ ), O(000F00,BA,6,_,x,_,_,_ ), 4 , 4 , 176 , 25 , 14 ), // #56
INST(Bts , X86Bt , O(000F00,AB,_,_,x,_,_,_ ), O(000F00,BA,5,_,x,_,_,_ ), 4 , 5 , 180 , 25 , 14 ), // #57
INST(Bzhi , VexRmv_Wx , V(000F38,F5,_,0,x,_,_,_ ), 0 , 10 , 0 , 184 , 13 , 15 ), // #58
- INST(Call , X86Call , O(000000,FF,2,_,_,_,_,_ ), 0 , 1 , 0 , 2848 , 26 , 1 ), // #59
+ INST(Call , X86Call , O(000000,FF,2,_,_,_,_,_ ), 0 , 1 , 0 , 2917 , 26 , 1 ), // #59
INST(Cbw , X86Op_xAX , O(660000,98,_,_,_,_,_,_ ), 0 , 19 , 0 , 189 , 27 , 0 ), // #60
INST(Cdq , X86Op_xDX_xAX , O(000000,99,_,_,_,_,_,_ ), 0 , 0 , 0 , 193 , 28 , 0 ), // #61
INST(Cdqe , X86Op_xAX , O(000000,98,_,_,1,_,_,_ ), 0 , 20 , 0 , 197 , 29 , 0 ), // #62
@@ -200,62 +200,62 @@ const InstDB::InstInfo InstDB::_instInfoTable[] = {
INST(Cmovs , X86Rm , O(000F00,48,_,_,x,_,_,_ ), 0 , 4 , 0 , 424 , 22 , 34 ), // #103
INST(Cmovz , X86Rm , O(000F00,44,_,_,x,_,_,_ ), 0 , 4 , 0 , 430 , 22 , 29 ), // #104
INST(Cmp , X86Arith , O(000000,38,7,_,x,_,_,_ ), 0 , 25 , 0 , 436 , 33 , 1 ), // #105
- INST(Cmppd , ExtRmi , O(660F00,C2,_,_,_,_,_,_ ), 0 , 3 , 0 , 3431 , 8 , 4 ), // #106
- INST(Cmpps , ExtRmi , O(000F00,C2,_,_,_,_,_,_ ), 0 , 4 , 0 , 3438 , 8 , 5 ), // #107
+ INST(Cmppd , ExtRmi , O(660F00,C2,_,_,_,_,_,_ ), 0 , 3 , 0 , 3619 , 8 , 4 ), // #106
+ INST(Cmpps , ExtRmi , O(000F00,C2,_,_,_,_,_,_ ), 0 , 4 , 0 , 3626 , 8 , 5 ), // #107
INST(Cmps , X86StrMm , O(000000,A6,_,_,_,_,_,_ ), 0 , 0 , 0 , 440 , 34 , 35 ), // #108
- INST(Cmpsd , ExtRmi , O(F20F00,C2,_,_,_,_,_,_ ), 0 , 5 , 0 , 3445 , 35 , 4 ), // #109
- INST(Cmpss , ExtRmi , O(F30F00,C2,_,_,_,_,_,_ ), 0 , 6 , 0 , 3452 , 36 , 5 ), // #110
+ INST(Cmpsd , ExtRmi , O(F20F00,C2,_,_,_,_,_,_ ), 0 , 5 , 0 , 3633 , 35 , 4 ), // #109
+ INST(Cmpss , ExtRmi , O(F30F00,C2,_,_,_,_,_,_ ), 0 , 6 , 0 , 3640 , 36 , 5 ), // #110
INST(Cmpxchg , X86Cmpxchg , O(000F00,B0,_,_,x,_,_,_ ), 0 , 4 , 0 , 445 , 37 , 36 ), // #111
INST(Cmpxchg16b , X86Cmpxchg8b_16b , O(000F00,C7,1,_,1,_,_,_ ), 0 , 26 , 0 , 453 , 38 , 37 ), // #112
INST(Cmpxchg8b , X86Cmpxchg8b_16b , O(000F00,C7,1,_,_,_,_,_ ), 0 , 27 , 0 , 464 , 39 , 38 ), // #113
- INST(Comisd , ExtRm , O(660F00,2F,_,_,_,_,_,_ ), 0 , 3 , 0 , 9930 , 6 , 39 ), // #114
- INST(Comiss , ExtRm , O(000F00,2F,_,_,_,_,_,_ ), 0 , 4 , 0 , 9939 , 7 , 40 ), // #115
+ INST(Comisd , ExtRm , O(660F00,2F,_,_,_,_,_,_ ), 0 , 3 , 0 , 10146, 6 , 39 ), // #114
+ INST(Comiss , ExtRm , O(000F00,2F,_,_,_,_,_,_ ), 0 , 4 , 0 , 10155, 7 , 40 ), // #115
INST(Cpuid , X86Op , O(000F00,A2,_,_,_,_,_,_ ), 0 , 4 , 0 , 474 , 40 , 41 ), // #116
INST(Cqo , X86Op_xDX_xAX , O(000000,99,_,_,1,_,_,_ ), 0 , 20 , 0 , 480 , 41 , 0 ), // #117
INST(Crc32 , X86Crc , O(F20F38,F0,_,_,x,_,_,_ ), 0 , 28 , 0 , 484 , 42 , 42 ), // #118
- INST(Cvtdq2pd , ExtRm , O(F30F00,E6,_,_,_,_,_,_ ), 0 , 6 , 0 , 3499 , 6 , 4 ), // #119
- INST(Cvtdq2ps , ExtRm , O(000F00,5B,_,_,_,_,_,_ ), 0 , 4 , 0 , 3509 , 5 , 4 ), // #120
- INST(Cvtpd2dq , ExtRm , O(F20F00,E6,_,_,_,_,_,_ ), 0 , 5 , 0 , 3548 , 5 , 4 ), // #121
+ INST(Cvtdq2pd , ExtRm , O(F30F00,E6,_,_,_,_,_,_ ), 0 , 6 , 0 , 3687 , 6 , 4 ), // #119
+ INST(Cvtdq2ps , ExtRm , O(000F00,5B,_,_,_,_,_,_ ), 0 , 4 , 0 , 3697 , 5 , 4 ), // #120
+ INST(Cvtpd2dq , ExtRm , O(F20F00,E6,_,_,_,_,_,_ ), 0 , 5 , 0 , 3736 , 5 , 4 ), // #121
INST(Cvtpd2pi , ExtRm , O(660F00,2D,_,_,_,_,_,_ ), 0 , 3 , 0 , 490 , 43 , 4 ), // #122
- INST(Cvtpd2ps , ExtRm , O(660F00,5A,_,_,_,_,_,_ ), 0 , 3 , 0 , 3558 , 5 , 4 ), // #123
+ INST(Cvtpd2ps , ExtRm , O(660F00,5A,_,_,_,_,_,_ ), 0 , 3 , 0 , 3746 , 5 , 4 ), // #123
INST(Cvtpi2pd , ExtRm , O(660F00,2A,_,_,_,_,_,_ ), 0 , 3 , 0 , 499 , 44 , 4 ), // #124
INST(Cvtpi2ps , ExtRm , O(000F00,2A,_,_,_,_,_,_ ), 0 , 4 , 0 , 508 , 44 , 5 ), // #125
- INST(Cvtps2dq , ExtRm , O(660F00,5B,_,_,_,_,_,_ ), 0 , 3 , 0 , 3610 , 5 , 4 ), // #126
- INST(Cvtps2pd , ExtRm , O(000F00,5A,_,_,_,_,_,_ ), 0 , 4 , 0 , 3620 , 6 , 4 ), // #127
+ INST(Cvtps2dq , ExtRm , O(660F00,5B,_,_,_,_,_,_ ), 0 , 3 , 0 , 3798 , 5 , 4 ), // #126
+ INST(Cvtps2pd , ExtRm , O(000F00,5A,_,_,_,_,_,_ ), 0 , 4 , 0 , 3808 , 6 , 4 ), // #127
INST(Cvtps2pi , ExtRm , O(000F00,2D,_,_,_,_,_,_ ), 0 , 4 , 0 , 517 , 45 , 5 ), // #128
- INST(Cvtsd2si , ExtRm_Wx , O(F20F00,2D,_,_,x,_,_,_ ), 0 , 5 , 0 , 3692 , 46 , 4 ), // #129
- INST(Cvtsd2ss , ExtRm , O(F20F00,5A,_,_,_,_,_,_ ), 0 , 5 , 0 , 3702 , 6 , 4 ), // #130
- INST(Cvtsi2sd , ExtRm_Wx , O(F20F00,2A,_,_,x,_,_,_ ), 0 , 5 , 0 , 3723 , 47 , 4 ), // #131
- INST(Cvtsi2ss , ExtRm_Wx , O(F30F00,2A,_,_,x,_,_,_ ), 0 , 6 , 0 , 3733 , 47 , 5 ), // #132
- INST(Cvtss2sd , ExtRm , O(F30F00,5A,_,_,_,_,_,_ ), 0 , 6 , 0 , 3743 , 7 , 4 ), // #133
- INST(Cvtss2si , ExtRm_Wx , O(F30F00,2D,_,_,x,_,_,_ ), 0 , 6 , 0 , 3753 , 48 , 5 ), // #134
- INST(Cvttpd2dq , ExtRm , O(660F00,E6,_,_,_,_,_,_ ), 0 , 3 , 0 , 3774 , 5 , 4 ), // #135
+ INST(Cvtsd2si , ExtRm_Wx , O(F20F00,2D,_,_,x,_,_,_ ), 0 , 5 , 0 , 3880 , 46 , 4 ), // #129
+ INST(Cvtsd2ss , ExtRm , O(F20F00,5A,_,_,_,_,_,_ ), 0 , 5 , 0 , 3890 , 6 , 4 ), // #130
+ INST(Cvtsi2sd , ExtRm_Wx , O(F20F00,2A,_,_,x,_,_,_ ), 0 , 5 , 0 , 3911 , 47 , 4 ), // #131
+ INST(Cvtsi2ss , ExtRm_Wx , O(F30F00,2A,_,_,x,_,_,_ ), 0 , 6 , 0 , 3921 , 47 , 5 ), // #132
+ INST(Cvtss2sd , ExtRm , O(F30F00,5A,_,_,_,_,_,_ ), 0 , 6 , 0 , 3931 , 7 , 4 ), // #133
+ INST(Cvtss2si , ExtRm_Wx , O(F30F00,2D,_,_,x,_,_,_ ), 0 , 6 , 0 , 3941 , 48 , 5 ), // #134
+ INST(Cvttpd2dq , ExtRm , O(660F00,E6,_,_,_,_,_,_ ), 0 , 3 , 0 , 3962 , 5 , 4 ), // #135
INST(Cvttpd2pi , ExtRm , O(660F00,2C,_,_,_,_,_,_ ), 0 , 3 , 0 , 526 , 43 , 4 ), // #136
- INST(Cvttps2dq , ExtRm , O(F30F00,5B,_,_,_,_,_,_ ), 0 , 6 , 0 , 3820 , 5 , 4 ), // #137
+ INST(Cvttps2dq , ExtRm , O(F30F00,5B,_,_,_,_,_,_ ), 0 , 6 , 0 , 4008 , 5 , 4 ), // #137
INST(Cvttps2pi , ExtRm , O(000F00,2C,_,_,_,_,_,_ ), 0 , 4 , 0 , 536 , 45 , 5 ), // #138
- INST(Cvttsd2si , ExtRm_Wx , O(F20F00,2C,_,_,x,_,_,_ ), 0 , 5 , 0 , 3866 , 46 , 4 ), // #139
- INST(Cvttss2si , ExtRm_Wx , O(F30F00,2C,_,_,x,_,_,_ ), 0 , 6 , 0 , 3889 , 48 , 5 ), // #140
+ INST(Cvttsd2si , ExtRm_Wx , O(F20F00,2C,_,_,x,_,_,_ ), 0 , 5 , 0 , 4054 , 46 , 4 ), // #139
+ INST(Cvttss2si , ExtRm_Wx , O(F30F00,2C,_,_,x,_,_,_ ), 0 , 6 , 0 , 4077 , 48 , 5 ), // #140
INST(Cwd , X86Op_xDX_xAX , O(660000,99,_,_,_,_,_,_ ), 0 , 19 , 0 , 546 , 49 , 0 ), // #141
INST(Cwde , X86Op_xAX , O(000000,98,_,_,_,_,_,_ ), 0 , 0 , 0 , 550 , 50 , 0 ), // #142
INST(Daa , X86Op , O(000000,27,_,_,_,_,_,_ ), 0 , 0 , 0 , 555 , 1 , 1 ), // #143
INST(Das , X86Op , O(000000,2F,_,_,_,_,_,_ ), 0 , 0 , 0 , 559 , 1 , 1 ), // #144
- INST(Dec , X86IncDec , O(000000,FE,1,_,x,_,_,_ ), O(000000,48,_,_,x,_,_,_ ), 29 , 6 , 3013 , 51 , 43 ), // #145
+ INST(Dec , X86IncDec , O(000000,FE,1,_,x,_,_,_ ), O(000000,48,_,_,x,_,_,_ ), 29 , 6 , 3201 , 51 , 43 ), // #145
INST(Div , X86M_GPB_MulDiv , O(000000,F6,6,_,x,_,_,_ ), 0 , 30 , 0 , 780 , 52 , 1 ), // #146
- INST(Divpd , ExtRm , O(660F00,5E,_,_,_,_,_,_ ), 0 , 3 , 0 , 3988 , 5 , 4 ), // #147
- INST(Divps , ExtRm , O(000F00,5E,_,_,_,_,_,_ ), 0 , 4 , 0 , 3995 , 5 , 5 ), // #148
- INST(Divsd , ExtRm , O(F20F00,5E,_,_,_,_,_,_ ), 0 , 5 , 0 , 4002 , 6 , 4 ), // #149
- INST(Divss , ExtRm , O(F30F00,5E,_,_,_,_,_,_ ), 0 , 6 , 0 , 4009 , 7 , 5 ), // #150
- INST(Dppd , ExtRmi , O(660F3A,41,_,_,_,_,_,_ ), 0 , 8 , 0 , 4026 , 8 , 12 ), // #151
- INST(Dpps , ExtRmi , O(660F3A,40,_,_,_,_,_,_ ), 0 , 8 , 0 , 4032 , 8 , 12 ), // #152
+ INST(Divpd , ExtRm , O(660F00,5E,_,_,_,_,_,_ ), 0 , 3 , 0 , 4176 , 5 , 4 ), // #147
+ INST(Divps , ExtRm , O(000F00,5E,_,_,_,_,_,_ ), 0 , 4 , 0 , 4183 , 5 , 5 ), // #148
+ INST(Divsd , ExtRm , O(F20F00,5E,_,_,_,_,_,_ ), 0 , 5 , 0 , 4190 , 6 , 4 ), // #149
+ INST(Divss , ExtRm , O(F30F00,5E,_,_,_,_,_,_ ), 0 , 6 , 0 , 4197 , 7 , 5 ), // #150
+ INST(Dppd , ExtRmi , O(660F3A,41,_,_,_,_,_,_ ), 0 , 8 , 0 , 4214 , 8 , 12 ), // #151
+ INST(Dpps , ExtRmi , O(660F3A,40,_,_,_,_,_,_ ), 0 , 8 , 0 , 4220 , 8 , 12 ), // #152
INST(Emms , X86Op , O(000F00,77,_,_,_,_,_,_ ), 0 , 4 , 0 , 748 , 53 , 44 ), // #153
INST(Enqcmd , X86EnqcmdMovdir64b , O(F20F38,F8,_,_,_,_,_,_ ), 0 , 28 , 0 , 563 , 54 , 45 ), // #154
INST(Enqcmds , X86EnqcmdMovdir64b , O(F30F38,F8,_,_,_,_,_,_ ), 0 , 7 , 0 , 570 , 54 , 45 ), // #155
- INST(Enter , X86Enter , O(000000,C8,_,_,_,_,_,_ ), 0 , 0 , 0 , 2856 , 55 , 0 ), // #156
- INST(Extractps , ExtExtract , O(660F3A,17,_,_,_,_,_,_ ), 0 , 8 , 0 , 4222 , 56 , 12 ), // #157
- INST(Extrq , ExtExtrq , O(660F00,79,_,_,_,_,_,_ ), O(660F00,78,0,_,_,_,_,_ ), 3 , 7 , 7290 , 57 , 46 ), // #158
+ INST(Enter , X86Enter , O(000000,C8,_,_,_,_,_,_ ), 0 , 0 , 0 , 2925 , 55 , 0 ), // #156
+ INST(Extractps , ExtExtract , O(660F3A,17,_,_,_,_,_,_ ), 0 , 8 , 0 , 4410 , 56 , 12 ), // #157
+ INST(Extrq , ExtExtrq , O(660F00,79,_,_,_,_,_,_ ), O(660F00,78,0,_,_,_,_,_ ), 3 , 7 , 7506 , 57 , 46 ), // #158
INST(F2xm1 , FpuOp , O_FPU(00,D9F0,_) , 0 , 31 , 0 , 578 , 30 , 0 ), // #159
INST(Fabs , FpuOp , O_FPU(00,D9E1,_) , 0 , 31 , 0 , 584 , 30 , 0 ), // #160
- INST(Fadd , FpuArith , O_FPU(00,C0C0,0) , 0 , 32 , 0 , 2067 , 58 , 0 ), // #161
+ INST(Fadd , FpuArith , O_FPU(00,C0C0,0) , 0 , 32 , 0 , 2073 , 58 , 0 ), // #161
INST(Faddp , FpuRDef , O_FPU(00,DEC0,_) , 0 , 33 , 0 , 589 , 59 , 0 ), // #162
INST(Fbld , X86M_Only , O_FPU(00,00DF,4) , 0 , 34 , 0 , 595 , 60 , 0 ), // #163
INST(Fbstp , X86M_Only , O_FPU(00,00DF,6) , 0 , 35 , 0 , 600 , 60 , 0 ), // #164
@@ -306,7 +306,7 @@ const InstDB::InstInfo InstDB::_instInfoTable[] = {
INST(Fldln2 , FpuOp , O_FPU(00,D9ED,_) , 0 , 31 , 0 , 890 , 30 , 0 ), // #209
INST(Fldpi , FpuOp , O_FPU(00,D9EB,_) , 0 , 31 , 0 , 897 , 30 , 0 ), // #210
INST(Fldz , FpuOp , O_FPU(00,D9EE,_) , 0 , 31 , 0 , 903 , 30 , 0 ), // #211
- INST(Fmul , FpuArith , O_FPU(00,C8C8,1) , 0 , 51 , 0 , 2109 , 58 , 0 ), // #212
+ INST(Fmul , FpuArith , O_FPU(00,C8C8,1) , 0 , 51 , 0 , 2115 , 58 , 0 ), // #212
INST(Fmulp , FpuRDef , O_FPU(00,DEC8,_) , 0 , 33 , 0 , 908 , 59 , 0 ), // #213
INST(Fnclex , FpuOp , O_FPU(00,DBE2,_) , 0 , 38 , 0 , 914 , 30 , 0 ), // #214
INST(Fninit , FpuOp , O_FPU(00,DBE3,_) , 0 , 38 , 0 , 921 , 30 , 0 ), // #215
@@ -331,9 +331,9 @@ const InstDB::InstInfo InstDB::_instInfoTable[] = {
INST(Fstenv , X86M_Only , O_FPU(9B,00D9,6) , 0 , 52 , 0 , 1045 , 31 , 0 ), // #234
INST(Fstp , FpuFldFst , O_FPU(00,00D9,3) , O(000000,DB,7,_,_,_,_,_ ), 47 , 13 , 1052 , 65 , 0 ), // #235
INST(Fstsw , FpuStsw , O_FPU(9B,00DD,7) , O_FPU(9B,DFE0,_) , 53 , 14 , 1057 , 67 , 0 ), // #236
- INST(Fsub , FpuArith , O_FPU(00,E0E8,4) , 0 , 54 , 0 , 2187 , 58 , 0 ), // #237
+ INST(Fsub , FpuArith , O_FPU(00,E0E8,4) , 0 , 54 , 0 , 2193 , 58 , 0 ), // #237
INST(Fsubp , FpuRDef , O_FPU(00,DEE8,_) , 0 , 33 , 0 , 1063 , 59 , 0 ), // #238
- INST(Fsubr , FpuArith , O_FPU(00,E8E0,5) , 0 , 55 , 0 , 2193 , 58 , 0 ), // #239
+ INST(Fsubr , FpuArith , O_FPU(00,E8E0,5) , 0 , 55 , 0 , 2199 , 58 , 0 ), // #239
INST(Fsubrp , FpuRDef , O_FPU(00,DEE0,_) , 0 , 33 , 0 , 1069 , 59 , 0 ), // #240
INST(Ftst , FpuOp , O_FPU(00,D9E4,_) , 0 , 31 , 0 , 1076 , 30 , 0 ), // #241
INST(Fucom , FpuRDef , O_FPU(00,DDE0,_) , 0 , 44 , 0 , 1081 , 59 , 0 ), // #242
@@ -352,25 +352,25 @@ const InstDB::InstInfo InstDB::_instInfoTable[] = {
INST(Fyl2x , FpuOp , O_FPU(00,D9F1,_) , 0 , 31 , 0 , 1175 , 30 , 0 ), // #255
INST(Fyl2xp1 , FpuOp , O_FPU(00,D9F9,_) , 0 , 31 , 0 , 1181 , 30 , 0 ), // #256
INST(Getsec , X86Op , O(000F00,37,_,_,_,_,_,_ ), 0 , 4 , 0 , 1189 , 30 , 50 ), // #257
- INST(Gf2p8affineinvqb , ExtRmi , O(660F3A,CF,_,_,_,_,_,_ ), 0 , 8 , 0 , 5577 , 8 , 51 ), // #258
- INST(Gf2p8affineqb , ExtRmi , O(660F3A,CE,_,_,_,_,_,_ ), 0 , 8 , 0 , 5595 , 8 , 51 ), // #259
- INST(Gf2p8mulb , ExtRm , O(660F38,CF,_,_,_,_,_,_ ), 0 , 2 , 0 , 5610 , 5 , 51 ), // #260
- INST(Haddpd , ExtRm , O(660F00,7C,_,_,_,_,_,_ ), 0 , 3 , 0 , 5621 , 5 , 6 ), // #261
- INST(Haddps , ExtRm , O(F20F00,7C,_,_,_,_,_,_ ), 0 , 5 , 0 , 5629 , 5 , 6 ), // #262
+ INST(Gf2p8affineinvqb , ExtRmi , O(660F3A,CF,_,_,_,_,_,_ ), 0 , 8 , 0 , 5765 , 8 , 51 ), // #258
+ INST(Gf2p8affineqb , ExtRmi , O(660F3A,CE,_,_,_,_,_,_ ), 0 , 8 , 0 , 5783 , 8 , 51 ), // #259
+ INST(Gf2p8mulb , ExtRm , O(660F38,CF,_,_,_,_,_,_ ), 0 , 2 , 0 , 5798 , 5 , 51 ), // #260
+ INST(Haddpd , ExtRm , O(660F00,7C,_,_,_,_,_,_ ), 0 , 3 , 0 , 5809 , 5 , 6 ), // #261
+ INST(Haddps , ExtRm , O(F20F00,7C,_,_,_,_,_,_ ), 0 , 5 , 0 , 5817 , 5 , 6 ), // #262
INST(Hlt , X86Op , O(000000,F4,_,_,_,_,_,_ ), 0 , 0 , 0 , 1196 , 30 , 0 ), // #263
- INST(Hsubpd , ExtRm , O(660F00,7D,_,_,_,_,_,_ ), 0 , 3 , 0 , 5637 , 5 , 6 ), // #264
- INST(Hsubps , ExtRm , O(F20F00,7D,_,_,_,_,_,_ ), 0 , 5 , 0 , 5645 , 5 , 6 ), // #265
+ INST(Hsubpd , ExtRm , O(660F00,7D,_,_,_,_,_,_ ), 0 , 3 , 0 , 5825 , 5 , 6 ), // #264
+ INST(Hsubps , ExtRm , O(F20F00,7D,_,_,_,_,_,_ ), 0 , 5 , 0 , 5833 , 5 , 6 ), // #265
INST(Idiv , X86M_GPB_MulDiv , O(000000,F6,7,_,x,_,_,_ ), 0 , 25 , 0 , 779 , 52 , 1 ), // #266
INST(Imul , X86Imul , O(000000,F6,5,_,x,_,_,_ ), 0 , 58 , 0 , 797 , 70 , 1 ), // #267
- INST(In , X86In , O(000000,EC,_,_,_,_,_,_ ), O(000000,E4,_,_,_,_,_,_ ), 0 , 15 , 10076, 71 , 0 ), // #268
+ INST(In , X86In , O(000000,EC,_,_,_,_,_,_ ), O(000000,E4,_,_,_,_,_,_ ), 0 , 15 , 10292, 71 , 0 ), // #268
INST(Inc , X86IncDec , O(000000,FE,0,_,x,_,_,_ ), O(000000,40,_,_,x,_,_,_ ), 0 , 16 , 1200 , 51 , 43 ), // #269
- INST(Ins , X86Ins , O(000000,6C,_,_,_,_,_,_ ), 0 , 0 , 0 , 1857 , 72 , 0 ), // #270
- INST(Insertps , ExtRmi , O(660F3A,21,_,_,_,_,_,_ ), 0 , 8 , 0 , 5781 , 36 , 12 ), // #271
+ INST(Ins , X86Ins , O(000000,6C,_,_,_,_,_,_ ), 0 , 0 , 0 , 1867 , 72 , 0 ), // #270
+ INST(Insertps , ExtRmi , O(660F3A,21,_,_,_,_,_,_ ), 0 , 8 , 0 , 5969 , 36 , 12 ), // #271
INST(Insertq , ExtInsertq , O(F20F00,79,_,_,_,_,_,_ ), O(F20F00,78,_,_,_,_,_,_ ), 5 , 17 , 1204 , 73 , 46 ), // #272
INST(Int , X86Int , O(000000,CD,_,_,_,_,_,_ ), 0 , 0 , 0 , 992 , 74 , 0 ), // #273
INST(Int3 , X86Op , O(000000,CC,_,_,_,_,_,_ ), 0 , 0 , 0 , 1212 , 30 , 0 ), // #274
INST(Into , X86Op , O(000000,CE,_,_,_,_,_,_ ), 0 , 0 , 0 , 1217 , 75 , 52 ), // #275
- INST(Invd , X86Op , O(000F00,08,_,_,_,_,_,_ ), 0 , 4 , 0 , 10031, 30 , 41 ), // #276
+ INST(Invd , X86Op , O(000F00,08,_,_,_,_,_,_ ), 0 , 4 , 0 , 10247, 30 , 41 ), // #276
INST(Invept , X86Rm_NoSize , O(660F38,80,_,_,_,_,_,_ ), 0 , 2 , 0 , 1222 , 76 , 53 ), // #277
INST(Invlpg , X86M_Only , O(000F00,01,7,_,_,_,_,_ ), 0 , 22 , 0 , 1229 , 31 , 41 ), // #278
INST(Invlpga , X86Op_xAddr , O(000F01,DF,_,_,_,_,_,_ ), 0 , 21 , 0 , 1236 , 77 , 22 ), // #279
@@ -425,8 +425,8 @@ const InstDB::InstInfo InstDB::_instInfoTable[] = {
INST(Kandq , VexRvm , V(000F00,41,_,1,1,_,_,_ ), 0 , 61 , 0 , 1471 , 83 , 62 ), // #328
INST(Kandw , VexRvm , V(000F00,41,_,1,0,_,_,_ ), 0 , 62 , 0 , 1477 , 83 , 63 ), // #329
INST(Kmovb , VexKmov , V(660F00,90,_,0,0,_,_,_ ), V(660F00,92,_,0,0,_,_,_ ), 63 , 36 , 1483 , 84 , 61 ), // #330
- INST(Kmovd , VexKmov , V(660F00,90,_,0,1,_,_,_ ), V(F20F00,92,_,0,0,_,_,_ ), 64 , 37 , 7770 , 85 , 62 ), // #331
- INST(Kmovq , VexKmov , V(000F00,90,_,0,1,_,_,_ ), V(F20F00,92,_,0,1,_,_,_ ), 65 , 38 , 7781 , 86 , 62 ), // #332
+ INST(Kmovd , VexKmov , V(660F00,90,_,0,1,_,_,_ ), V(F20F00,92,_,0,0,_,_,_ ), 64 , 37 , 7986 , 85 , 62 ), // #331
+ INST(Kmovq , VexKmov , V(000F00,90,_,0,1,_,_,_ ), V(F20F00,92,_,0,1,_,_,_ ), 65 , 38 , 7997 , 86 , 62 ), // #332
INST(Kmovw , VexKmov , V(000F00,90,_,0,0,_,_,_ ), V(000F00,92,_,0,0,_,_,_ ), 66 , 39 , 1489 , 87 , 63 ), // #333
INST(Knotb , VexRm , V(660F00,44,_,0,0,_,_,_ ), 0 , 63 , 0 , 1495 , 88 , 61 ), // #334
INST(Knotd , VexRm , V(660F00,44,_,0,1,_,_,_ ), 0 , 64 , 0 , 1501 , 88 , 62 ), // #335
@@ -465,1139 +465,1166 @@ const InstDB::InstInfo InstDB::_instInfoTable[] = {
INST(Kxorw , VexRvm , V(000F00,47,_,1,0,_,_,_ ), 0 , 62 , 0 , 1748 , 83 , 63 ), // #368
INST(Lahf , X86Op , O(000000,9F,_,_,_,_,_,_ ), 0 , 0 , 0 , 1754 , 90 , 67 ), // #369
INST(Lar , X86Rm , O(000F00,02,_,_,_,_,_,_ ), 0 , 4 , 0 , 1759 , 91 , 10 ), // #370
- INST(Lddqu , ExtRm , O(F20F00,F0,_,_,_,_,_,_ ), 0 , 5 , 0 , 5791 , 92 , 6 ), // #371
- INST(Ldmxcsr , X86M_Only , O(000F00,AE,2,_,_,_,_,_ ), 0 , 69 , 0 , 5798 , 93 , 5 ), // #372
+ INST(Lddqu , ExtRm , O(F20F00,F0,_,_,_,_,_,_ ), 0 , 5 , 0 , 5979 , 92 , 6 ), // #371
+ INST(Ldmxcsr , X86M_Only , O(000F00,AE,2,_,_,_,_,_ ), 0 , 69 , 0 , 5986 , 93 , 5 ), // #372
INST(Lds , X86Rm , O(000000,C5,_,_,_,_,_,_ ), 0 , 0 , 0 , 1763 , 94 , 0 ), // #373
- INST(Lea , X86Lea , O(000000,8D,_,_,x,_,_,_ ), 0 , 0 , 0 , 1767 , 95 , 0 ), // #374
- INST(Leave , X86Op , O(000000,C9,_,_,_,_,_,_ ), 0 , 0 , 0 , 1771 , 30 , 0 ), // #375
- INST(Les , X86Rm , O(000000,C4,_,_,_,_,_,_ ), 0 , 0 , 0 , 1777 , 94 , 0 ), // #376
- INST(Lfence , X86Fence , O(000F00,AE,5,_,_,_,_,_ ), 0 , 70 , 0 , 1781 , 30 , 4 ), // #377
- INST(Lfs , X86Rm , O(000F00,B4,_,_,_,_,_,_ ), 0 , 4 , 0 , 1788 , 96 , 0 ), // #378
- INST(Lgdt , X86M_Only , O(000F00,01,2,_,_,_,_,_ ), 0 , 69 , 0 , 1792 , 31 , 0 ), // #379
- INST(Lgs , X86Rm , O(000F00,B5,_,_,_,_,_,_ ), 0 , 4 , 0 , 1797 , 96 , 0 ), // #380
- INST(Lidt , X86M_Only , O(000F00,01,3,_,_,_,_,_ ), 0 , 71 , 0 , 1801 , 31 , 0 ), // #381
- INST(Lldt , X86M_NoSize , O(000F00,00,2,_,_,_,_,_ ), 0 , 69 , 0 , 1806 , 97 , 0 ), // #382
- INST(Llwpcb , VexR_Wx , V(XOP_M9,12,0,0,x,_,_,_ ), 0 , 72 , 0 , 1811 , 98 , 68 ), // #383
- INST(Lmsw , X86M_NoSize , O(000F00,01,6,_,_,_,_,_ ), 0 , 73 , 0 , 1818 , 97 , 0 ), // #384
- INST(Lods , X86StrRm , O(000000,AC,_,_,_,_,_,_ ), 0 , 0 , 0 , 1823 , 99 , 69 ), // #385
- INST(Loop , X86JecxzLoop , 0 , O(000000,E2,_,_,_,_,_,_ ), 0 , 40 , 1828 , 100, 0 ), // #386
- INST(Loope , X86JecxzLoop , 0 , O(000000,E1,_,_,_,_,_,_ ), 0 , 41 , 1833 , 100, 56 ), // #387
- INST(Loopne , X86JecxzLoop , 0 , O(000000,E0,_,_,_,_,_,_ ), 0 , 42 , 1839 , 100, 56 ), // #388
- INST(Lsl , X86Rm , O(000F00,03,_,_,_,_,_,_ ), 0 , 4 , 0 , 1846 , 101, 10 ), // #389
- INST(Lss , X86Rm , O(000F00,B2,_,_,_,_,_,_ ), 0 , 4 , 0 , 6289 , 96 , 0 ), // #390
- INST(Ltr , X86M_NoSize , O(000F00,00,3,_,_,_,_,_ ), 0 , 71 , 0 , 1850 , 97 , 0 ), // #391
- INST(Lwpins , VexVmi4_Wx , V(XOP_MA,12,0,0,x,_,_,_ ), 0 , 74 , 0 , 1854 , 102, 68 ), // #392
- INST(Lwpval , VexVmi4_Wx , V(XOP_MA,12,1,0,x,_,_,_ ), 0 , 75 , 0 , 1861 , 102, 68 ), // #393
- INST(Lzcnt , X86Rm_Raw66H , O(F30F00,BD,_,_,x,_,_,_ ), 0 , 6 , 0 , 1868 , 22 , 70 ), // #394
- INST(Maskmovdqu , ExtRm_ZDI , O(660F00,57,_,_,_,_,_,_ ), 0 , 3 , 0 , 5807 , 103, 4 ), // #395
- INST(Maskmovq , ExtRm_ZDI , O(000F00,F7,_,_,_,_,_,_ ), 0 , 4 , 0 , 7778 , 104, 71 ), // #396
- INST(Maxpd , ExtRm , O(660F00,5F,_,_,_,_,_,_ ), 0 , 3 , 0 , 5841 , 5 , 4 ), // #397
- INST(Maxps , ExtRm , O(000F00,5F,_,_,_,_,_,_ ), 0 , 4 , 0 , 5848 , 5 , 5 ), // #398
- INST(Maxsd , ExtRm , O(F20F00,5F,_,_,_,_,_,_ ), 0 , 5 , 0 , 7797 , 6 , 4 ), // #399
- INST(Maxss , ExtRm , O(F30F00,5F,_,_,_,_,_,_ ), 0 , 6 , 0 , 5862 , 7 , 5 ), // #400
- INST(Mfence , X86Fence , O(000F00,AE,6,_,_,_,_,_ ), 0 , 73 , 0 , 1874 , 30 , 4 ), // #401
- INST(Minpd , ExtRm , O(660F00,5D,_,_,_,_,_,_ ), 0 , 3 , 0 , 5891 , 5 , 4 ), // #402
- INST(Minps , ExtRm , O(000F00,5D,_,_,_,_,_,_ ), 0 , 4 , 0 , 5898 , 5 , 5 ), // #403
- INST(Minsd , ExtRm , O(F20F00,5D,_,_,_,_,_,_ ), 0 , 5 , 0 , 7861 , 6 , 4 ), // #404
- INST(Minss , ExtRm , O(F30F00,5D,_,_,_,_,_,_ ), 0 , 6 , 0 , 5912 , 7 , 5 ), // #405
- INST(Monitor , X86Op , O(000F01,C8,_,_,_,_,_,_ ), 0 , 21 , 0 , 1881 , 105, 72 ), // #406
- INST(Monitorx , X86Op , O(000F01,FA,_,_,_,_,_,_ ), 0 , 21 , 0 , 1889 , 105, 73 ), // #407
- INST(Mov , X86Mov , 0 , 0 , 0 , 0 , 138 , 106, 0 ), // #408
- INST(Movapd , ExtMov , O(660F00,28,_,_,_,_,_,_ ), O(660F00,29,_,_,_,_,_,_ ), 3 , 43 , 5943 , 107, 4 ), // #409
- INST(Movaps , ExtMov , O(000F00,28,_,_,_,_,_,_ ), O(000F00,29,_,_,_,_,_,_ ), 4 , 44 , 5951 , 107, 5 ), // #410
- INST(Movbe , ExtMovbe , O(000F38,F0,_,_,x,_,_,_ ), O(000F38,F1,_,_,x,_,_,_ ), 76 , 45 , 626 , 108, 74 ), // #411
- INST(Movd , ExtMovd , O(000F00,6E,_,_,_,_,_,_ ), O(000F00,7E,_,_,_,_,_,_ ), 4 , 46 , 7771 , 109, 75 ), // #412
- INST(Movddup , ExtMov , O(F20F00,12,_,_,_,_,_,_ ), 0 , 5 , 0 , 5965 , 6 , 6 ), // #413
- INST(Movdir64b , X86EnqcmdMovdir64b , O(660F38,F8,_,_,_,_,_,_ ), 0 , 2 , 0 , 1898 , 110, 76 ), // #414
- INST(Movdiri , X86MovntiMovdiri , O(000F38,F9,_,_,_,_,_,_ ), 0 , 76 , 0 , 1908 , 111, 77 ), // #415
- INST(Movdq2q , ExtMov , O(F20F00,D6,_,_,_,_,_,_ ), 0 , 5 , 0 , 1916 , 112, 4 ), // #416
- INST(Movdqa , ExtMov , O(660F00,6F,_,_,_,_,_,_ ), O(660F00,7F,_,_,_,_,_,_ ), 3 , 47 , 5974 , 107, 4 ), // #417
- INST(Movdqu , ExtMov , O(F30F00,6F,_,_,_,_,_,_ ), O(F30F00,7F,_,_,_,_,_,_ ), 6 , 48 , 5811 , 107, 4 ), // #418
- INST(Movhlps , ExtMov , O(000F00,12,_,_,_,_,_,_ ), 0 , 4 , 0 , 6049 , 113, 5 ), // #419
- INST(Movhpd , ExtMov , O(660F00,16,_,_,_,_,_,_ ), O(660F00,17,_,_,_,_,_,_ ), 3 , 49 , 6058 , 114, 4 ), // #420
- INST(Movhps , ExtMov , O(000F00,16,_,_,_,_,_,_ ), O(000F00,17,_,_,_,_,_,_ ), 4 , 50 , 6066 , 114, 5 ), // #421
- INST(Movlhps , ExtMov , O(000F00,16,_,_,_,_,_,_ ), 0 , 4 , 0 , 6074 , 113, 5 ), // #422
- INST(Movlpd , ExtMov , O(660F00,12,_,_,_,_,_,_ ), O(660F00,13,_,_,_,_,_,_ ), 3 , 51 , 6083 , 114, 4 ), // #423
- INST(Movlps , ExtMov , O(000F00,12,_,_,_,_,_,_ ), O(000F00,13,_,_,_,_,_,_ ), 4 , 52 , 6091 , 114, 5 ), // #424
- INST(Movmskpd , ExtMov , O(660F00,50,_,_,_,_,_,_ ), 0 , 3 , 0 , 6099 , 115, 4 ), // #425
- INST(Movmskps , ExtMov , O(000F00,50,_,_,_,_,_,_ ), 0 , 4 , 0 , 6109 , 115, 5 ), // #426
- INST(Movntdq , ExtMov , 0 , O(660F00,E7,_,_,_,_,_,_ ), 0 , 53 , 6119 , 116, 4 ), // #427
- INST(Movntdqa , ExtMov , O(660F38,2A,_,_,_,_,_,_ ), 0 , 2 , 0 , 6128 , 92 , 12 ), // #428
- INST(Movnti , X86MovntiMovdiri , O(000F00,C3,_,_,x,_,_,_ ), 0 , 4 , 0 , 1924 , 111, 4 ), // #429
- INST(Movntpd , ExtMov , 0 , O(660F00,2B,_,_,_,_,_,_ ), 0 , 54 , 6138 , 116, 4 ), // #430
- INST(Movntps , ExtMov , 0 , O(000F00,2B,_,_,_,_,_,_ ), 0 , 55 , 6147 , 116, 5 ), // #431
- INST(Movntq , ExtMov , 0 , O(000F00,E7,_,_,_,_,_,_ ), 0 , 56 , 1931 , 117, 71 ), // #432
- INST(Movntsd , ExtMov , 0 , O(F20F00,2B,_,_,_,_,_,_ ), 0 , 57 , 1938 , 118, 46 ), // #433
- INST(Movntss , ExtMov , 0 , O(F30F00,2B,_,_,_,_,_,_ ), 0 , 58 , 1946 , 119, 46 ), // #434
- INST(Movq , ExtMovq , O(000F00,6E,_,_,x,_,_,_ ), O(000F00,7E,_,_,x,_,_,_ ), 4 , 59 , 7782 , 120, 75 ), // #435
- INST(Movq2dq , ExtRm , O(F30F00,D6,_,_,_,_,_,_ ), 0 , 6 , 0 , 1954 , 121, 4 ), // #436
- INST(Movs , X86StrMm , O(000000,A4,_,_,_,_,_,_ ), 0 , 0 , 0 , 425 , 122, 69 ), // #437
- INST(Movsd , ExtMov , O(F20F00,10,_,_,_,_,_,_ ), O(F20F00,11,_,_,_,_,_,_ ), 5 , 60 , 6162 , 123, 4 ), // #438
- INST(Movshdup , ExtRm , O(F30F00,16,_,_,_,_,_,_ ), 0 , 6 , 0 , 6169 , 5 , 6 ), // #439
- INST(Movsldup , ExtRm , O(F30F00,12,_,_,_,_,_,_ ), 0 , 6 , 0 , 6179 , 5 , 6 ), // #440
- INST(Movss , ExtMov , O(F30F00,10,_,_,_,_,_,_ ), O(F30F00,11,_,_,_,_,_,_ ), 6 , 61 , 6189 , 124, 5 ), // #441
- INST(Movsx , X86MovsxMovzx , O(000F00,BE,_,_,x,_,_,_ ), 0 , 4 , 0 , 1962 , 125, 0 ), // #442
- INST(Movsxd , X86Rm , O(000000,63,_,_,x,_,_,_ ), 0 , 0 , 0 , 1968 , 126, 0 ), // #443
- INST(Movupd , ExtMov , O(660F00,10,_,_,_,_,_,_ ), O(660F00,11,_,_,_,_,_,_ ), 3 , 62 , 6196 , 107, 4 ), // #444
- INST(Movups , ExtMov , O(000F00,10,_,_,_,_,_,_ ), O(000F00,11,_,_,_,_,_,_ ), 4 , 63 , 6204 , 107, 5 ), // #445
- INST(Movzx , X86MovsxMovzx , O(000F00,B6,_,_,x,_,_,_ ), 0 , 4 , 0 , 1975 , 125, 0 ), // #446
- INST(Mpsadbw , ExtRmi , O(660F3A,42,_,_,_,_,_,_ ), 0 , 8 , 0 , 6212 , 8 , 12 ), // #447
- INST(Mul , X86M_GPB_MulDiv , O(000000,F6,4,_,x,_,_,_ ), 0 , 9 , 0 , 798 , 52 , 1 ), // #448
- INST(Mulpd , ExtRm , O(660F00,59,_,_,_,_,_,_ ), 0 , 3 , 0 , 6266 , 5 , 4 ), // #449
- INST(Mulps , ExtRm , O(000F00,59,_,_,_,_,_,_ ), 0 , 4 , 0 , 6273 , 5 , 5 ), // #450
- INST(Mulsd , ExtRm , O(F20F00,59,_,_,_,_,_,_ ), 0 , 5 , 0 , 6280 , 6 , 4 ), // #451
- INST(Mulss , ExtRm , O(F30F00,59,_,_,_,_,_,_ ), 0 , 6 , 0 , 6287 , 7 , 5 ), // #452
- INST(Mulx , VexRvm_ZDX_Wx , V(F20F38,F6,_,0,x,_,_,_ ), 0 , 77 , 0 , 1981 , 127, 78 ), // #453
- INST(Mwait , X86Op , O(000F01,C9,_,_,_,_,_,_ ), 0 , 21 , 0 , 1986 , 128, 72 ), // #454
- INST(Mwaitx , X86Op , O(000F01,FB,_,_,_,_,_,_ ), 0 , 21 , 0 , 1992 , 129, 73 ), // #455
- INST(Neg , X86M_GPB , O(000000,F6,3,_,x,_,_,_ ), 0 , 78 , 0 , 1999 , 130, 1 ), // #456
- INST(Nop , X86M_Nop , O(000000,90,_,_,_,_,_,_ ), 0 , 0 , 0 , 929 , 131, 0 ), // #457
- INST(Not , X86M_GPB , O(000000,F6,2,_,x,_,_,_ ), 0 , 1 , 0 , 2003 , 130, 0 ), // #458
- INST(Or , X86Arith , O(000000,08,1,_,x,_,_,_ ), 0 , 29 , 0 , 1138 , 132, 1 ), // #459
- INST(Orpd , ExtRm , O(660F00,56,_,_,_,_,_,_ ), 0 , 3 , 0 , 9988 , 11 , 4 ), // #460
- INST(Orps , ExtRm , O(000F00,56,_,_,_,_,_,_ ), 0 , 4 , 0 , 9995 , 11 , 5 ), // #461
- INST(Out , X86Out , O(000000,EE,_,_,_,_,_,_ ), O(000000,E6,_,_,_,_,_,_ ), 0 , 64 , 2007 , 133, 0 ), // #462
- INST(Outs , X86Outs , O(000000,6E,_,_,_,_,_,_ ), 0 , 0 , 0 , 2011 , 134, 0 ), // #463
- INST(Pabsb , ExtRm_P , O(000F38,1C,_,_,_,_,_,_ ), 0 , 76 , 0 , 6341 , 135, 79 ), // #464
- INST(Pabsd , ExtRm_P , O(000F38,1E,_,_,_,_,_,_ ), 0 , 76 , 0 , 6348 , 135, 79 ), // #465
- INST(Pabsw , ExtRm_P , O(000F38,1D,_,_,_,_,_,_ ), 0 , 76 , 0 , 6362 , 135, 79 ), // #466
- INST(Packssdw , ExtRm_P , O(000F00,6B,_,_,_,_,_,_ ), 0 , 4 , 0 , 6369 , 135, 75 ), // #467
- INST(Packsswb , ExtRm_P , O(000F00,63,_,_,_,_,_,_ ), 0 , 4 , 0 , 6379 , 135, 75 ), // #468
- INST(Packusdw , ExtRm , O(660F38,2B,_,_,_,_,_,_ ), 0 , 2 , 0 , 6389 , 5 , 12 ), // #469
- INST(Packuswb , ExtRm_P , O(000F00,67,_,_,_,_,_,_ ), 0 , 4 , 0 , 6399 , 135, 75 ), // #470
- INST(Paddb , ExtRm_P , O(000F00,FC,_,_,_,_,_,_ ), 0 , 4 , 0 , 6409 , 135, 75 ), // #471
- INST(Paddd , ExtRm_P , O(000F00,FE,_,_,_,_,_,_ ), 0 , 4 , 0 , 6416 , 135, 75 ), // #472
- INST(Paddq , ExtRm_P , O(000F00,D4,_,_,_,_,_,_ ), 0 , 4 , 0 , 6423 , 135, 4 ), // #473
- INST(Paddsb , ExtRm_P , O(000F00,EC,_,_,_,_,_,_ ), 0 , 4 , 0 , 6430 , 135, 75 ), // #474
- INST(Paddsw , ExtRm_P , O(000F00,ED,_,_,_,_,_,_ ), 0 , 4 , 0 , 6438 , 135, 75 ), // #475
- INST(Paddusb , ExtRm_P , O(000F00,DC,_,_,_,_,_,_ ), 0 , 4 , 0 , 6446 , 135, 75 ), // #476
- INST(Paddusw , ExtRm_P , O(000F00,DD,_,_,_,_,_,_ ), 0 , 4 , 0 , 6455 , 135, 75 ), // #477
- INST(Paddw , ExtRm_P , O(000F00,FD,_,_,_,_,_,_ ), 0 , 4 , 0 , 6464 , 135, 75 ), // #478
- INST(Palignr , ExtRmi_P , O(000F3A,0F,_,_,_,_,_,_ ), 0 , 79 , 0 , 6471 , 136, 6 ), // #479
- INST(Pand , ExtRm_P , O(000F00,DB,_,_,_,_,_,_ ), 0 , 4 , 0 , 6480 , 137, 75 ), // #480
- INST(Pandn , ExtRm_P , O(000F00,DF,_,_,_,_,_,_ ), 0 , 4 , 0 , 6493 , 138, 75 ), // #481
- INST(Pause , X86Op , O(F30000,90,_,_,_,_,_,_ ), 0 , 80 , 0 , 2016 , 30 , 0 ), // #482
- INST(Pavgb , ExtRm_P , O(000F00,E0,_,_,_,_,_,_ ), 0 , 4 , 0 , 6523 , 135, 80 ), // #483
- INST(Pavgusb , Ext3dNow , O(000F0F,BF,_,_,_,_,_,_ ), 0 , 81 , 0 , 2022 , 139, 48 ), // #484
- INST(Pavgw , ExtRm_P , O(000F00,E3,_,_,_,_,_,_ ), 0 , 4 , 0 , 6530 , 135, 80 ), // #485
- INST(Pblendvb , ExtRm_XMM0 , O(660F38,10,_,_,_,_,_,_ ), 0 , 2 , 0 , 6546 , 15 , 12 ), // #486
- INST(Pblendw , ExtRmi , O(660F3A,0E,_,_,_,_,_,_ ), 0 , 8 , 0 , 6556 , 8 , 12 ), // #487
- INST(Pclmulqdq , ExtRmi , O(660F3A,44,_,_,_,_,_,_ ), 0 , 8 , 0 , 6649 , 8 , 81 ), // #488
- INST(Pcmpeqb , ExtRm_P , O(000F00,74,_,_,_,_,_,_ ), 0 , 4 , 0 , 6681 , 138, 75 ), // #489
- INST(Pcmpeqd , ExtRm_P , O(000F00,76,_,_,_,_,_,_ ), 0 , 4 , 0 , 6690 , 138, 75 ), // #490
- INST(Pcmpeqq , ExtRm , O(660F38,29,_,_,_,_,_,_ ), 0 , 2 , 0 , 6699 , 140, 12 ), // #491
- INST(Pcmpeqw , ExtRm_P , O(000F00,75,_,_,_,_,_,_ ), 0 , 4 , 0 , 6708 , 138, 75 ), // #492
- INST(Pcmpestri , ExtRmi , O(660F3A,61,_,_,_,_,_,_ ), 0 , 8 , 0 , 6717 , 141, 82 ), // #493
- INST(Pcmpestrm , ExtRmi , O(660F3A,60,_,_,_,_,_,_ ), 0 , 8 , 0 , 6728 , 142, 82 ), // #494
- INST(Pcmpgtb , ExtRm_P , O(000F00,64,_,_,_,_,_,_ ), 0 , 4 , 0 , 6739 , 138, 75 ), // #495
- INST(Pcmpgtd , ExtRm_P , O(000F00,66,_,_,_,_,_,_ ), 0 , 4 , 0 , 6748 , 138, 75 ), // #496
- INST(Pcmpgtq , ExtRm , O(660F38,37,_,_,_,_,_,_ ), 0 , 2 , 0 , 6757 , 140, 42 ), // #497
- INST(Pcmpgtw , ExtRm_P , O(000F00,65,_,_,_,_,_,_ ), 0 , 4 , 0 , 6766 , 138, 75 ), // #498
- INST(Pcmpistri , ExtRmi , O(660F3A,63,_,_,_,_,_,_ ), 0 , 8 , 0 , 6775 , 143, 82 ), // #499
- INST(Pcmpistrm , ExtRmi , O(660F3A,62,_,_,_,_,_,_ ), 0 , 8 , 0 , 6786 , 144, 82 ), // #500
- INST(Pcommit , X86Op_O , O(660F00,AE,7,_,_,_,_,_ ), 0 , 23 , 0 , 2030 , 30 , 83 ), // #501
- INST(Pdep , VexRvm_Wx , V(F20F38,F5,_,0,x,_,_,_ ), 0 , 77 , 0 , 2038 , 10 , 78 ), // #502
- INST(Pext , VexRvm_Wx , V(F30F38,F5,_,0,x,_,_,_ ), 0 , 82 , 0 , 2043 , 10 , 78 ), // #503
- INST(Pextrb , ExtExtract , O(000F3A,14,_,_,_,_,_,_ ), 0 , 79 , 0 , 7273 , 145, 12 ), // #504
- INST(Pextrd , ExtExtract , O(000F3A,16,_,_,_,_,_,_ ), 0 , 79 , 0 , 7281 , 56 , 12 ), // #505
- INST(Pextrq , ExtExtract , O(000F3A,16,_,_,1,_,_,_ ), 0 , 83 , 0 , 7289 , 146, 12 ), // #506
- INST(Pextrw , ExtPextrw , O(000F00,C5,_,_,_,_,_,_ ), O(000F3A,15,_,_,_,_,_,_ ), 4 , 65 , 7297 , 147, 84 ), // #507
- INST(Pf2id , Ext3dNow , O(000F0F,1D,_,_,_,_,_,_ ), 0 , 81 , 0 , 2048 , 139, 48 ), // #508
- INST(Pf2iw , Ext3dNow , O(000F0F,1C,_,_,_,_,_,_ ), 0 , 81 , 0 , 2054 , 139, 85 ), // #509
- INST(Pfacc , Ext3dNow , O(000F0F,AE,_,_,_,_,_,_ ), 0 , 81 , 0 , 2060 , 139, 48 ), // #510
- INST(Pfadd , Ext3dNow , O(000F0F,9E,_,_,_,_,_,_ ), 0 , 81 , 0 , 2066 , 139, 48 ), // #511
- INST(Pfcmpeq , Ext3dNow , O(000F0F,B0,_,_,_,_,_,_ ), 0 , 81 , 0 , 2072 , 139, 48 ), // #512
- INST(Pfcmpge , Ext3dNow , O(000F0F,90,_,_,_,_,_,_ ), 0 , 81 , 0 , 2080 , 139, 48 ), // #513
- INST(Pfcmpgt , Ext3dNow , O(000F0F,A0,_,_,_,_,_,_ ), 0 , 81 , 0 , 2088 , 139, 48 ), // #514
- INST(Pfmax , Ext3dNow , O(000F0F,A4,_,_,_,_,_,_ ), 0 , 81 , 0 , 2096 , 139, 48 ), // #515
- INST(Pfmin , Ext3dNow , O(000F0F,94,_,_,_,_,_,_ ), 0 , 81 , 0 , 2102 , 139, 48 ), // #516
- INST(Pfmul , Ext3dNow , O(000F0F,B4,_,_,_,_,_,_ ), 0 , 81 , 0 , 2108 , 139, 48 ), // #517
- INST(Pfnacc , Ext3dNow , O(000F0F,8A,_,_,_,_,_,_ ), 0 , 81 , 0 , 2114 , 139, 85 ), // #518
- INST(Pfpnacc , Ext3dNow , O(000F0F,8E,_,_,_,_,_,_ ), 0 , 81 , 0 , 2121 , 139, 85 ), // #519
- INST(Pfrcp , Ext3dNow , O(000F0F,96,_,_,_,_,_,_ ), 0 , 81 , 0 , 2129 , 139, 48 ), // #520
- INST(Pfrcpit1 , Ext3dNow , O(000F0F,A6,_,_,_,_,_,_ ), 0 , 81 , 0 , 2135 , 139, 48 ), // #521
- INST(Pfrcpit2 , Ext3dNow , O(000F0F,B6,_,_,_,_,_,_ ), 0 , 81 , 0 , 2144 , 139, 48 ), // #522
- INST(Pfrcpv , Ext3dNow , O(000F0F,86,_,_,_,_,_,_ ), 0 , 81 , 0 , 2153 , 139, 86 ), // #523
- INST(Pfrsqit1 , Ext3dNow , O(000F0F,A7,_,_,_,_,_,_ ), 0 , 81 , 0 , 2160 , 139, 48 ), // #524
- INST(Pfrsqrt , Ext3dNow , O(000F0F,97,_,_,_,_,_,_ ), 0 , 81 , 0 , 2169 , 139, 48 ), // #525
- INST(Pfrsqrtv , Ext3dNow , O(000F0F,87,_,_,_,_,_,_ ), 0 , 81 , 0 , 2177 , 139, 86 ), // #526
- INST(Pfsub , Ext3dNow , O(000F0F,9A,_,_,_,_,_,_ ), 0 , 81 , 0 , 2186 , 139, 48 ), // #527
- INST(Pfsubr , Ext3dNow , O(000F0F,AA,_,_,_,_,_,_ ), 0 , 81 , 0 , 2192 , 139, 48 ), // #528
- INST(Phaddd , ExtRm_P , O(000F38,02,_,_,_,_,_,_ ), 0 , 76 , 0 , 7376 , 135, 79 ), // #529
- INST(Phaddsw , ExtRm_P , O(000F38,03,_,_,_,_,_,_ ), 0 , 76 , 0 , 7393 , 135, 79 ), // #530
- INST(Phaddw , ExtRm_P , O(000F38,01,_,_,_,_,_,_ ), 0 , 76 , 0 , 7462 , 135, 79 ), // #531
- INST(Phminposuw , ExtRm , O(660F38,41,_,_,_,_,_,_ ), 0 , 2 , 0 , 7488 , 5 , 12 ), // #532
- INST(Phsubd , ExtRm_P , O(000F38,06,_,_,_,_,_,_ ), 0 , 76 , 0 , 7509 , 135, 79 ), // #533
- INST(Phsubsw , ExtRm_P , O(000F38,07,_,_,_,_,_,_ ), 0 , 76 , 0 , 7526 , 135, 79 ), // #534
- INST(Phsubw , ExtRm_P , O(000F38,05,_,_,_,_,_,_ ), 0 , 76 , 0 , 7535 , 135, 79 ), // #535
- INST(Pi2fd , Ext3dNow , O(000F0F,0D,_,_,_,_,_,_ ), 0 , 81 , 0 , 2199 , 139, 48 ), // #536
- INST(Pi2fw , Ext3dNow , O(000F0F,0C,_,_,_,_,_,_ ), 0 , 81 , 0 , 2205 , 139, 85 ), // #537
- INST(Pinsrb , ExtRmi , O(660F3A,20,_,_,_,_,_,_ ), 0 , 8 , 0 , 7552 , 148, 12 ), // #538
- INST(Pinsrd , ExtRmi , O(660F3A,22,_,_,_,_,_,_ ), 0 , 8 , 0 , 7560 , 149, 12 ), // #539
- INST(Pinsrq , ExtRmi , O(660F3A,22,_,_,1,_,_,_ ), 0 , 84 , 0 , 7568 , 150, 12 ), // #540
- INST(Pinsrw , ExtRmi_P , O(000F00,C4,_,_,_,_,_,_ ), 0 , 4 , 0 , 7576 , 151, 80 ), // #541
- INST(Pmaddubsw , ExtRm_P , O(000F38,04,_,_,_,_,_,_ ), 0 , 76 , 0 , 7746 , 135, 79 ), // #542
- INST(Pmaddwd , ExtRm_P , O(000F00,F5,_,_,_,_,_,_ ), 0 , 4 , 0 , 7757 , 135, 75 ), // #543
- INST(Pmaxsb , ExtRm , O(660F38,3C,_,_,_,_,_,_ ), 0 , 2 , 0 , 7788 , 11 , 12 ), // #544
- INST(Pmaxsd , ExtRm , O(660F38,3D,_,_,_,_,_,_ ), 0 , 2 , 0 , 7796 , 11 , 12 ), // #545
- INST(Pmaxsw , ExtRm_P , O(000F00,EE,_,_,_,_,_,_ ), 0 , 4 , 0 , 7812 , 137, 80 ), // #546
- INST(Pmaxub , ExtRm_P , O(000F00,DE,_,_,_,_,_,_ ), 0 , 4 , 0 , 7820 , 137, 80 ), // #547
- INST(Pmaxud , ExtRm , O(660F38,3F,_,_,_,_,_,_ ), 0 , 2 , 0 , 7828 , 11 , 12 ), // #548
- INST(Pmaxuw , ExtRm , O(660F38,3E,_,_,_,_,_,_ ), 0 , 2 , 0 , 7844 , 11 , 12 ), // #549
- INST(Pminsb , ExtRm , O(660F38,38,_,_,_,_,_,_ ), 0 , 2 , 0 , 7852 , 11 , 12 ), // #550
- INST(Pminsd , ExtRm , O(660F38,39,_,_,_,_,_,_ ), 0 , 2 , 0 , 7860 , 11 , 12 ), // #551
- INST(Pminsw , ExtRm_P , O(000F00,EA,_,_,_,_,_,_ ), 0 , 4 , 0 , 7876 , 137, 80 ), // #552
- INST(Pminub , ExtRm_P , O(000F00,DA,_,_,_,_,_,_ ), 0 , 4 , 0 , 7884 , 137, 80 ), // #553
- INST(Pminud , ExtRm , O(660F38,3B,_,_,_,_,_,_ ), 0 , 2 , 0 , 7892 , 11 , 12 ), // #554
- INST(Pminuw , ExtRm , O(660F38,3A,_,_,_,_,_,_ ), 0 , 2 , 0 , 7908 , 11 , 12 ), // #555
- INST(Pmovmskb , ExtRm_P , O(000F00,D7,_,_,_,_,_,_ ), 0 , 4 , 0 , 7986 , 152, 80 ), // #556
- INST(Pmovsxbd , ExtRm , O(660F38,21,_,_,_,_,_,_ ), 0 , 2 , 0 , 8083 , 7 , 12 ), // #557
- INST(Pmovsxbq , ExtRm , O(660F38,22,_,_,_,_,_,_ ), 0 , 2 , 0 , 8093 , 153, 12 ), // #558
- INST(Pmovsxbw , ExtRm , O(660F38,20,_,_,_,_,_,_ ), 0 , 2 , 0 , 8103 , 6 , 12 ), // #559
- INST(Pmovsxdq , ExtRm , O(660F38,25,_,_,_,_,_,_ ), 0 , 2 , 0 , 8113 , 6 , 12 ), // #560
- INST(Pmovsxwd , ExtRm , O(660F38,23,_,_,_,_,_,_ ), 0 , 2 , 0 , 8123 , 6 , 12 ), // #561
- INST(Pmovsxwq , ExtRm , O(660F38,24,_,_,_,_,_,_ ), 0 , 2 , 0 , 8133 , 7 , 12 ), // #562
- INST(Pmovzxbd , ExtRm , O(660F38,31,_,_,_,_,_,_ ), 0 , 2 , 0 , 8220 , 7 , 12 ), // #563
- INST(Pmovzxbq , ExtRm , O(660F38,32,_,_,_,_,_,_ ), 0 , 2 , 0 , 8230 , 153, 12 ), // #564
- INST(Pmovzxbw , ExtRm , O(660F38,30,_,_,_,_,_,_ ), 0 , 2 , 0 , 8240 , 6 , 12 ), // #565
- INST(Pmovzxdq , ExtRm , O(660F38,35,_,_,_,_,_,_ ), 0 , 2 , 0 , 8250 , 6 , 12 ), // #566
- INST(Pmovzxwd , ExtRm , O(660F38,33,_,_,_,_,_,_ ), 0 , 2 , 0 , 8260 , 6 , 12 ), // #567
- INST(Pmovzxwq , ExtRm , O(660F38,34,_,_,_,_,_,_ ), 0 , 2 , 0 , 8270 , 7 , 12 ), // #568
- INST(Pmuldq , ExtRm , O(660F38,28,_,_,_,_,_,_ ), 0 , 2 , 0 , 8280 , 5 , 12 ), // #569
- INST(Pmulhrsw , ExtRm_P , O(000F38,0B,_,_,_,_,_,_ ), 0 , 76 , 0 , 8288 , 135, 79 ), // #570
- INST(Pmulhrw , Ext3dNow , O(000F0F,B7,_,_,_,_,_,_ ), 0 , 81 , 0 , 2211 , 139, 48 ), // #571
- INST(Pmulhuw , ExtRm_P , O(000F00,E4,_,_,_,_,_,_ ), 0 , 4 , 0 , 8298 , 135, 80 ), // #572
- INST(Pmulhw , ExtRm_P , O(000F00,E5,_,_,_,_,_,_ ), 0 , 4 , 0 , 8307 , 135, 75 ), // #573
- INST(Pmulld , ExtRm , O(660F38,40,_,_,_,_,_,_ ), 0 , 2 , 0 , 8315 , 5 , 12 ), // #574
- INST(Pmullw , ExtRm_P , O(000F00,D5,_,_,_,_,_,_ ), 0 , 4 , 0 , 8331 , 135, 75 ), // #575
- INST(Pmuludq , ExtRm_P , O(000F00,F4,_,_,_,_,_,_ ), 0 , 4 , 0 , 8354 , 135, 4 ), // #576
- INST(Pop , X86Pop , O(000000,8F,0,_,_,_,_,_ ), O(000000,58,_,_,_,_,_,_ ), 0 , 66 , 2219 , 154, 0 ), // #577
- INST(Popa , X86Op , O(660000,61,_,_,_,_,_,_ ), 0 , 19 , 0 , 2223 , 75 , 0 ), // #578
- INST(Popad , X86Op , O(000000,61,_,_,_,_,_,_ ), 0 , 0 , 0 , 2228 , 75 , 0 ), // #579
- INST(Popcnt , X86Rm_Raw66H , O(F30F00,B8,_,_,x,_,_,_ ), 0 , 6 , 0 , 2234 , 22 , 87 ), // #580
- INST(Popf , X86Op , O(660000,9D,_,_,_,_,_,_ ), 0 , 19 , 0 , 2241 , 30 , 88 ), // #581
- INST(Popfd , X86Op , O(000000,9D,_,_,_,_,_,_ ), 0 , 0 , 0 , 2246 , 75 , 88 ), // #582
- INST(Popfq , X86Op , O(000000,9D,_,_,_,_,_,_ ), 0 , 0 , 0 , 2252 , 155, 88 ), // #583
- INST(Por , ExtRm_P , O(000F00,EB,_,_,_,_,_,_ ), 0 , 4 , 0 , 8399 , 137, 75 ), // #584
- INST(Prefetch , X86M_Only , O(000F00,0D,0,_,_,_,_,_ ), 0 , 4 , 0 , 2258 , 31 , 48 ), // #585
- INST(Prefetchnta , X86M_Only , O(000F00,18,0,_,_,_,_,_ ), 0 , 4 , 0 , 2267 , 31 , 71 ), // #586
- INST(Prefetcht0 , X86M_Only , O(000F00,18,1,_,_,_,_,_ ), 0 , 27 , 0 , 2279 , 31 , 71 ), // #587
- INST(Prefetcht1 , X86M_Only , O(000F00,18,2,_,_,_,_,_ ), 0 , 69 , 0 , 2290 , 31 , 71 ), // #588
- INST(Prefetcht2 , X86M_Only , O(000F00,18,3,_,_,_,_,_ ), 0 , 71 , 0 , 2301 , 31 , 71 ), // #589
- INST(Prefetchw , X86M_Only , O(000F00,0D,1,_,_,_,_,_ ), 0 , 27 , 0 , 2312 , 31 , 89 ), // #590
- INST(Prefetchwt1 , X86M_Only , O(000F00,0D,2,_,_,_,_,_ ), 0 , 69 , 0 , 2322 , 31 , 90 ), // #591
- INST(Psadbw , ExtRm_P , O(000F00,F6,_,_,_,_,_,_ ), 0 , 4 , 0 , 3980 , 135, 80 ), // #592
- INST(Pshufb , ExtRm_P , O(000F38,00,_,_,_,_,_,_ ), 0 , 76 , 0 , 8725 , 135, 79 ), // #593
- INST(Pshufd , ExtRmi , O(660F00,70,_,_,_,_,_,_ ), 0 , 3 , 0 , 8746 , 8 , 4 ), // #594
- INST(Pshufhw , ExtRmi , O(F30F00,70,_,_,_,_,_,_ ), 0 , 6 , 0 , 8754 , 8 , 4 ), // #595
- INST(Pshuflw , ExtRmi , O(F20F00,70,_,_,_,_,_,_ ), 0 , 5 , 0 , 8763 , 8 , 4 ), // #596
- INST(Pshufw , ExtRmi_P , O(000F00,70,_,_,_,_,_,_ ), 0 , 4 , 0 , 2334 , 156, 71 ), // #597
- INST(Psignb , ExtRm_P , O(000F38,08,_,_,_,_,_,_ ), 0 , 76 , 0 , 8772 , 135, 79 ), // #598
- INST(Psignd , ExtRm_P , O(000F38,0A,_,_,_,_,_,_ ), 0 , 76 , 0 , 8780 , 135, 79 ), // #599
- INST(Psignw , ExtRm_P , O(000F38,09,_,_,_,_,_,_ ), 0 , 76 , 0 , 8788 , 135, 79 ), // #600
- INST(Pslld , ExtRmRi_P , O(000F00,F2,_,_,_,_,_,_ ), O(000F00,72,6,_,_,_,_,_ ), 4 , 67 , 8796 , 157, 75 ), // #601
- INST(Pslldq , ExtRmRi , 0 , O(660F00,73,7,_,_,_,_,_ ), 0 , 68 , 8803 , 158, 4 ), // #602
- INST(Psllq , ExtRmRi_P , O(000F00,F3,_,_,_,_,_,_ ), O(000F00,73,6,_,_,_,_,_ ), 4 , 69 , 8811 , 157, 75 ), // #603
- INST(Psllw , ExtRmRi_P , O(000F00,F1,_,_,_,_,_,_ ), O(000F00,71,6,_,_,_,_,_ ), 4 , 70 , 8842 , 157, 75 ), // #604
- INST(Psrad , ExtRmRi_P , O(000F00,E2,_,_,_,_,_,_ ), O(000F00,72,4,_,_,_,_,_ ), 4 , 71 , 8849 , 157, 75 ), // #605
- INST(Psraw , ExtRmRi_P , O(000F00,E1,_,_,_,_,_,_ ), O(000F00,71,4,_,_,_,_,_ ), 4 , 72 , 8887 , 157, 75 ), // #606
- INST(Psrld , ExtRmRi_P , O(000F00,D2,_,_,_,_,_,_ ), O(000F00,72,2,_,_,_,_,_ ), 4 , 73 , 8894 , 157, 75 ), // #607
- INST(Psrldq , ExtRmRi , 0 , O(660F00,73,3,_,_,_,_,_ ), 0 , 74 , 8901 , 158, 4 ), // #608
- INST(Psrlq , ExtRmRi_P , O(000F00,D3,_,_,_,_,_,_ ), O(000F00,73,2,_,_,_,_,_ ), 4 , 75 , 8909 , 157, 75 ), // #609
- INST(Psrlw , ExtRmRi_P , O(000F00,D1,_,_,_,_,_,_ ), O(000F00,71,2,_,_,_,_,_ ), 4 , 76 , 8940 , 157, 75 ), // #610
- INST(Psubb , ExtRm_P , O(000F00,F8,_,_,_,_,_,_ ), 0 , 4 , 0 , 8947 , 138, 75 ), // #611
- INST(Psubd , ExtRm_P , O(000F00,FA,_,_,_,_,_,_ ), 0 , 4 , 0 , 8954 , 138, 75 ), // #612
- INST(Psubq , ExtRm_P , O(000F00,FB,_,_,_,_,_,_ ), 0 , 4 , 0 , 8961 , 138, 4 ), // #613
- INST(Psubsb , ExtRm_P , O(000F00,E8,_,_,_,_,_,_ ), 0 , 4 , 0 , 8968 , 138, 75 ), // #614
- INST(Psubsw , ExtRm_P , O(000F00,E9,_,_,_,_,_,_ ), 0 , 4 , 0 , 8976 , 138, 75 ), // #615
- INST(Psubusb , ExtRm_P , O(000F00,D8,_,_,_,_,_,_ ), 0 , 4 , 0 , 8984 , 138, 75 ), // #616
- INST(Psubusw , ExtRm_P , O(000F00,D9,_,_,_,_,_,_ ), 0 , 4 , 0 , 8993 , 138, 75 ), // #617
- INST(Psubw , ExtRm_P , O(000F00,F9,_,_,_,_,_,_ ), 0 , 4 , 0 , 9002 , 138, 75 ), // #618
- INST(Pswapd , Ext3dNow , O(000F0F,BB,_,_,_,_,_,_ ), 0 , 81 , 0 , 2341 , 139, 85 ), // #619
- INST(Ptest , ExtRm , O(660F38,17,_,_,_,_,_,_ ), 0 , 2 , 0 , 9031 , 5 , 91 ), // #620
- INST(Punpckhbw , ExtRm_P , O(000F00,68,_,_,_,_,_,_ ), 0 , 4 , 0 , 9114 , 135, 75 ), // #621
- INST(Punpckhdq , ExtRm_P , O(000F00,6A,_,_,_,_,_,_ ), 0 , 4 , 0 , 9125 , 135, 75 ), // #622
- INST(Punpckhqdq , ExtRm , O(660F00,6D,_,_,_,_,_,_ ), 0 , 3 , 0 , 9136 , 5 , 4 ), // #623
- INST(Punpckhwd , ExtRm_P , O(000F00,69,_,_,_,_,_,_ ), 0 , 4 , 0 , 9148 , 135, 75 ), // #624
- INST(Punpcklbw , ExtRm_P , O(000F00,60,_,_,_,_,_,_ ), 0 , 4 , 0 , 9159 , 135, 75 ), // #625
- INST(Punpckldq , ExtRm_P , O(000F00,62,_,_,_,_,_,_ ), 0 , 4 , 0 , 9170 , 135, 75 ), // #626
- INST(Punpcklqdq , ExtRm , O(660F00,6C,_,_,_,_,_,_ ), 0 , 3 , 0 , 9181 , 5 , 4 ), // #627
- INST(Punpcklwd , ExtRm_P , O(000F00,61,_,_,_,_,_,_ ), 0 , 4 , 0 , 9193 , 135, 75 ), // #628
- INST(Push , X86Push , O(000000,FF,6,_,_,_,_,_ ), O(000000,50,_,_,_,_,_,_ ), 30 , 77 , 2348 , 159, 0 ), // #629
- INST(Pusha , X86Op , O(660000,60,_,_,_,_,_,_ ), 0 , 19 , 0 , 2353 , 75 , 0 ), // #630
- INST(Pushad , X86Op , O(000000,60,_,_,_,_,_,_ ), 0 , 0 , 0 , 2359 , 75 , 0 ), // #631
- INST(Pushf , X86Op , O(660000,9C,_,_,_,_,_,_ ), 0 , 19 , 0 , 2366 , 30 , 92 ), // #632
- INST(Pushfd , X86Op , O(000000,9C,_,_,_,_,_,_ ), 0 , 0 , 0 , 2372 , 75 , 92 ), // #633
- INST(Pushfq , X86Op , O(000000,9C,_,_,_,_,_,_ ), 0 , 0 , 0 , 2379 , 155, 92 ), // #634
- INST(Pxor , ExtRm_P , O(000F00,EF,_,_,_,_,_,_ ), 0 , 4 , 0 , 9204 , 138, 75 ), // #635
- INST(Rcl , X86Rot , O(000000,D0,2,_,x,_,_,_ ), 0 , 1 , 0 , 2386 , 160, 93 ), // #636
- INST(Rcpps , ExtRm , O(000F00,53,_,_,_,_,_,_ ), 0 , 4 , 0 , 9332 , 5 , 5 ), // #637
- INST(Rcpss , ExtRm , O(F30F00,53,_,_,_,_,_,_ ), 0 , 6 , 0 , 9339 , 7 , 5 ), // #638
- INST(Rcr , X86Rot , O(000000,D0,3,_,x,_,_,_ ), 0 , 78 , 0 , 2390 , 160, 93 ), // #639
- INST(Rdfsbase , X86M , O(F30F00,AE,0,_,x,_,_,_ ), 0 , 6 , 0 , 2394 , 161, 94 ), // #640
- INST(Rdgsbase , X86M , O(F30F00,AE,1,_,x,_,_,_ ), 0 , 85 , 0 , 2403 , 161, 94 ), // #641
- INST(Rdmsr , X86Op , O(000F00,32,_,_,_,_,_,_ ), 0 , 4 , 0 , 2412 , 162, 95 ), // #642
- INST(Rdpid , X86R_Native , O(F30F00,C7,7,_,_,_,_,_ ), 0 , 86 , 0 , 2418 , 163, 96 ), // #643
- INST(Rdpmc , X86Op , O(000F00,33,_,_,_,_,_,_ ), 0 , 4 , 0 , 2424 , 162, 0 ), // #644
- INST(Rdrand , X86M , O(000F00,C7,6,_,x,_,_,_ ), 0 , 73 , 0 , 2430 , 23 , 97 ), // #645
- INST(Rdseed , X86M , O(000F00,C7,7,_,x,_,_,_ ), 0 , 22 , 0 , 2437 , 23 , 98 ), // #646
- INST(Rdtsc , X86Op , O(000F00,31,_,_,_,_,_,_ ), 0 , 4 , 0 , 2444 , 28 , 99 ), // #647
- INST(Rdtscp , X86Op , O(000F01,F9,_,_,_,_,_,_ ), 0 , 21 , 0 , 2450 , 162, 100), // #648
- INST(Ret , X86Ret , O(000000,C2,_,_,_,_,_,_ ), 0 , 0 , 0 , 2883 , 164, 0 ), // #649
- INST(Rol , X86Rot , O(000000,D0,0,_,x,_,_,_ ), 0 , 0 , 0 , 2457 , 160, 101), // #650
- INST(Ror , X86Rot , O(000000,D0,1,_,x,_,_,_ ), 0 , 29 , 0 , 2461 , 160, 101), // #651
- INST(Rorx , VexRmi_Wx , V(F20F3A,F0,_,0,x,_,_,_ ), 0 , 87 , 0 , 2465 , 165, 78 ), // #652
- INST(Roundpd , ExtRmi , O(660F3A,09,_,_,_,_,_,_ ), 0 , 8 , 0 , 9434 , 8 , 12 ), // #653
- INST(Roundps , ExtRmi , O(660F3A,08,_,_,_,_,_,_ ), 0 , 8 , 0 , 9443 , 8 , 12 ), // #654
- INST(Roundsd , ExtRmi , O(660F3A,0B,_,_,_,_,_,_ ), 0 , 8 , 0 , 9452 , 35 , 12 ), // #655
- INST(Roundss , ExtRmi , O(660F3A,0A,_,_,_,_,_,_ ), 0 , 8 , 0 , 9461 , 36 , 12 ), // #656
- INST(Rsm , X86Op , O(000F00,AA,_,_,_,_,_,_ ), 0 , 4 , 0 , 2470 , 75 , 1 ), // #657
- INST(Rsqrtps , ExtRm , O(000F00,52,_,_,_,_,_,_ ), 0 , 4 , 0 , 9558 , 5 , 5 ), // #658
- INST(Rsqrtss , ExtRm , O(F30F00,52,_,_,_,_,_,_ ), 0 , 6 , 0 , 9567 , 7 , 5 ), // #659
- INST(Sahf , X86Op , O(000000,9E,_,_,_,_,_,_ ), 0 , 0 , 0 , 2474 , 90 , 102), // #660
- INST(Sal , X86Rot , O(000000,D0,4,_,x,_,_,_ ), 0 , 9 , 0 , 2479 , 160, 1 ), // #661
- INST(Sar , X86Rot , O(000000,D0,7,_,x,_,_,_ ), 0 , 25 , 0 , 2483 , 160, 1 ), // #662
- INST(Sarx , VexRmv_Wx , V(F30F38,F7,_,0,x,_,_,_ ), 0 , 82 , 0 , 2487 , 13 , 78 ), // #663
- INST(Sbb , X86Arith , O(000000,18,3,_,x,_,_,_ ), 0 , 78 , 0 , 2492 , 166, 2 ), // #664
- INST(Scas , X86StrRm , O(000000,AE,_,_,_,_,_,_ ), 0 , 0 , 0 , 2496 , 167, 35 ), // #665
- INST(Seta , X86Set , O(000F00,97,_,_,_,_,_,_ ), 0 , 4 , 0 , 2501 , 168, 54 ), // #666
- INST(Setae , X86Set , O(000F00,93,_,_,_,_,_,_ ), 0 , 4 , 0 , 2506 , 168, 55 ), // #667
- INST(Setb , X86Set , O(000F00,92,_,_,_,_,_,_ ), 0 , 4 , 0 , 2512 , 168, 55 ), // #668
- INST(Setbe , X86Set , O(000F00,96,_,_,_,_,_,_ ), 0 , 4 , 0 , 2517 , 168, 54 ), // #669
- INST(Setc , X86Set , O(000F00,92,_,_,_,_,_,_ ), 0 , 4 , 0 , 2523 , 168, 55 ), // #670
- INST(Sete , X86Set , O(000F00,94,_,_,_,_,_,_ ), 0 , 4 , 0 , 2528 , 168, 56 ), // #671
- INST(Setg , X86Set , O(000F00,9F,_,_,_,_,_,_ ), 0 , 4 , 0 , 2533 , 168, 57 ), // #672
- INST(Setge , X86Set , O(000F00,9D,_,_,_,_,_,_ ), 0 , 4 , 0 , 2538 , 168, 58 ), // #673
- INST(Setl , X86Set , O(000F00,9C,_,_,_,_,_,_ ), 0 , 4 , 0 , 2544 , 168, 58 ), // #674
- INST(Setle , X86Set , O(000F00,9E,_,_,_,_,_,_ ), 0 , 4 , 0 , 2549 , 168, 57 ), // #675
- INST(Setna , X86Set , O(000F00,96,_,_,_,_,_,_ ), 0 , 4 , 0 , 2555 , 168, 54 ), // #676
- INST(Setnae , X86Set , O(000F00,92,_,_,_,_,_,_ ), 0 , 4 , 0 , 2561 , 168, 55 ), // #677
- INST(Setnb , X86Set , O(000F00,93,_,_,_,_,_,_ ), 0 , 4 , 0 , 2568 , 168, 55 ), // #678
- INST(Setnbe , X86Set , O(000F00,97,_,_,_,_,_,_ ), 0 , 4 , 0 , 2574 , 168, 54 ), // #679
- INST(Setnc , X86Set , O(000F00,93,_,_,_,_,_,_ ), 0 , 4 , 0 , 2581 , 168, 55 ), // #680
- INST(Setne , X86Set , O(000F00,95,_,_,_,_,_,_ ), 0 , 4 , 0 , 2587 , 168, 56 ), // #681
- INST(Setng , X86Set , O(000F00,9E,_,_,_,_,_,_ ), 0 , 4 , 0 , 2593 , 168, 57 ), // #682
- INST(Setnge , X86Set , O(000F00,9C,_,_,_,_,_,_ ), 0 , 4 , 0 , 2599 , 168, 58 ), // #683
- INST(Setnl , X86Set , O(000F00,9D,_,_,_,_,_,_ ), 0 , 4 , 0 , 2606 , 168, 58 ), // #684
- INST(Setnle , X86Set , O(000F00,9F,_,_,_,_,_,_ ), 0 , 4 , 0 , 2612 , 168, 57 ), // #685
- INST(Setno , X86Set , O(000F00,91,_,_,_,_,_,_ ), 0 , 4 , 0 , 2619 , 168, 52 ), // #686
- INST(Setnp , X86Set , O(000F00,9B,_,_,_,_,_,_ ), 0 , 4 , 0 , 2625 , 168, 59 ), // #687
- INST(Setns , X86Set , O(000F00,99,_,_,_,_,_,_ ), 0 , 4 , 0 , 2631 , 168, 60 ), // #688
- INST(Setnz , X86Set , O(000F00,95,_,_,_,_,_,_ ), 0 , 4 , 0 , 2637 , 168, 56 ), // #689
- INST(Seto , X86Set , O(000F00,90,_,_,_,_,_,_ ), 0 , 4 , 0 , 2643 , 168, 52 ), // #690
- INST(Setp , X86Set , O(000F00,9A,_,_,_,_,_,_ ), 0 , 4 , 0 , 2648 , 168, 59 ), // #691
- INST(Setpe , X86Set , O(000F00,9A,_,_,_,_,_,_ ), 0 , 4 , 0 , 2653 , 168, 59 ), // #692
- INST(Setpo , X86Set , O(000F00,9B,_,_,_,_,_,_ ), 0 , 4 , 0 , 2659 , 168, 59 ), // #693
- INST(Sets , X86Set , O(000F00,98,_,_,_,_,_,_ ), 0 , 4 , 0 , 2665 , 168, 60 ), // #694
- INST(Setz , X86Set , O(000F00,94,_,_,_,_,_,_ ), 0 , 4 , 0 , 2670 , 168, 56 ), // #695
- INST(Sfence , X86Fence , O(000F00,AE,7,_,_,_,_,_ ), 0 , 22 , 0 , 2675 , 30 , 71 ), // #696
- INST(Sgdt , X86M_Only , O(000F00,01,0,_,_,_,_,_ ), 0 , 4 , 0 , 2682 , 31 , 0 ), // #697
- INST(Sha1msg1 , ExtRm , O(000F38,C9,_,_,_,_,_,_ ), 0 , 76 , 0 , 2687 , 5 , 103), // #698
- INST(Sha1msg2 , ExtRm , O(000F38,CA,_,_,_,_,_,_ ), 0 , 76 , 0 , 2696 , 5 , 103), // #699
- INST(Sha1nexte , ExtRm , O(000F38,C8,_,_,_,_,_,_ ), 0 , 76 , 0 , 2705 , 5 , 103), // #700
- INST(Sha1rnds4 , ExtRmi , O(000F3A,CC,_,_,_,_,_,_ ), 0 , 79 , 0 , 2715 , 8 , 103), // #701
- INST(Sha256msg1 , ExtRm , O(000F38,CC,_,_,_,_,_,_ ), 0 , 76 , 0 , 2725 , 5 , 103), // #702
- INST(Sha256msg2 , ExtRm , O(000F38,CD,_,_,_,_,_,_ ), 0 , 76 , 0 , 2736 , 5 , 103), // #703
- INST(Sha256rnds2 , ExtRm_XMM0 , O(000F38,CB,_,_,_,_,_,_ ), 0 , 76 , 0 , 2747 , 15 , 103), // #704
- INST(Shl , X86Rot , O(000000,D0,4,_,x,_,_,_ ), 0 , 9 , 0 , 2759 , 160, 1 ), // #705
- INST(Shld , X86ShldShrd , O(000F00,A4,_,_,x,_,_,_ ), 0 , 4 , 0 , 8603 , 169, 1 ), // #706
- INST(Shlx , VexRmv_Wx , V(660F38,F7,_,0,x,_,_,_ ), 0 , 88 , 0 , 2763 , 13 , 78 ), // #707
- INST(Shr , X86Rot , O(000000,D0,5,_,x,_,_,_ ), 0 , 58 , 0 , 2768 , 160, 1 ), // #708
- INST(Shrd , X86ShldShrd , O(000F00,AC,_,_,x,_,_,_ ), 0 , 4 , 0 , 2772 , 169, 1 ), // #709
- INST(Shrx , VexRmv_Wx , V(F20F38,F7,_,0,x,_,_,_ ), 0 , 77 , 0 , 2777 , 13 , 78 ), // #710
- INST(Shufpd , ExtRmi , O(660F00,C6,_,_,_,_,_,_ ), 0 , 3 , 0 , 9828 , 8 , 4 ), // #711
- INST(Shufps , ExtRmi , O(000F00,C6,_,_,_,_,_,_ ), 0 , 4 , 0 , 9836 , 8 , 5 ), // #712
- INST(Sidt , X86M_Only , O(000F00,01,1,_,_,_,_,_ ), 0 , 27 , 0 , 2782 , 31 , 0 ), // #713
- INST(Skinit , X86Op_xAX , O(000F01,DE,_,_,_,_,_,_ ), 0 , 21 , 0 , 2787 , 50 , 104), // #714
- INST(Sldt , X86M , O(000F00,00,0,_,_,_,_,_ ), 0 , 4 , 0 , 2794 , 170, 0 ), // #715
- INST(Slwpcb , VexR_Wx , V(XOP_M9,12,1,0,x,_,_,_ ), 0 , 11 , 0 , 2799 , 98 , 68 ), // #716
- INST(Smsw , X86M , O(000F00,01,4,_,_,_,_,_ ), 0 , 89 , 0 , 2806 , 170, 0 ), // #717
- INST(Sqrtpd , ExtRm , O(660F00,51,_,_,_,_,_,_ ), 0 , 3 , 0 , 9844 , 5 , 4 ), // #718
- INST(Sqrtps , ExtRm , O(000F00,51,_,_,_,_,_,_ ), 0 , 4 , 0 , 9559 , 5 , 5 ), // #719
- INST(Sqrtsd , ExtRm , O(F20F00,51,_,_,_,_,_,_ ), 0 , 5 , 0 , 9860 , 6 , 4 ), // #720
- INST(Sqrtss , ExtRm , O(F30F00,51,_,_,_,_,_,_ ), 0 , 6 , 0 , 9568 , 7 , 5 ), // #721
- INST(Stac , X86Op , O(000F01,CB,_,_,_,_,_,_ ), 0 , 21 , 0 , 2811 , 30 , 16 ), // #722
- INST(Stc , X86Op , O(000000,F9,_,_,_,_,_,_ ), 0 , 0 , 0 , 2816 , 30 , 17 ), // #723
- INST(Std , X86Op , O(000000,FD,_,_,_,_,_,_ ), 0 , 0 , 0 , 6586 , 30 , 18 ), // #724
- INST(Stgi , X86Op , O(000F01,DC,_,_,_,_,_,_ ), 0 , 21 , 0 , 2820 , 30 , 104), // #725
- INST(Sti , X86Op , O(000000,FB,_,_,_,_,_,_ ), 0 , 0 , 0 , 2825 , 30 , 23 ), // #726
- INST(Stmxcsr , X86M_Only , O(000F00,AE,3,_,_,_,_,_ ), 0 , 71 , 0 , 9876 , 93 , 5 ), // #727
- INST(Stos , X86StrMr , O(000000,AA,_,_,_,_,_,_ ), 0 , 0 , 0 , 2829 , 171, 69 ), // #728
- INST(Str , X86M , O(000F00,00,1,_,_,_,_,_ ), 0 , 27 , 0 , 2834 , 170, 0 ), // #729
- INST(Sub , X86Arith , O(000000,28,5,_,x,_,_,_ ), 0 , 58 , 0 , 836 , 166, 1 ), // #730
- INST(Subpd , ExtRm , O(660F00,5C,_,_,_,_,_,_ ), 0 , 3 , 0 , 4556 , 5 , 4 ), // #731
- INST(Subps , ExtRm , O(000F00,5C,_,_,_,_,_,_ ), 0 , 4 , 0 , 4568 , 5 , 5 ), // #732
- INST(Subsd , ExtRm , O(F20F00,5C,_,_,_,_,_,_ ), 0 , 5 , 0 , 5244 , 6 , 4 ), // #733
- INST(Subss , ExtRm , O(F30F00,5C,_,_,_,_,_,_ ), 0 , 6 , 0 , 5254 , 7 , 5 ), // #734
- INST(Swapgs , X86Op , O(000F01,F8,_,_,_,_,_,_ ), 0 , 21 , 0 , 2838 , 155, 0 ), // #735
- INST(Syscall , X86Op , O(000F00,05,_,_,_,_,_,_ ), 0 , 4 , 0 , 2845 , 155, 0 ), // #736
- INST(Sysenter , X86Op , O(000F00,34,_,_,_,_,_,_ ), 0 , 4 , 0 , 2853 , 30 , 0 ), // #737
- INST(Sysexit , X86Op , O(000F00,35,_,_,_,_,_,_ ), 0 , 4 , 0 , 2862 , 30 , 0 ), // #738
- INST(Sysexit64 , X86Op , O(000F00,35,_,_,_,_,_,_ ), 0 , 4 , 0 , 2870 , 30 , 0 ), // #739
- INST(Sysret , X86Op , O(000F00,07,_,_,_,_,_,_ ), 0 , 4 , 0 , 2880 , 155, 0 ), // #740
- INST(Sysret64 , X86Op , O(000F00,07,_,_,_,_,_,_ ), 0 , 4 , 0 , 2887 , 155, 0 ), // #741
- INST(T1mskc , VexVm_Wx , V(XOP_M9,01,7,0,x,_,_,_ ), 0 , 90 , 0 , 2896 , 14 , 11 ), // #742
- INST(Test , X86Test , O(000000,84,_,_,x,_,_,_ ), O(000000,F6,_,_,x,_,_,_ ), 0 , 78 , 9032 , 172, 1 ), // #743
- INST(Tzcnt , X86Rm_Raw66H , O(F30F00,BC,_,_,x,_,_,_ ), 0 , 6 , 0 , 2903 , 22 , 9 ), // #744
- INST(Tzmsk , VexVm_Wx , V(XOP_M9,01,4,0,x,_,_,_ ), 0 , 91 , 0 , 2909 , 14 , 11 ), // #745
- INST(Ucomisd , ExtRm , O(660F00,2E,_,_,_,_,_,_ ), 0 , 3 , 0 , 9929 , 6 , 39 ), // #746
- INST(Ucomiss , ExtRm , O(000F00,2E,_,_,_,_,_,_ ), 0 , 4 , 0 , 9938 , 7 , 40 ), // #747
- INST(Ud2 , X86Op , O(000F00,0B,_,_,_,_,_,_ ), 0 , 4 , 0 , 2915 , 30 , 0 ), // #748
- INST(Unpckhpd , ExtRm , O(660F00,15,_,_,_,_,_,_ ), 0 , 3 , 0 , 9947 , 5 , 4 ), // #749
- INST(Unpckhps , ExtRm , O(000F00,15,_,_,_,_,_,_ ), 0 , 4 , 0 , 9957 , 5 , 5 ), // #750
- INST(Unpcklpd , ExtRm , O(660F00,14,_,_,_,_,_,_ ), 0 , 3 , 0 , 9967 , 5 , 4 ), // #751
- INST(Unpcklps , ExtRm , O(000F00,14,_,_,_,_,_,_ ), 0 , 4 , 0 , 9977 , 5 , 5 ), // #752
- INST(V4fmaddps , VexRm_T1_4X , E(F20F38,9A,_,2,_,0,2,T4X), 0 , 92 , 0 , 2919 , 173, 105), // #753
- INST(V4fmaddss , VexRm_T1_4X , E(F20F38,9B,_,2,_,0,2,T4X), 0 , 92 , 0 , 2929 , 174, 105), // #754
- INST(V4fnmaddps , VexRm_T1_4X , E(F20F38,AA,_,2,_,0,2,T4X), 0 , 92 , 0 , 2939 , 173, 105), // #755
- INST(V4fnmaddss , VexRm_T1_4X , E(F20F38,AB,_,2,_,0,2,T4X), 0 , 92 , 0 , 2950 , 174, 105), // #756
- INST(Vaddpd , VexRvm_Lx , V(660F00,58,_,x,I,1,4,FV ), 0 , 93 , 0 , 2961 , 175, 106), // #757
- INST(Vaddps , VexRvm_Lx , V(000F00,58,_,x,I,0,4,FV ), 0 , 94 , 0 , 2968 , 176, 106), // #758
- INST(Vaddsd , VexRvm , V(F20F00,58,_,I,I,1,3,T1S), 0 , 95 , 0 , 2975 , 177, 107), // #759
- INST(Vaddss , VexRvm , V(F30F00,58,_,I,I,0,2,T1S), 0 , 96 , 0 , 2982 , 178, 107), // #760
- INST(Vaddsubpd , VexRvm_Lx , V(660F00,D0,_,x,I,_,_,_ ), 0 , 63 , 0 , 2989 , 179, 108), // #761
- INST(Vaddsubps , VexRvm_Lx , V(F20F00,D0,_,x,I,_,_,_ ), 0 , 97 , 0 , 2999 , 179, 108), // #762
- INST(Vaesdec , VexRvm_Lx , V(660F38,DE,_,x,I,_,4,FVM), 0 , 98 , 0 , 3009 , 180, 109), // #763
- INST(Vaesdeclast , VexRvm_Lx , V(660F38,DF,_,x,I,_,4,FVM), 0 , 98 , 0 , 3017 , 180, 109), // #764
- INST(Vaesenc , VexRvm_Lx , V(660F38,DC,_,x,I,_,4,FVM), 0 , 98 , 0 , 3029 , 180, 109), // #765
- INST(Vaesenclast , VexRvm_Lx , V(660F38,DD,_,x,I,_,4,FVM), 0 , 98 , 0 , 3037 , 180, 109), // #766
- INST(Vaesimc , VexRm , V(660F38,DB,_,0,I,_,_,_ ), 0 , 88 , 0 , 3049 , 181, 110), // #767
- INST(Vaeskeygenassist , VexRmi , V(660F3A,DF,_,0,I,_,_,_ ), 0 , 67 , 0 , 3057 , 182, 110), // #768
- INST(Valignd , VexRvmi_Lx , E(660F3A,03,_,x,_,0,4,FV ), 0 , 99 , 0 , 3074 , 183, 111), // #769
- INST(Valignq , VexRvmi_Lx , E(660F3A,03,_,x,_,1,4,FV ), 0 , 100, 0 , 3082 , 184, 111), // #770
- INST(Vandnpd , VexRvm_Lx , V(660F00,55,_,x,I,1,4,FV ), 0 , 93 , 0 , 3090 , 185, 112), // #771
- INST(Vandnps , VexRvm_Lx , V(000F00,55,_,x,I,0,4,FV ), 0 , 94 , 0 , 3098 , 186, 112), // #772
- INST(Vandpd , VexRvm_Lx , V(660F00,54,_,x,I,1,4,FV ), 0 , 93 , 0 , 3106 , 187, 112), // #773
- INST(Vandps , VexRvm_Lx , V(000F00,54,_,x,I,0,4,FV ), 0 , 94 , 0 , 3113 , 188, 112), // #774
- INST(Vblendmb , VexRvm_Lx , E(660F38,66,_,x,_,0,4,FVM), 0 , 101, 0 , 3120 , 189, 113), // #775
- INST(Vblendmd , VexRvm_Lx , E(660F38,64,_,x,_,0,4,FV ), 0 , 102, 0 , 3129 , 190, 111), // #776
- INST(Vblendmpd , VexRvm_Lx , E(660F38,65,_,x,_,1,4,FV ), 0 , 103, 0 , 3138 , 191, 111), // #777
- INST(Vblendmps , VexRvm_Lx , E(660F38,65,_,x,_,0,4,FV ), 0 , 102, 0 , 3148 , 190, 111), // #778
- INST(Vblendmq , VexRvm_Lx , E(660F38,64,_,x,_,1,4,FV ), 0 , 103, 0 , 3158 , 191, 111), // #779
- INST(Vblendmw , VexRvm_Lx , E(660F38,66,_,x,_,1,4,FVM), 0 , 104, 0 , 3167 , 189, 113), // #780
- INST(Vblendpd , VexRvmi_Lx , V(660F3A,0D,_,x,I,_,_,_ ), 0 , 67 , 0 , 3176 , 192, 108), // #781
- INST(Vblendps , VexRvmi_Lx , V(660F3A,0C,_,x,I,_,_,_ ), 0 , 67 , 0 , 3185 , 192, 108), // #782
- INST(Vblendvpd , VexRvmr_Lx , V(660F3A,4B,_,x,0,_,_,_ ), 0 , 67 , 0 , 3194 , 193, 108), // #783
- INST(Vblendvps , VexRvmr_Lx , V(660F3A,4A,_,x,0,_,_,_ ), 0 , 67 , 0 , 3204 , 193, 108), // #784
- INST(Vbroadcastf128 , VexRm , V(660F38,1A,_,1,0,_,_,_ ), 0 , 105, 0 , 3214 , 194, 108), // #785
- INST(Vbroadcastf32x2 , VexRm_Lx , E(660F38,19,_,x,_,0,3,T2 ), 0 , 106, 0 , 3229 , 195, 114), // #786
- INST(Vbroadcastf32x4 , VexRm_Lx , E(660F38,1A,_,x,_,0,4,T4 ), 0 , 107, 0 , 3245 , 196, 63 ), // #787
- INST(Vbroadcastf32x8 , VexRm , E(660F38,1B,_,2,_,0,5,T8 ), 0 , 108, 0 , 3261 , 197, 61 ), // #788
- INST(Vbroadcastf64x2 , VexRm_Lx , E(660F38,1A,_,x,_,1,4,T2 ), 0 , 109, 0 , 3277 , 196, 114), // #789
- INST(Vbroadcastf64x4 , VexRm , E(660F38,1B,_,2,_,1,5,T4 ), 0 , 110, 0 , 3293 , 197, 63 ), // #790
- INST(Vbroadcasti128 , VexRm , V(660F38,5A,_,1,0,_,_,_ ), 0 , 105, 0 , 3309 , 194, 115), // #791
- INST(Vbroadcasti32x2 , VexRm_Lx , E(660F38,59,_,x,_,0,3,T2 ), 0 , 106, 0 , 3324 , 198, 114), // #792
- INST(Vbroadcasti32x4 , VexRm_Lx , E(660F38,5A,_,x,_,0,4,T4 ), 0 , 107, 0 , 3340 , 196, 111), // #793
- INST(Vbroadcasti32x8 , VexRm , E(660F38,5B,_,2,_,0,5,T8 ), 0 , 108, 0 , 3356 , 197, 61 ), // #794
- INST(Vbroadcasti64x2 , VexRm_Lx , E(660F38,5A,_,x,_,1,4,T2 ), 0 , 109, 0 , 3372 , 196, 114), // #795
- INST(Vbroadcasti64x4 , VexRm , E(660F38,5B,_,2,_,1,5,T4 ), 0 , 110, 0 , 3388 , 197, 63 ), // #796
- INST(Vbroadcastsd , VexRm_Lx , V(660F38,19,_,x,0,1,3,T1S), 0 , 111, 0 , 3404 , 199, 116), // #797
- INST(Vbroadcastss , VexRm_Lx , V(660F38,18,_,x,0,0,2,T1S), 0 , 112, 0 , 3417 , 200, 116), // #798
- INST(Vcmppd , VexRvmi_Lx , V(660F00,C2,_,x,I,1,4,FV ), 0 , 93 , 0 , 3430 , 201, 106), // #799
- INST(Vcmpps , VexRvmi_Lx , V(000F00,C2,_,x,I,0,4,FV ), 0 , 94 , 0 , 3437 , 202, 106), // #800
- INST(Vcmpsd , VexRvmi , V(F20F00,C2,_,I,I,1,3,T1S), 0 , 95 , 0 , 3444 , 203, 107), // #801
- INST(Vcmpss , VexRvmi , V(F30F00,C2,_,I,I,0,2,T1S), 0 , 96 , 0 , 3451 , 204, 107), // #802
- INST(Vcomisd , VexRm , V(660F00,2F,_,I,I,1,3,T1S), 0 , 113, 0 , 3458 , 205, 117), // #803
- INST(Vcomiss , VexRm , V(000F00,2F,_,I,I,0,2,T1S), 0 , 114, 0 , 3466 , 206, 117), // #804
- INST(Vcompresspd , VexMr_Lx , E(660F38,8A,_,x,_,1,3,T1S), 0 , 115, 0 , 3474 , 207, 111), // #805
- INST(Vcompressps , VexMr_Lx , E(660F38,8A,_,x,_,0,2,T1S), 0 , 116, 0 , 3486 , 207, 111), // #806
- INST(Vcvtdq2pd , VexRm_Lx , V(F30F00,E6,_,x,I,0,3,HV ), 0 , 117, 0 , 3498 , 208, 106), // #807
- INST(Vcvtdq2ps , VexRm_Lx , V(000F00,5B,_,x,I,0,4,FV ), 0 , 94 , 0 , 3508 , 209, 106), // #808
- INST(Vcvtne2ps2bf16 , VexRvm , E(F20F38,72,_,_,_,0,_,_ ), 0 , 118, 0 , 3518 , 190, 118), // #809
- INST(Vcvtneps2bf16 , VexRm , E(F30F38,72,_,_,_,0,_,_ ), 0 , 119, 0 , 3533 , 210, 118), // #810
- INST(Vcvtpd2dq , VexRm_Lx , V(F20F00,E6,_,x,I,1,4,FV ), 0 , 120, 0 , 3547 , 211, 106), // #811
- INST(Vcvtpd2ps , VexRm_Lx , V(660F00,5A,_,x,I,1,4,FV ), 0 , 93 , 0 , 3557 , 211, 106), // #812
- INST(Vcvtpd2qq , VexRm_Lx , E(660F00,7B,_,x,_,1,4,FV ), 0 , 121, 0 , 3567 , 212, 114), // #813
- INST(Vcvtpd2udq , VexRm_Lx , E(000F00,79,_,x,_,1,4,FV ), 0 , 122, 0 , 3577 , 213, 111), // #814
- INST(Vcvtpd2uqq , VexRm_Lx , E(660F00,79,_,x,_,1,4,FV ), 0 , 121, 0 , 3588 , 212, 114), // #815
- INST(Vcvtph2ps , VexRm_Lx , V(660F38,13,_,x,0,0,3,HVM), 0 , 123, 0 , 3599 , 214, 119), // #816
- INST(Vcvtps2dq , VexRm_Lx , V(660F00,5B,_,x,I,0,4,FV ), 0 , 124, 0 , 3609 , 209, 106), // #817
- INST(Vcvtps2pd , VexRm_Lx , V(000F00,5A,_,x,I,0,4,HV ), 0 , 125, 0 , 3619 , 215, 106), // #818
- INST(Vcvtps2ph , VexMri_Lx , V(660F3A,1D,_,x,0,0,3,HVM), 0 , 126, 0 , 3629 , 216, 119), // #819
- INST(Vcvtps2qq , VexRm_Lx , E(660F00,7B,_,x,_,0,3,HV ), 0 , 127, 0 , 3639 , 217, 114), // #820
- INST(Vcvtps2udq , VexRm_Lx , E(000F00,79,_,x,_,0,4,FV ), 0 , 128, 0 , 3649 , 218, 111), // #821
- INST(Vcvtps2uqq , VexRm_Lx , E(660F00,79,_,x,_,0,3,HV ), 0 , 127, 0 , 3660 , 217, 114), // #822
- INST(Vcvtqq2pd , VexRm_Lx , E(F30F00,E6,_,x,_,1,4,FV ), 0 , 129, 0 , 3671 , 212, 114), // #823
- INST(Vcvtqq2ps , VexRm_Lx , E(000F00,5B,_,x,_,1,4,FV ), 0 , 122, 0 , 3681 , 213, 114), // #824
- INST(Vcvtsd2si , VexRm_Wx , V(F20F00,2D,_,I,x,x,3,T1F), 0 , 130, 0 , 3691 , 219, 107), // #825
- INST(Vcvtsd2ss , VexRvm , V(F20F00,5A,_,I,I,1,3,T1S), 0 , 95 , 0 , 3701 , 177, 107), // #826
- INST(Vcvtsd2usi , VexRm_Wx , E(F20F00,79,_,I,_,x,3,T1F), 0 , 131, 0 , 3711 , 220, 63 ), // #827
- INST(Vcvtsi2sd , VexRvm_Wx , V(F20F00,2A,_,I,x,x,2,T1W), 0 , 132, 0 , 3722 , 221, 107), // #828
- INST(Vcvtsi2ss , VexRvm_Wx , V(F30F00,2A,_,I,x,x,2,T1W), 0 , 133, 0 , 3732 , 221, 107), // #829
- INST(Vcvtss2sd , VexRvm , V(F30F00,5A,_,I,I,0,2,T1S), 0 , 96 , 0 , 3742 , 222, 107), // #830
- INST(Vcvtss2si , VexRm_Wx , V(F30F00,2D,_,I,x,x,2,T1F), 0 , 134, 0 , 3752 , 223, 107), // #831
- INST(Vcvtss2usi , VexRm_Wx , E(F30F00,79,_,I,_,x,2,T1F), 0 , 135, 0 , 3762 , 224, 63 ), // #832
- INST(Vcvttpd2dq , VexRm_Lx , V(660F00,E6,_,x,I,1,4,FV ), 0 , 93 , 0 , 3773 , 225, 106), // #833
- INST(Vcvttpd2qq , VexRm_Lx , E(660F00,7A,_,x,_,1,4,FV ), 0 , 121, 0 , 3784 , 226, 111), // #834
- INST(Vcvttpd2udq , VexRm_Lx , E(000F00,78,_,x,_,1,4,FV ), 0 , 122, 0 , 3795 , 227, 111), // #835
- INST(Vcvttpd2uqq , VexRm_Lx , E(660F00,78,_,x,_,1,4,FV ), 0 , 121, 0 , 3807 , 226, 114), // #836
- INST(Vcvttps2dq , VexRm_Lx , V(F30F00,5B,_,x,I,0,4,FV ), 0 , 136, 0 , 3819 , 228, 106), // #837
- INST(Vcvttps2qq , VexRm_Lx , E(660F00,7A,_,x,_,0,3,HV ), 0 , 127, 0 , 3830 , 229, 114), // #838
- INST(Vcvttps2udq , VexRm_Lx , E(000F00,78,_,x,_,0,4,FV ), 0 , 128, 0 , 3841 , 230, 111), // #839
- INST(Vcvttps2uqq , VexRm_Lx , E(660F00,78,_,x,_,0,3,HV ), 0 , 127, 0 , 3853 , 229, 114), // #840
- INST(Vcvttsd2si , VexRm_Wx , V(F20F00,2C,_,I,x,x,3,T1F), 0 , 130, 0 , 3865 , 231, 107), // #841
- INST(Vcvttsd2usi , VexRm_Wx , E(F20F00,78,_,I,_,x,3,T1F), 0 , 131, 0 , 3876 , 232, 63 ), // #842
- INST(Vcvttss2si , VexRm_Wx , V(F30F00,2C,_,I,x,x,2,T1F), 0 , 134, 0 , 3888 , 233, 107), // #843
- INST(Vcvttss2usi , VexRm_Wx , E(F30F00,78,_,I,_,x,2,T1F), 0 , 135, 0 , 3899 , 234, 63 ), // #844
- INST(Vcvtudq2pd , VexRm_Lx , E(F30F00,7A,_,x,_,0,3,HV ), 0 , 137, 0 , 3911 , 235, 111), // #845
- INST(Vcvtudq2ps , VexRm_Lx , E(F20F00,7A,_,x,_,0,4,FV ), 0 , 138, 0 , 3922 , 218, 111), // #846
- INST(Vcvtuqq2pd , VexRm_Lx , E(F30F00,7A,_,x,_,1,4,FV ), 0 , 129, 0 , 3933 , 212, 114), // #847
- INST(Vcvtuqq2ps , VexRm_Lx , E(F20F00,7A,_,x,_,1,4,FV ), 0 , 139, 0 , 3944 , 213, 114), // #848
- INST(Vcvtusi2sd , VexRvm_Wx , E(F20F00,7B,_,I,_,x,2,T1W), 0 , 140, 0 , 3955 , 236, 63 ), // #849
- INST(Vcvtusi2ss , VexRvm_Wx , E(F30F00,7B,_,I,_,x,2,T1W), 0 , 141, 0 , 3966 , 236, 63 ), // #850
- INST(Vdbpsadbw , VexRvmi_Lx , E(660F3A,42,_,x,_,0,4,FVM), 0 , 142, 0 , 3977 , 237, 113), // #851
- INST(Vdivpd , VexRvm_Lx , V(660F00,5E,_,x,I,1,4,FV ), 0 , 93 , 0 , 3987 , 175, 106), // #852
- INST(Vdivps , VexRvm_Lx , V(000F00,5E,_,x,I,0,4,FV ), 0 , 94 , 0 , 3994 , 176, 106), // #853
- INST(Vdivsd , VexRvm , V(F20F00,5E,_,I,I,1,3,T1S), 0 , 95 , 0 , 4001 , 177, 107), // #854
- INST(Vdivss , VexRvm , V(F30F00,5E,_,I,I,0,2,T1S), 0 , 96 , 0 , 4008 , 178, 107), // #855
- INST(Vdpbf16ps , VexRvm , E(F30F38,52,_,_,_,0,_,_ ), 0 , 119, 0 , 4015 , 190, 118), // #856
- INST(Vdppd , VexRvmi_Lx , V(660F3A,41,_,x,I,_,_,_ ), 0 , 67 , 0 , 4025 , 238, 108), // #857
- INST(Vdpps , VexRvmi_Lx , V(660F3A,40,_,x,I,_,_,_ ), 0 , 67 , 0 , 4031 , 192, 108), // #858
- INST(Verr , X86M_NoSize , O(000F00,00,4,_,_,_,_,_ ), 0 , 89 , 0 , 4037 , 97 , 10 ), // #859
- INST(Verw , X86M_NoSize , O(000F00,00,5,_,_,_,_,_ ), 0 , 70 , 0 , 4042 , 97 , 10 ), // #860
- INST(Vexp2pd , VexRm , E(660F38,C8,_,2,_,1,4,FV ), 0 , 143, 0 , 4047 , 239, 120), // #861
- INST(Vexp2ps , VexRm , E(660F38,C8,_,2,_,0,4,FV ), 0 , 144, 0 , 4055 , 240, 120), // #862
- INST(Vexpandpd , VexRm_Lx , E(660F38,88,_,x,_,1,3,T1S), 0 , 115, 0 , 4063 , 241, 111), // #863
- INST(Vexpandps , VexRm_Lx , E(660F38,88,_,x,_,0,2,T1S), 0 , 116, 0 , 4073 , 241, 111), // #864
- INST(Vextractf128 , VexMri , V(660F3A,19,_,1,0,_,_,_ ), 0 , 145, 0 , 4083 , 242, 108), // #865
- INST(Vextractf32x4 , VexMri_Lx , E(660F3A,19,_,x,_,0,4,T4 ), 0 , 146, 0 , 4096 , 243, 111), // #866
- INST(Vextractf32x8 , VexMri , E(660F3A,1B,_,2,_,0,5,T8 ), 0 , 147, 0 , 4110 , 244, 61 ), // #867
- INST(Vextractf64x2 , VexMri_Lx , E(660F3A,19,_,x,_,1,4,T2 ), 0 , 148, 0 , 4124 , 243, 114), // #868
- INST(Vextractf64x4 , VexMri , E(660F3A,1B,_,2,_,1,5,T4 ), 0 , 149, 0 , 4138 , 244, 63 ), // #869
- INST(Vextracti128 , VexMri , V(660F3A,39,_,1,0,_,_,_ ), 0 , 145, 0 , 4152 , 242, 115), // #870
- INST(Vextracti32x4 , VexMri_Lx , E(660F3A,39,_,x,_,0,4,T4 ), 0 , 146, 0 , 4165 , 243, 111), // #871
- INST(Vextracti32x8 , VexMri , E(660F3A,3B,_,2,_,0,5,T8 ), 0 , 147, 0 , 4179 , 244, 61 ), // #872
- INST(Vextracti64x2 , VexMri_Lx , E(660F3A,39,_,x,_,1,4,T2 ), 0 , 148, 0 , 4193 , 243, 114), // #873
- INST(Vextracti64x4 , VexMri , E(660F3A,3B,_,2,_,1,5,T4 ), 0 , 149, 0 , 4207 , 244, 63 ), // #874
- INST(Vextractps , VexMri , V(660F3A,17,_,0,I,I,2,T1S), 0 , 150, 0 , 4221 , 245, 107), // #875
- INST(Vfixupimmpd , VexRvmi_Lx , E(660F3A,54,_,x,_,1,4,FV ), 0 , 100, 0 , 4232 , 246, 111), // #876
- INST(Vfixupimmps , VexRvmi_Lx , E(660F3A,54,_,x,_,0,4,FV ), 0 , 99 , 0 , 4244 , 247, 111), // #877
- INST(Vfixupimmsd , VexRvmi , E(660F3A,55,_,I,_,1,3,T1S), 0 , 151, 0 , 4256 , 248, 63 ), // #878
- INST(Vfixupimmss , VexRvmi , E(660F3A,55,_,I,_,0,2,T1S), 0 , 152, 0 , 4268 , 249, 63 ), // #879
- INST(Vfmadd132pd , VexRvm_Lx , V(660F38,98,_,x,1,1,4,FV ), 0 , 153, 0 , 4280 , 175, 121), // #880
- INST(Vfmadd132ps , VexRvm_Lx , V(660F38,98,_,x,0,0,4,FV ), 0 , 154, 0 , 4292 , 176, 121), // #881
- INST(Vfmadd132sd , VexRvm , V(660F38,99,_,I,1,1,3,T1S), 0 , 155, 0 , 4304 , 177, 122), // #882
- INST(Vfmadd132ss , VexRvm , V(660F38,99,_,I,0,0,2,T1S), 0 , 112, 0 , 4316 , 178, 122), // #883
- INST(Vfmadd213pd , VexRvm_Lx , V(660F38,A8,_,x,1,1,4,FV ), 0 , 153, 0 , 4328 , 175, 121), // #884
- INST(Vfmadd213ps , VexRvm_Lx , V(660F38,A8,_,x,0,0,4,FV ), 0 , 154, 0 , 4340 , 176, 121), // #885
- INST(Vfmadd213sd , VexRvm , V(660F38,A9,_,I,1,1,3,T1S), 0 , 155, 0 , 4352 , 177, 122), // #886
- INST(Vfmadd213ss , VexRvm , V(660F38,A9,_,I,0,0,2,T1S), 0 , 112, 0 , 4364 , 178, 122), // #887
- INST(Vfmadd231pd , VexRvm_Lx , V(660F38,B8,_,x,1,1,4,FV ), 0 , 153, 0 , 4376 , 175, 121), // #888
- INST(Vfmadd231ps , VexRvm_Lx , V(660F38,B8,_,x,0,0,4,FV ), 0 , 154, 0 , 4388 , 176, 121), // #889
- INST(Vfmadd231sd , VexRvm , V(660F38,B9,_,I,1,1,3,T1S), 0 , 155, 0 , 4400 , 177, 122), // #890
- INST(Vfmadd231ss , VexRvm , V(660F38,B9,_,I,0,0,2,T1S), 0 , 112, 0 , 4412 , 178, 122), // #891
- INST(Vfmaddpd , Fma4_Lx , V(660F3A,69,_,x,x,_,_,_ ), 0 , 67 , 0 , 4424 , 250, 123), // #892
- INST(Vfmaddps , Fma4_Lx , V(660F3A,68,_,x,x,_,_,_ ), 0 , 67 , 0 , 4433 , 250, 123), // #893
- INST(Vfmaddsd , Fma4 , V(660F3A,6B,_,0,x,_,_,_ ), 0 , 67 , 0 , 4442 , 251, 123), // #894
- INST(Vfmaddss , Fma4 , V(660F3A,6A,_,0,x,_,_,_ ), 0 , 67 , 0 , 4451 , 252, 123), // #895
- INST(Vfmaddsub132pd , VexRvm_Lx , V(660F38,96,_,x,1,1,4,FV ), 0 , 153, 0 , 4460 , 175, 121), // #896
- INST(Vfmaddsub132ps , VexRvm_Lx , V(660F38,96,_,x,0,0,4,FV ), 0 , 154, 0 , 4475 , 176, 121), // #897
- INST(Vfmaddsub213pd , VexRvm_Lx , V(660F38,A6,_,x,1,1,4,FV ), 0 , 153, 0 , 4490 , 175, 121), // #898
- INST(Vfmaddsub213ps , VexRvm_Lx , V(660F38,A6,_,x,0,0,4,FV ), 0 , 154, 0 , 4505 , 176, 121), // #899
- INST(Vfmaddsub231pd , VexRvm_Lx , V(660F38,B6,_,x,1,1,4,FV ), 0 , 153, 0 , 4520 , 175, 121), // #900
- INST(Vfmaddsub231ps , VexRvm_Lx , V(660F38,B6,_,x,0,0,4,FV ), 0 , 154, 0 , 4535 , 176, 121), // #901
- INST(Vfmaddsubpd , Fma4_Lx , V(660F3A,5D,_,x,x,_,_,_ ), 0 , 67 , 0 , 4550 , 250, 123), // #902
- INST(Vfmaddsubps , Fma4_Lx , V(660F3A,5C,_,x,x,_,_,_ ), 0 , 67 , 0 , 4562 , 250, 123), // #903
- INST(Vfmsub132pd , VexRvm_Lx , V(660F38,9A,_,x,1,1,4,FV ), 0 , 153, 0 , 4574 , 175, 121), // #904
- INST(Vfmsub132ps , VexRvm_Lx , V(660F38,9A,_,x,0,0,4,FV ), 0 , 154, 0 , 4586 , 176, 121), // #905
- INST(Vfmsub132sd , VexRvm , V(660F38,9B,_,I,1,1,3,T1S), 0 , 155, 0 , 4598 , 177, 122), // #906
- INST(Vfmsub132ss , VexRvm , V(660F38,9B,_,I,0,0,2,T1S), 0 , 112, 0 , 4610 , 178, 122), // #907
- INST(Vfmsub213pd , VexRvm_Lx , V(660F38,AA,_,x,1,1,4,FV ), 0 , 153, 0 , 4622 , 175, 121), // #908
- INST(Vfmsub213ps , VexRvm_Lx , V(660F38,AA,_,x,0,0,4,FV ), 0 , 154, 0 , 4634 , 176, 121), // #909
- INST(Vfmsub213sd , VexRvm , V(660F38,AB,_,I,1,1,3,T1S), 0 , 155, 0 , 4646 , 177, 122), // #910
- INST(Vfmsub213ss , VexRvm , V(660F38,AB,_,I,0,0,2,T1S), 0 , 112, 0 , 4658 , 178, 122), // #911
- INST(Vfmsub231pd , VexRvm_Lx , V(660F38,BA,_,x,1,1,4,FV ), 0 , 153, 0 , 4670 , 175, 121), // #912
- INST(Vfmsub231ps , VexRvm_Lx , V(660F38,BA,_,x,0,0,4,FV ), 0 , 154, 0 , 4682 , 176, 121), // #913
- INST(Vfmsub231sd , VexRvm , V(660F38,BB,_,I,1,1,3,T1S), 0 , 155, 0 , 4694 , 177, 122), // #914
- INST(Vfmsub231ss , VexRvm , V(660F38,BB,_,I,0,0,2,T1S), 0 , 112, 0 , 4706 , 178, 122), // #915
- INST(Vfmsubadd132pd , VexRvm_Lx , V(660F38,97,_,x,1,1,4,FV ), 0 , 153, 0 , 4718 , 175, 121), // #916
- INST(Vfmsubadd132ps , VexRvm_Lx , V(660F38,97,_,x,0,0,4,FV ), 0 , 154, 0 , 4733 , 176, 121), // #917
- INST(Vfmsubadd213pd , VexRvm_Lx , V(660F38,A7,_,x,1,1,4,FV ), 0 , 153, 0 , 4748 , 175, 121), // #918
- INST(Vfmsubadd213ps , VexRvm_Lx , V(660F38,A7,_,x,0,0,4,FV ), 0 , 154, 0 , 4763 , 176, 121), // #919
- INST(Vfmsubadd231pd , VexRvm_Lx , V(660F38,B7,_,x,1,1,4,FV ), 0 , 153, 0 , 4778 , 175, 121), // #920
- INST(Vfmsubadd231ps , VexRvm_Lx , V(660F38,B7,_,x,0,0,4,FV ), 0 , 154, 0 , 4793 , 176, 121), // #921
- INST(Vfmsubaddpd , Fma4_Lx , V(660F3A,5F,_,x,x,_,_,_ ), 0 , 67 , 0 , 4808 , 250, 123), // #922
- INST(Vfmsubaddps , Fma4_Lx , V(660F3A,5E,_,x,x,_,_,_ ), 0 , 67 , 0 , 4820 , 250, 123), // #923
- INST(Vfmsubpd , Fma4_Lx , V(660F3A,6D,_,x,x,_,_,_ ), 0 , 67 , 0 , 4832 , 250, 123), // #924
- INST(Vfmsubps , Fma4_Lx , V(660F3A,6C,_,x,x,_,_,_ ), 0 , 67 , 0 , 4841 , 250, 123), // #925
- INST(Vfmsubsd , Fma4 , V(660F3A,6F,_,0,x,_,_,_ ), 0 , 67 , 0 , 4850 , 251, 123), // #926
- INST(Vfmsubss , Fma4 , V(660F3A,6E,_,0,x,_,_,_ ), 0 , 67 , 0 , 4859 , 252, 123), // #927
- INST(Vfnmadd132pd , VexRvm_Lx , V(660F38,9C,_,x,1,1,4,FV ), 0 , 153, 0 , 4868 , 175, 121), // #928
- INST(Vfnmadd132ps , VexRvm_Lx , V(660F38,9C,_,x,0,0,4,FV ), 0 , 154, 0 , 4881 , 176, 121), // #929
- INST(Vfnmadd132sd , VexRvm , V(660F38,9D,_,I,1,1,3,T1S), 0 , 155, 0 , 4894 , 177, 122), // #930
- INST(Vfnmadd132ss , VexRvm , V(660F38,9D,_,I,0,0,2,T1S), 0 , 112, 0 , 4907 , 178, 122), // #931
- INST(Vfnmadd213pd , VexRvm_Lx , V(660F38,AC,_,x,1,1,4,FV ), 0 , 153, 0 , 4920 , 175, 121), // #932
- INST(Vfnmadd213ps , VexRvm_Lx , V(660F38,AC,_,x,0,0,4,FV ), 0 , 154, 0 , 4933 , 176, 121), // #933
- INST(Vfnmadd213sd , VexRvm , V(660F38,AD,_,I,1,1,3,T1S), 0 , 155, 0 , 4946 , 177, 122), // #934
- INST(Vfnmadd213ss , VexRvm , V(660F38,AD,_,I,0,0,2,T1S), 0 , 112, 0 , 4959 , 178, 122), // #935
- INST(Vfnmadd231pd , VexRvm_Lx , V(660F38,BC,_,x,1,1,4,FV ), 0 , 153, 0 , 4972 , 175, 121), // #936
- INST(Vfnmadd231ps , VexRvm_Lx , V(660F38,BC,_,x,0,0,4,FV ), 0 , 154, 0 , 4985 , 176, 121), // #937
- INST(Vfnmadd231sd , VexRvm , V(660F38,BC,_,I,1,1,3,T1S), 0 , 155, 0 , 4998 , 177, 122), // #938
- INST(Vfnmadd231ss , VexRvm , V(660F38,BC,_,I,0,0,2,T1S), 0 , 112, 0 , 5011 , 178, 122), // #939
- INST(Vfnmaddpd , Fma4_Lx , V(660F3A,79,_,x,x,_,_,_ ), 0 , 67 , 0 , 5024 , 250, 123), // #940
- INST(Vfnmaddps , Fma4_Lx , V(660F3A,78,_,x,x,_,_,_ ), 0 , 67 , 0 , 5034 , 250, 123), // #941
- INST(Vfnmaddsd , Fma4 , V(660F3A,7B,_,0,x,_,_,_ ), 0 , 67 , 0 , 5044 , 251, 123), // #942
- INST(Vfnmaddss , Fma4 , V(660F3A,7A,_,0,x,_,_,_ ), 0 , 67 , 0 , 5054 , 252, 123), // #943
- INST(Vfnmsub132pd , VexRvm_Lx , V(660F38,9E,_,x,1,1,4,FV ), 0 , 153, 0 , 5064 , 175, 121), // #944
- INST(Vfnmsub132ps , VexRvm_Lx , V(660F38,9E,_,x,0,0,4,FV ), 0 , 154, 0 , 5077 , 176, 121), // #945
- INST(Vfnmsub132sd , VexRvm , V(660F38,9F,_,I,1,1,3,T1S), 0 , 155, 0 , 5090 , 177, 122), // #946
- INST(Vfnmsub132ss , VexRvm , V(660F38,9F,_,I,0,0,2,T1S), 0 , 112, 0 , 5103 , 178, 122), // #947
- INST(Vfnmsub213pd , VexRvm_Lx , V(660F38,AE,_,x,1,1,4,FV ), 0 , 153, 0 , 5116 , 175, 121), // #948
- INST(Vfnmsub213ps , VexRvm_Lx , V(660F38,AE,_,x,0,0,4,FV ), 0 , 154, 0 , 5129 , 176, 121), // #949
- INST(Vfnmsub213sd , VexRvm , V(660F38,AF,_,I,1,1,3,T1S), 0 , 155, 0 , 5142 , 177, 122), // #950
- INST(Vfnmsub213ss , VexRvm , V(660F38,AF,_,I,0,0,2,T1S), 0 , 112, 0 , 5155 , 178, 122), // #951
- INST(Vfnmsub231pd , VexRvm_Lx , V(660F38,BE,_,x,1,1,4,FV ), 0 , 153, 0 , 5168 , 175, 121), // #952
- INST(Vfnmsub231ps , VexRvm_Lx , V(660F38,BE,_,x,0,0,4,FV ), 0 , 154, 0 , 5181 , 176, 121), // #953
- INST(Vfnmsub231sd , VexRvm , V(660F38,BF,_,I,1,1,3,T1S), 0 , 155, 0 , 5194 , 177, 122), // #954
- INST(Vfnmsub231ss , VexRvm , V(660F38,BF,_,I,0,0,2,T1S), 0 , 112, 0 , 5207 , 178, 122), // #955
- INST(Vfnmsubpd , Fma4_Lx , V(660F3A,7D,_,x,x,_,_,_ ), 0 , 67 , 0 , 5220 , 250, 123), // #956
- INST(Vfnmsubps , Fma4_Lx , V(660F3A,7C,_,x,x,_,_,_ ), 0 , 67 , 0 , 5230 , 250, 123), // #957
- INST(Vfnmsubsd , Fma4 , V(660F3A,7F,_,0,x,_,_,_ ), 0 , 67 , 0 , 5240 , 251, 123), // #958
- INST(Vfnmsubss , Fma4 , V(660F3A,7E,_,0,x,_,_,_ ), 0 , 67 , 0 , 5250 , 252, 123), // #959
- INST(Vfpclasspd , VexRmi_Lx , E(660F3A,66,_,x,_,1,4,FV ), 0 , 100, 0 , 5260 , 253, 114), // #960
- INST(Vfpclassps , VexRmi_Lx , E(660F3A,66,_,x,_,0,4,FV ), 0 , 99 , 0 , 5271 , 254, 114), // #961
- INST(Vfpclasssd , VexRmi_Lx , E(660F3A,67,_,I,_,1,3,T1S), 0 , 151, 0 , 5282 , 255, 61 ), // #962
- INST(Vfpclassss , VexRmi_Lx , E(660F3A,67,_,I,_,0,2,T1S), 0 , 152, 0 , 5293 , 256, 61 ), // #963
- INST(Vfrczpd , VexRm_Lx , V(XOP_M9,81,_,x,0,_,_,_ ), 0 , 72 , 0 , 5304 , 257, 124), // #964
- INST(Vfrczps , VexRm_Lx , V(XOP_M9,80,_,x,0,_,_,_ ), 0 , 72 , 0 , 5312 , 257, 124), // #965
- INST(Vfrczsd , VexRm , V(XOP_M9,83,_,0,0,_,_,_ ), 0 , 72 , 0 , 5320 , 258, 124), // #966
- INST(Vfrczss , VexRm , V(XOP_M9,82,_,0,0,_,_,_ ), 0 , 72 , 0 , 5328 , 259, 124), // #967
- INST(Vgatherdpd , VexRmvRm_VM , V(660F38,92,_,x,1,_,_,_ ), V(660F38,92,_,x,_,1,3,T1S), 156, 79 , 5336 , 260, 125), // #968
- INST(Vgatherdps , VexRmvRm_VM , V(660F38,92,_,x,0,_,_,_ ), V(660F38,92,_,x,_,0,2,T1S), 88 , 80 , 5347 , 261, 125), // #969
- INST(Vgatherpf0dpd , VexM_VM , E(660F38,C6,1,2,_,1,3,T1S), 0 , 157, 0 , 5358 , 262, 126), // #970
- INST(Vgatherpf0dps , VexM_VM , E(660F38,C6,1,2,_,0,2,T1S), 0 , 158, 0 , 5372 , 263, 126), // #971
- INST(Vgatherpf0qpd , VexM_VM , E(660F38,C7,1,2,_,1,3,T1S), 0 , 157, 0 , 5386 , 264, 126), // #972
- INST(Vgatherpf0qps , VexM_VM , E(660F38,C7,1,2,_,0,2,T1S), 0 , 158, 0 , 5400 , 264, 126), // #973
- INST(Vgatherpf1dpd , VexM_VM , E(660F38,C6,2,2,_,1,3,T1S), 0 , 159, 0 , 5414 , 262, 126), // #974
- INST(Vgatherpf1dps , VexM_VM , E(660F38,C6,2,2,_,0,2,T1S), 0 , 160, 0 , 5428 , 263, 126), // #975
- INST(Vgatherpf1qpd , VexM_VM , E(660F38,C7,2,2,_,1,3,T1S), 0 , 159, 0 , 5442 , 264, 126), // #976
- INST(Vgatherpf1qps , VexM_VM , E(660F38,C7,2,2,_,0,2,T1S), 0 , 160, 0 , 5456 , 264, 126), // #977
- INST(Vgatherqpd , VexRmvRm_VM , V(660F38,93,_,x,1,_,_,_ ), V(660F38,93,_,x,_,1,3,T1S), 156, 81 , 5470 , 265, 125), // #978
- INST(Vgatherqps , VexRmvRm_VM , V(660F38,93,_,x,0,_,_,_ ), V(660F38,93,_,x,_,0,2,T1S), 88 , 82 , 5481 , 266, 125), // #979
- INST(Vgetexppd , VexRm_Lx , E(660F38,42,_,x,_,1,4,FV ), 0 , 103, 0 , 5492 , 226, 111), // #980
- INST(Vgetexpps , VexRm_Lx , E(660F38,42,_,x,_,0,4,FV ), 0 , 102, 0 , 5502 , 230, 111), // #981
- INST(Vgetexpsd , VexRvm , E(660F38,43,_,I,_,1,3,T1S), 0 , 115, 0 , 5512 , 267, 63 ), // #982
- INST(Vgetexpss , VexRvm , E(660F38,43,_,I,_,0,2,T1S), 0 , 116, 0 , 5522 , 268, 63 ), // #983
- INST(Vgetmantpd , VexRmi_Lx , E(660F3A,26,_,x,_,1,4,FV ), 0 , 100, 0 , 5532 , 269, 111), // #984
- INST(Vgetmantps , VexRmi_Lx , E(660F3A,26,_,x,_,0,4,FV ), 0 , 99 , 0 , 5543 , 270, 111), // #985
- INST(Vgetmantsd , VexRvmi , E(660F3A,27,_,I,_,1,3,T1S), 0 , 151, 0 , 5554 , 248, 63 ), // #986
- INST(Vgetmantss , VexRvmi , E(660F3A,27,_,I,_,0,2,T1S), 0 , 152, 0 , 5565 , 249, 63 ), // #987
- INST(Vgf2p8affineinvqb, VexRvmi_Lx , V(660F3A,CF,_,x,1,1,4,FV ), 0 , 161, 0 , 5576 , 271, 127), // #988
- INST(Vgf2p8affineqb , VexRvmi_Lx , V(660F3A,CE,_,x,1,1,4,FV ), 0 , 161, 0 , 5594 , 271, 127), // #989
- INST(Vgf2p8mulb , VexRvm_Lx , V(660F38,CF,_,x,0,0,4,FV ), 0 , 154, 0 , 5609 , 272, 127), // #990
- INST(Vhaddpd , VexRvm_Lx , V(660F00,7C,_,x,I,_,_,_ ), 0 , 63 , 0 , 5620 , 179, 108), // #991
- INST(Vhaddps , VexRvm_Lx , V(F20F00,7C,_,x,I,_,_,_ ), 0 , 97 , 0 , 5628 , 179, 108), // #992
- INST(Vhsubpd , VexRvm_Lx , V(660F00,7D,_,x,I,_,_,_ ), 0 , 63 , 0 , 5636 , 179, 108), // #993
- INST(Vhsubps , VexRvm_Lx , V(F20F00,7D,_,x,I,_,_,_ ), 0 , 97 , 0 , 5644 , 179, 108), // #994
- INST(Vinsertf128 , VexRvmi , V(660F3A,18,_,1,0,_,_,_ ), 0 , 145, 0 , 5652 , 273, 108), // #995
- INST(Vinsertf32x4 , VexRvmi_Lx , E(660F3A,18,_,x,_,0,4,T4 ), 0 , 146, 0 , 5664 , 274, 111), // #996
- INST(Vinsertf32x8 , VexRvmi , E(660F3A,1A,_,2,_,0,5,T8 ), 0 , 147, 0 , 5677 , 275, 61 ), // #997
- INST(Vinsertf64x2 , VexRvmi_Lx , E(660F3A,18,_,x,_,1,4,T2 ), 0 , 148, 0 , 5690 , 274, 114), // #998
- INST(Vinsertf64x4 , VexRvmi , E(660F3A,1A,_,2,_,1,5,T4 ), 0 , 149, 0 , 5703 , 275, 63 ), // #999
- INST(Vinserti128 , VexRvmi , V(660F3A,38,_,1,0,_,_,_ ), 0 , 145, 0 , 5716 , 273, 115), // #1000
- INST(Vinserti32x4 , VexRvmi_Lx , E(660F3A,38,_,x,_,0,4,T4 ), 0 , 146, 0 , 5728 , 274, 111), // #1001
- INST(Vinserti32x8 , VexRvmi , E(660F3A,3A,_,2,_,0,5,T8 ), 0 , 147, 0 , 5741 , 275, 61 ), // #1002
- INST(Vinserti64x2 , VexRvmi_Lx , E(660F3A,38,_,x,_,1,4,T2 ), 0 , 148, 0 , 5754 , 274, 114), // #1003
- INST(Vinserti64x4 , VexRvmi , E(660F3A,3A,_,2,_,1,5,T4 ), 0 , 149, 0 , 5767 , 275, 63 ), // #1004
- INST(Vinsertps , VexRvmi , V(660F3A,21,_,0,I,0,2,T1S), 0 , 150, 0 , 5780 , 276, 107), // #1005
- INST(Vlddqu , VexRm_Lx , V(F20F00,F0,_,x,I,_,_,_ ), 0 , 97 , 0 , 5790 , 277, 108), // #1006
- INST(Vldmxcsr , VexM , V(000F00,AE,2,0,I,_,_,_ ), 0 , 162, 0 , 5797 , 278, 108), // #1007
- INST(Vmaskmovdqu , VexRm_ZDI , V(660F00,F7,_,0,I,_,_,_ ), 0 , 63 , 0 , 5806 , 279, 108), // #1008
- INST(Vmaskmovpd , VexRvmMvr_Lx , V(660F38,2D,_,x,0,_,_,_ ), V(660F38,2F,_,x,0,_,_,_ ), 88 , 83 , 5818 , 280, 108), // #1009
- INST(Vmaskmovps , VexRvmMvr_Lx , V(660F38,2C,_,x,0,_,_,_ ), V(660F38,2E,_,x,0,_,_,_ ), 88 , 84 , 5829 , 280, 108), // #1010
- INST(Vmaxpd , VexRvm_Lx , V(660F00,5F,_,x,I,1,4,FV ), 0 , 93 , 0 , 5840 , 281, 106), // #1011
- INST(Vmaxps , VexRvm_Lx , V(000F00,5F,_,x,I,0,4,FV ), 0 , 94 , 0 , 5847 , 282, 106), // #1012
- INST(Vmaxsd , VexRvm , V(F20F00,5F,_,I,I,1,3,T1S), 0 , 95 , 0 , 5854 , 283, 106), // #1013
- INST(Vmaxss , VexRvm , V(F30F00,5F,_,I,I,0,2,T1S), 0 , 96 , 0 , 5861 , 222, 106), // #1014
- INST(Vmcall , X86Op , O(000F01,C1,_,_,_,_,_,_ ), 0 , 21 , 0 , 5868 , 30 , 53 ), // #1015
- INST(Vmclear , X86M_Only , O(660F00,C7,6,_,_,_,_,_ ), 0 , 24 , 0 , 5875 , 284, 53 ), // #1016
- INST(Vmfunc , X86Op , O(000F01,D4,_,_,_,_,_,_ ), 0 , 21 , 0 , 5883 , 30 , 53 ), // #1017
- INST(Vminpd , VexRvm_Lx , V(660F00,5D,_,x,I,1,4,FV ), 0 , 93 , 0 , 5890 , 281, 106), // #1018
- INST(Vminps , VexRvm_Lx , V(000F00,5D,_,x,I,0,4,FV ), 0 , 94 , 0 , 5897 , 282, 106), // #1019
- INST(Vminsd , VexRvm , V(F20F00,5D,_,I,I,1,3,T1S), 0 , 95 , 0 , 5904 , 283, 106), // #1020
- INST(Vminss , VexRvm , V(F30F00,5D,_,I,I,0,2,T1S), 0 , 96 , 0 , 5911 , 222, 106), // #1021
- INST(Vmlaunch , X86Op , O(000F01,C2,_,_,_,_,_,_ ), 0 , 21 , 0 , 5918 , 30 , 53 ), // #1022
- INST(Vmload , X86Op_xAX , O(000F01,DA,_,_,_,_,_,_ ), 0 , 21 , 0 , 5927 , 285, 22 ), // #1023
- INST(Vmmcall , X86Op , O(000F01,D9,_,_,_,_,_,_ ), 0 , 21 , 0 , 5934 , 30 , 22 ), // #1024
- INST(Vmovapd , VexRmMr_Lx , V(660F00,28,_,x,I,1,4,FVM), V(660F00,29,_,x,I,1,4,FVM), 163, 85 , 5942 , 286, 106), // #1025
- INST(Vmovaps , VexRmMr_Lx , V(000F00,28,_,x,I,0,4,FVM), V(000F00,29,_,x,I,0,4,FVM), 164, 86 , 5950 , 286, 106), // #1026
- INST(Vmovd , VexMovdMovq , V(660F00,6E,_,0,0,0,2,T1S), V(660F00,7E,_,0,0,0,2,T1S), 165, 87 , 5958 , 287, 107), // #1027
- INST(Vmovddup , VexRm_Lx , V(F20F00,12,_,x,I,1,3,DUP), 0 , 166, 0 , 5964 , 288, 106), // #1028
- INST(Vmovdqa , VexRmMr_Lx , V(660F00,6F,_,x,I,_,_,_ ), V(660F00,7F,_,x,I,_,_,_ ), 63 , 88 , 5973 , 289, 108), // #1029
- INST(Vmovdqa32 , VexRmMr_Lx , E(660F00,6F,_,x,_,0,4,FVM), E(660F00,7F,_,x,_,0,4,FVM), 167, 89 , 5981 , 290, 111), // #1030
- INST(Vmovdqa64 , VexRmMr_Lx , E(660F00,6F,_,x,_,1,4,FVM), E(660F00,7F,_,x,_,1,4,FVM), 168, 90 , 5991 , 290, 111), // #1031
- INST(Vmovdqu , VexRmMr_Lx , V(F30F00,6F,_,x,I,_,_,_ ), V(F30F00,7F,_,x,I,_,_,_ ), 169, 91 , 6001 , 289, 108), // #1032
- INST(Vmovdqu16 , VexRmMr_Lx , E(F20F00,6F,_,x,_,1,4,FVM), E(F20F00,7F,_,x,_,1,4,FVM), 170, 92 , 6009 , 290, 113), // #1033
- INST(Vmovdqu32 , VexRmMr_Lx , E(F30F00,6F,_,x,_,0,4,FVM), E(F30F00,7F,_,x,_,0,4,FVM), 171, 93 , 6019 , 290, 111), // #1034
- INST(Vmovdqu64 , VexRmMr_Lx , E(F30F00,6F,_,x,_,1,4,FVM), E(F30F00,7F,_,x,_,1,4,FVM), 172, 94 , 6029 , 290, 111), // #1035
- INST(Vmovdqu8 , VexRmMr_Lx , E(F20F00,6F,_,x,_,0,4,FVM), E(F20F00,7F,_,x,_,0,4,FVM), 173, 95 , 6039 , 290, 113), // #1036
- INST(Vmovhlps , VexRvm , V(000F00,12,_,0,I,0,_,_ ), 0 , 66 , 0 , 6048 , 291, 107), // #1037
- INST(Vmovhpd , VexRvmMr , V(660F00,16,_,0,I,1,3,T1S), V(660F00,17,_,0,I,1,3,T1S), 113, 96 , 6057 , 292, 107), // #1038
- INST(Vmovhps , VexRvmMr , V(000F00,16,_,0,I,0,3,T2 ), V(000F00,17,_,0,I,0,3,T2 ), 174, 97 , 6065 , 292, 107), // #1039
- INST(Vmovlhps , VexRvm , V(000F00,16,_,0,I,0,_,_ ), 0 , 66 , 0 , 6073 , 291, 107), // #1040
- INST(Vmovlpd , VexRvmMr , V(660F00,12,_,0,I,1,3,T1S), V(660F00,13,_,0,I,1,3,T1S), 113, 98 , 6082 , 292, 107), // #1041
- INST(Vmovlps , VexRvmMr , V(000F00,12,_,0,I,0,3,T2 ), V(000F00,13,_,0,I,0,3,T2 ), 174, 99 , 6090 , 292, 107), // #1042
- INST(Vmovmskpd , VexRm_Lx , V(660F00,50,_,x,I,_,_,_ ), 0 , 63 , 0 , 6098 , 293, 108), // #1043
- INST(Vmovmskps , VexRm_Lx , V(000F00,50,_,x,I,_,_,_ ), 0 , 66 , 0 , 6108 , 293, 108), // #1044
- INST(Vmovntdq , VexMr_Lx , V(660F00,E7,_,x,I,0,4,FVM), 0 , 175, 0 , 6118 , 294, 106), // #1045
- INST(Vmovntdqa , VexRm_Lx , V(660F38,2A,_,x,I,0,4,FVM), 0 , 98 , 0 , 6127 , 295, 116), // #1046
- INST(Vmovntpd , VexMr_Lx , V(660F00,2B,_,x,I,1,4,FVM), 0 , 163, 0 , 6137 , 294, 106), // #1047
- INST(Vmovntps , VexMr_Lx , V(000F00,2B,_,x,I,0,4,FVM), 0 , 164, 0 , 6146 , 294, 106), // #1048
- INST(Vmovq , VexMovdMovq , V(660F00,6E,_,0,I,1,3,T1S), V(660F00,7E,_,0,I,1,3,T1S), 113, 100, 6155 , 296, 107), // #1049
- INST(Vmovsd , VexMovssMovsd , V(F20F00,10,_,I,I,1,3,T1S), V(F20F00,11,_,I,I,1,3,T1S), 95 , 101, 6161 , 297, 107), // #1050
- INST(Vmovshdup , VexRm_Lx , V(F30F00,16,_,x,I,0,4,FVM), 0 , 176, 0 , 6168 , 298, 106), // #1051
- INST(Vmovsldup , VexRm_Lx , V(F30F00,12,_,x,I,0,4,FVM), 0 , 176, 0 , 6178 , 298, 106), // #1052
- INST(Vmovss , VexMovssMovsd , V(F30F00,10,_,I,I,0,2,T1S), V(F30F00,11,_,I,I,0,2,T1S), 96 , 102, 6188 , 299, 107), // #1053
- INST(Vmovupd , VexRmMr_Lx , V(660F00,10,_,x,I,1,4,FVM), V(660F00,11,_,x,I,1,4,FVM), 163, 103, 6195 , 286, 106), // #1054
- INST(Vmovups , VexRmMr_Lx , V(000F00,10,_,x,I,0,4,FVM), V(000F00,11,_,x,I,0,4,FVM), 164, 104, 6203 , 286, 106), // #1055
- INST(Vmpsadbw , VexRvmi_Lx , V(660F3A,42,_,x,I,_,_,_ ), 0 , 67 , 0 , 6211 , 192, 128), // #1056
- INST(Vmptrld , X86M_Only , O(000F00,C7,6,_,_,_,_,_ ), 0 , 73 , 0 , 6220 , 284, 53 ), // #1057
- INST(Vmptrst , X86M_Only , O(000F00,C7,7,_,_,_,_,_ ), 0 , 22 , 0 , 6228 , 284, 53 ), // #1058
- INST(Vmread , X86Mr_NoSize , O(000F00,78,_,_,_,_,_,_ ), 0 , 4 , 0 , 6236 , 300, 53 ), // #1059
- INST(Vmresume , X86Op , O(000F01,C3,_,_,_,_,_,_ ), 0 , 21 , 0 , 6243 , 30 , 53 ), // #1060
- INST(Vmrun , X86Op_xAX , O(000F01,D8,_,_,_,_,_,_ ), 0 , 21 , 0 , 6252 , 285, 22 ), // #1061
- INST(Vmsave , X86Op_xAX , O(000F01,DB,_,_,_,_,_,_ ), 0 , 21 , 0 , 6258 , 285, 22 ), // #1062
- INST(Vmulpd , VexRvm_Lx , V(660F00,59,_,x,I,1,4,FV ), 0 , 93 , 0 , 6265 , 175, 106), // #1063
- INST(Vmulps , VexRvm_Lx , V(000F00,59,_,x,I,0,4,FV ), 0 , 94 , 0 , 6272 , 176, 106), // #1064
- INST(Vmulsd , VexRvm_Lx , V(F20F00,59,_,I,I,1,3,T1S), 0 , 95 , 0 , 6279 , 177, 107), // #1065
- INST(Vmulss , VexRvm_Lx , V(F30F00,59,_,I,I,0,2,T1S), 0 , 96 , 0 , 6286 , 178, 107), // #1066
- INST(Vmwrite , X86Rm_NoSize , O(000F00,79,_,_,_,_,_,_ ), 0 , 4 , 0 , 6293 , 301, 53 ), // #1067
- INST(Vmxon , X86M_Only , O(F30F00,C7,6,_,_,_,_,_ ), 0 , 177, 0 , 6301 , 284, 53 ), // #1068
- INST(Vorpd , VexRvm_Lx , V(660F00,56,_,x,I,1,4,FV ), 0 , 93 , 0 , 6307 , 187, 112), // #1069
- INST(Vorps , VexRvm_Lx , V(000F00,56,_,x,I,0,4,FV ), 0 , 94 , 0 , 6313 , 188, 112), // #1070
- INST(Vp4dpwssd , VexRm_T1_4X , E(F20F38,52,_,2,_,0,2,T4X), 0 , 92 , 0 , 6319 , 173, 129), // #1071
- INST(Vp4dpwssds , VexRm_T1_4X , E(F20F38,53,_,2,_,0,2,T4X), 0 , 92 , 0 , 6329 , 173, 129), // #1072
- INST(Vpabsb , VexRm_Lx , V(660F38,1C,_,x,I,_,4,FVM), 0 , 98 , 0 , 6340 , 298, 130), // #1073
- INST(Vpabsd , VexRm_Lx , V(660F38,1E,_,x,I,0,4,FV ), 0 , 154, 0 , 6347 , 298, 116), // #1074
- INST(Vpabsq , VexRm_Lx , E(660F38,1F,_,x,_,1,4,FV ), 0 , 103, 0 , 6354 , 241, 111), // #1075
- INST(Vpabsw , VexRm_Lx , V(660F38,1D,_,x,I,_,4,FVM), 0 , 98 , 0 , 6361 , 298, 130), // #1076
- INST(Vpackssdw , VexRvm_Lx , V(660F00,6B,_,x,I,0,4,FV ), 0 , 124, 0 , 6368 , 186, 130), // #1077
- INST(Vpacksswb , VexRvm_Lx , V(660F00,63,_,x,I,I,4,FVM), 0 , 175, 0 , 6378 , 272, 130), // #1078
- INST(Vpackusdw , VexRvm_Lx , V(660F38,2B,_,x,I,0,4,FV ), 0 , 154, 0 , 6388 , 186, 130), // #1079
- INST(Vpackuswb , VexRvm_Lx , V(660F00,67,_,x,I,I,4,FVM), 0 , 175, 0 , 6398 , 272, 130), // #1080
- INST(Vpaddb , VexRvm_Lx , V(660F00,FC,_,x,I,I,4,FVM), 0 , 175, 0 , 6408 , 272, 130), // #1081
- INST(Vpaddd , VexRvm_Lx , V(660F00,FE,_,x,I,0,4,FV ), 0 , 124, 0 , 6415 , 186, 116), // #1082
- INST(Vpaddq , VexRvm_Lx , V(660F00,D4,_,x,I,1,4,FV ), 0 , 93 , 0 , 6422 , 185, 116), // #1083
- INST(Vpaddsb , VexRvm_Lx , V(660F00,EC,_,x,I,I,4,FVM), 0 , 175, 0 , 6429 , 272, 130), // #1084
- INST(Vpaddsw , VexRvm_Lx , V(660F00,ED,_,x,I,I,4,FVM), 0 , 175, 0 , 6437 , 272, 130), // #1085
- INST(Vpaddusb , VexRvm_Lx , V(660F00,DC,_,x,I,I,4,FVM), 0 , 175, 0 , 6445 , 272, 130), // #1086
- INST(Vpaddusw , VexRvm_Lx , V(660F00,DD,_,x,I,I,4,FVM), 0 , 175, 0 , 6454 , 272, 130), // #1087
- INST(Vpaddw , VexRvm_Lx , V(660F00,FD,_,x,I,I,4,FVM), 0 , 175, 0 , 6463 , 272, 130), // #1088
- INST(Vpalignr , VexRvmi_Lx , V(660F3A,0F,_,x,I,I,4,FVM), 0 , 178, 0 , 6470 , 271, 130), // #1089
- INST(Vpand , VexRvm_Lx , V(660F00,DB,_,x,I,_,_,_ ), 0 , 63 , 0 , 6479 , 302, 128), // #1090
- INST(Vpandd , VexRvm_Lx , E(660F00,DB,_,x,_,0,4,FV ), 0 , 179, 0 , 6485 , 303, 111), // #1091
- INST(Vpandn , VexRvm_Lx , V(660F00,DF,_,x,I,_,_,_ ), 0 , 63 , 0 , 6492 , 304, 128), // #1092
- INST(Vpandnd , VexRvm_Lx , E(660F00,DF,_,x,_,0,4,FV ), 0 , 179, 0 , 6499 , 305, 111), // #1093
- INST(Vpandnq , VexRvm_Lx , E(660F00,DF,_,x,_,1,4,FV ), 0 , 121, 0 , 6507 , 306, 111), // #1094
- INST(Vpandq , VexRvm_Lx , E(660F00,DB,_,x,_,1,4,FV ), 0 , 121, 0 , 6515 , 307, 111), // #1095
- INST(Vpavgb , VexRvm_Lx , V(660F00,E0,_,x,I,I,4,FVM), 0 , 175, 0 , 6522 , 272, 130), // #1096
- INST(Vpavgw , VexRvm_Lx , V(660F00,E3,_,x,I,I,4,FVM), 0 , 175, 0 , 6529 , 272, 130), // #1097
- INST(Vpblendd , VexRvmi_Lx , V(660F3A,02,_,x,0,_,_,_ ), 0 , 67 , 0 , 6536 , 192, 115), // #1098
- INST(Vpblendvb , VexRvmr , V(660F3A,4C,_,x,0,_,_,_ ), 0 , 67 , 0 , 6545 , 193, 128), // #1099
- INST(Vpblendw , VexRvmi_Lx , V(660F3A,0E,_,x,I,_,_,_ ), 0 , 67 , 0 , 6555 , 192, 128), // #1100
- INST(Vpbroadcastb , VexRm_Lx_Bcst , V(660F38,78,_,x,0,0,0,T1S), E(660F38,7A,_,x,0,0,0,T1S), 180, 105, 6564 , 308, 131), // #1101
- INST(Vpbroadcastd , VexRm_Lx_Bcst , V(660F38,58,_,x,0,0,2,T1S), E(660F38,7C,_,x,0,0,0,T1S), 112, 106, 6577 , 309, 125), // #1102
- INST(Vpbroadcastmb2d , VexRm_Lx , E(F30F38,3A,_,x,_,0,_,_ ), 0 , 119, 0 , 6590 , 310, 132), // #1103
- INST(Vpbroadcastmb2q , VexRm_Lx , E(F30F38,2A,_,x,_,1,_,_ ), 0 , 181, 0 , 6606 , 310, 132), // #1104
- INST(Vpbroadcastq , VexRm_Lx_Bcst , V(660F38,59,_,x,0,1,3,T1S), E(660F38,7C,_,x,0,1,0,T1S), 111, 107, 6622 , 311, 125), // #1105
- INST(Vpbroadcastw , VexRm_Lx_Bcst , V(660F38,79,_,x,0,0,1,T1S), E(660F38,7B,_,x,0,0,0,T1S), 182, 108, 6635 , 312, 131), // #1106
- INST(Vpclmulqdq , VexRvmi_Lx , V(660F3A,44,_,x,I,_,4,FVM), 0 , 178, 0 , 6648 , 313, 133), // #1107
- INST(Vpcmov , VexRvrmRvmr_Lx , V(XOP_M8,A2,_,x,x,_,_,_ ), 0 , 183, 0 , 6659 , 250, 124), // #1108
- INST(Vpcmpb , VexRvmi_Lx , E(660F3A,3F,_,x,_,0,4,FVM), 0 , 142, 0 , 6666 , 314, 113), // #1109
- INST(Vpcmpd , VexRvmi_Lx , E(660F3A,1F,_,x,_,0,4,FV ), 0 , 99 , 0 , 6673 , 315, 111), // #1110
- INST(Vpcmpeqb , VexRvm_Lx , V(660F00,74,_,x,I,I,4,FV ), 0 , 124, 0 , 6680 , 316, 130), // #1111
- INST(Vpcmpeqd , VexRvm_Lx , V(660F00,76,_,x,I,0,4,FVM), 0 , 175, 0 , 6689 , 317, 116), // #1112
- INST(Vpcmpeqq , VexRvm_Lx , V(660F38,29,_,x,I,1,4,FVM), 0 , 184, 0 , 6698 , 318, 116), // #1113
- INST(Vpcmpeqw , VexRvm_Lx , V(660F00,75,_,x,I,I,4,FV ), 0 , 124, 0 , 6707 , 316, 130), // #1114
- INST(Vpcmpestri , VexRmi , V(660F3A,61,_,0,I,_,_,_ ), 0 , 67 , 0 , 6716 , 319, 134), // #1115
- INST(Vpcmpestrm , VexRmi , V(660F3A,60,_,0,I,_,_,_ ), 0 , 67 , 0 , 6727 , 320, 134), // #1116
- INST(Vpcmpgtb , VexRvm_Lx , V(660F00,64,_,x,I,I,4,FV ), 0 , 124, 0 , 6738 , 316, 130), // #1117
- INST(Vpcmpgtd , VexRvm_Lx , V(660F00,66,_,x,I,0,4,FVM), 0 , 175, 0 , 6747 , 317, 116), // #1118
- INST(Vpcmpgtq , VexRvm_Lx , V(660F38,37,_,x,I,1,4,FVM), 0 , 184, 0 , 6756 , 318, 116), // #1119
- INST(Vpcmpgtw , VexRvm_Lx , V(660F00,65,_,x,I,I,4,FV ), 0 , 124, 0 , 6765 , 316, 130), // #1120
- INST(Vpcmpistri , VexRmi , V(660F3A,63,_,0,I,_,_,_ ), 0 , 67 , 0 , 6774 , 321, 134), // #1121
- INST(Vpcmpistrm , VexRmi , V(660F3A,62,_,0,I,_,_,_ ), 0 , 67 , 0 , 6785 , 322, 134), // #1122
- INST(Vpcmpq , VexRvmi_Lx , E(660F3A,1F,_,x,_,1,4,FV ), 0 , 100, 0 , 6796 , 323, 111), // #1123
- INST(Vpcmpub , VexRvmi_Lx , E(660F3A,3E,_,x,_,0,4,FVM), 0 , 142, 0 , 6803 , 314, 113), // #1124
- INST(Vpcmpud , VexRvmi_Lx , E(660F3A,1E,_,x,_,0,4,FV ), 0 , 99 , 0 , 6811 , 315, 111), // #1125
- INST(Vpcmpuq , VexRvmi_Lx , E(660F3A,1E,_,x,_,1,4,FV ), 0 , 100, 0 , 6819 , 323, 111), // #1126
- INST(Vpcmpuw , VexRvmi_Lx , E(660F3A,3E,_,x,_,1,4,FVM), 0 , 185, 0 , 6827 , 323, 113), // #1127
- INST(Vpcmpw , VexRvmi_Lx , E(660F3A,3F,_,x,_,1,4,FVM), 0 , 185, 0 , 6835 , 323, 113), // #1128
- INST(Vpcomb , VexRvmi , V(XOP_M8,CC,_,0,0,_,_,_ ), 0 , 183, 0 , 6842 , 238, 124), // #1129
- INST(Vpcomd , VexRvmi , V(XOP_M8,CE,_,0,0,_,_,_ ), 0 , 183, 0 , 6849 , 238, 124), // #1130
- INST(Vpcompressb , VexMr_Lx , E(660F38,63,_,x,_,0,0,T1S), 0 , 186, 0 , 6856 , 207, 135), // #1131
- INST(Vpcompressd , VexMr_Lx , E(660F38,8B,_,x,_,0,2,T1S), 0 , 116, 0 , 6868 , 207, 111), // #1132
- INST(Vpcompressq , VexMr_Lx , E(660F38,8B,_,x,_,1,3,T1S), 0 , 115, 0 , 6880 , 207, 111), // #1133
- INST(Vpcompressw , VexMr_Lx , E(660F38,63,_,x,_,1,1,T1S), 0 , 187, 0 , 6892 , 207, 135), // #1134
- INST(Vpcomq , VexRvmi , V(XOP_M8,CF,_,0,0,_,_,_ ), 0 , 183, 0 , 6904 , 238, 124), // #1135
- INST(Vpcomub , VexRvmi , V(XOP_M8,EC,_,0,0,_,_,_ ), 0 , 183, 0 , 6911 , 238, 124), // #1136
- INST(Vpcomud , VexRvmi , V(XOP_M8,EE,_,0,0,_,_,_ ), 0 , 183, 0 , 6919 , 238, 124), // #1137
- INST(Vpcomuq , VexRvmi , V(XOP_M8,EF,_,0,0,_,_,_ ), 0 , 183, 0 , 6927 , 238, 124), // #1138
- INST(Vpcomuw , VexRvmi , V(XOP_M8,ED,_,0,0,_,_,_ ), 0 , 183, 0 , 6935 , 238, 124), // #1139
- INST(Vpcomw , VexRvmi , V(XOP_M8,CD,_,0,0,_,_,_ ), 0 , 183, 0 , 6943 , 238, 124), // #1140
- INST(Vpconflictd , VexRm_Lx , E(660F38,C4,_,x,_,0,4,FV ), 0 , 102, 0 , 6950 , 324, 132), // #1141
- INST(Vpconflictq , VexRm_Lx , E(660F38,C4,_,x,_,1,4,FV ), 0 , 103, 0 , 6962 , 324, 132), // #1142
- INST(Vpdpbusd , VexRvm_Lx , E(660F38,50,_,x,_,0,4,FV ), 0 , 102, 0 , 6974 , 190, 136), // #1143
- INST(Vpdpbusds , VexRvm_Lx , E(660F38,51,_,x,_,0,4,FV ), 0 , 102, 0 , 6983 , 190, 136), // #1144
- INST(Vpdpwssd , VexRvm_Lx , E(660F38,52,_,x,_,0,4,FV ), 0 , 102, 0 , 6993 , 190, 136), // #1145
- INST(Vpdpwssds , VexRvm_Lx , E(660F38,53,_,x,_,0,4,FV ), 0 , 102, 0 , 7002 , 190, 136), // #1146
- INST(Vperm2f128 , VexRvmi , V(660F3A,06,_,1,0,_,_,_ ), 0 , 145, 0 , 7012 , 325, 108), // #1147
- INST(Vperm2i128 , VexRvmi , V(660F3A,46,_,1,0,_,_,_ ), 0 , 145, 0 , 7023 , 325, 115), // #1148
- INST(Vpermb , VexRvm_Lx , E(660F38,8D,_,x,_,0,4,FVM), 0 , 101, 0 , 7034 , 189, 137), // #1149
- INST(Vpermd , VexRvm_Lx , V(660F38,36,_,x,0,0,4,FV ), 0 , 154, 0 , 7041 , 326, 125), // #1150
- INST(Vpermi2b , VexRvm_Lx , E(660F38,75,_,x,_,0,4,FVM), 0 , 101, 0 , 7048 , 189, 137), // #1151
- INST(Vpermi2d , VexRvm_Lx , E(660F38,76,_,x,_,0,4,FV ), 0 , 102, 0 , 7057 , 190, 111), // #1152
- INST(Vpermi2pd , VexRvm_Lx , E(660F38,77,_,x,_,1,4,FV ), 0 , 103, 0 , 7066 , 191, 111), // #1153
- INST(Vpermi2ps , VexRvm_Lx , E(660F38,77,_,x,_,0,4,FV ), 0 , 102, 0 , 7076 , 190, 111), // #1154
- INST(Vpermi2q , VexRvm_Lx , E(660F38,76,_,x,_,1,4,FV ), 0 , 103, 0 , 7086 , 191, 111), // #1155
- INST(Vpermi2w , VexRvm_Lx , E(660F38,75,_,x,_,1,4,FVM), 0 , 104, 0 , 7095 , 189, 113), // #1156
- INST(Vpermil2pd , VexRvrmiRvmri_Lx , V(660F3A,49,_,x,x,_,_,_ ), 0 , 67 , 0 , 7104 , 327, 124), // #1157
- INST(Vpermil2ps , VexRvrmiRvmri_Lx , V(660F3A,48,_,x,x,_,_,_ ), 0 , 67 , 0 , 7115 , 327, 124), // #1158
- INST(Vpermilpd , VexRvmRmi_Lx , V(660F38,0D,_,x,0,1,4,FV ), V(660F3A,05,_,x,0,1,4,FV ), 188, 109, 7126 , 328, 106), // #1159
- INST(Vpermilps , VexRvmRmi_Lx , V(660F38,0C,_,x,0,0,4,FV ), V(660F3A,04,_,x,0,0,4,FV ), 154, 110, 7136 , 328, 106), // #1160
- INST(Vpermpd , VexRvmRmi_Lx , E(660F38,16,_,x,1,1,4,FV ), V(660F3A,01,_,x,1,1,4,FV ), 189, 111, 7146 , 329, 125), // #1161
- INST(Vpermps , VexRvm_Lx , V(660F38,16,_,x,0,0,4,FV ), 0 , 154, 0 , 7154 , 326, 125), // #1162
- INST(Vpermq , VexRvmRmi_Lx , V(660F38,36,_,x,_,1,4,FV ), V(660F3A,00,_,x,1,1,4,FV ), 188, 112, 7162 , 329, 125), // #1163
- INST(Vpermt2b , VexRvm_Lx , E(660F38,7D,_,x,_,0,4,FVM), 0 , 101, 0 , 7169 , 189, 137), // #1164
- INST(Vpermt2d , VexRvm_Lx , E(660F38,7E,_,x,_,0,4,FV ), 0 , 102, 0 , 7178 , 190, 111), // #1165
- INST(Vpermt2pd , VexRvm_Lx , E(660F38,7F,_,x,_,1,4,FV ), 0 , 103, 0 , 7187 , 191, 111), // #1166
- INST(Vpermt2ps , VexRvm_Lx , E(660F38,7F,_,x,_,0,4,FV ), 0 , 102, 0 , 7197 , 190, 111), // #1167
- INST(Vpermt2q , VexRvm_Lx , E(660F38,7E,_,x,_,1,4,FV ), 0 , 103, 0 , 7207 , 191, 111), // #1168
- INST(Vpermt2w , VexRvm_Lx , E(660F38,7D,_,x,_,1,4,FVM), 0 , 104, 0 , 7216 , 189, 113), // #1169
- INST(Vpermw , VexRvm_Lx , E(660F38,8D,_,x,_,1,4,FVM), 0 , 104, 0 , 7225 , 189, 113), // #1170
- INST(Vpexpandb , VexRm_Lx , E(660F38,62,_,x,_,0,0,T1S), 0 , 186, 0 , 7232 , 241, 135), // #1171
- INST(Vpexpandd , VexRm_Lx , E(660F38,89,_,x,_,0,2,T1S), 0 , 116, 0 , 7242 , 241, 111), // #1172
- INST(Vpexpandq , VexRm_Lx , E(660F38,89,_,x,_,1,3,T1S), 0 , 115, 0 , 7252 , 241, 111), // #1173
- INST(Vpexpandw , VexRm_Lx , E(660F38,62,_,x,_,1,1,T1S), 0 , 187, 0 , 7262 , 241, 135), // #1174
- INST(Vpextrb , VexMri , V(660F3A,14,_,0,0,I,0,T1S), 0 , 190, 0 , 7272 , 330, 138), // #1175
- INST(Vpextrd , VexMri , V(660F3A,16,_,0,0,0,2,T1S), 0 , 150, 0 , 7280 , 245, 139), // #1176
- INST(Vpextrq , VexMri , V(660F3A,16,_,0,1,1,3,T1S), 0 , 191, 0 , 7288 , 331, 139), // #1177
- INST(Vpextrw , VexMri , V(660F3A,15,_,0,0,I,1,T1S), 0 , 192, 0 , 7296 , 332, 138), // #1178
- INST(Vpgatherdd , VexRmvRm_VM , V(660F38,90,_,x,0,_,_,_ ), V(660F38,90,_,x,_,0,2,T1S), 88 , 113, 7304 , 261, 125), // #1179
- INST(Vpgatherdq , VexRmvRm_VM , V(660F38,90,_,x,1,_,_,_ ), V(660F38,90,_,x,_,1,3,T1S), 156, 114, 7315 , 260, 125), // #1180
- INST(Vpgatherqd , VexRmvRm_VM , V(660F38,91,_,x,0,_,_,_ ), V(660F38,91,_,x,_,0,2,T1S), 88 , 115, 7326 , 266, 125), // #1181
- INST(Vpgatherqq , VexRmvRm_VM , V(660F38,91,_,x,1,_,_,_ ), V(660F38,91,_,x,_,1,3,T1S), 156, 116, 7337 , 265, 125), // #1182
- INST(Vphaddbd , VexRm , V(XOP_M9,C2,_,0,0,_,_,_ ), 0 , 72 , 0 , 7348 , 181, 124), // #1183
- INST(Vphaddbq , VexRm , V(XOP_M9,C3,_,0,0,_,_,_ ), 0 , 72 , 0 , 7357 , 181, 124), // #1184
- INST(Vphaddbw , VexRm , V(XOP_M9,C1,_,0,0,_,_,_ ), 0 , 72 , 0 , 7366 , 181, 124), // #1185
- INST(Vphaddd , VexRvm_Lx , V(660F38,02,_,x,I,_,_,_ ), 0 , 88 , 0 , 7375 , 179, 128), // #1186
- INST(Vphadddq , VexRm , V(XOP_M9,CB,_,0,0,_,_,_ ), 0 , 72 , 0 , 7383 , 181, 124), // #1187
- INST(Vphaddsw , VexRvm_Lx , V(660F38,03,_,x,I,_,_,_ ), 0 , 88 , 0 , 7392 , 179, 128), // #1188
- INST(Vphaddubd , VexRm , V(XOP_M9,D2,_,0,0,_,_,_ ), 0 , 72 , 0 , 7401 , 181, 124), // #1189
- INST(Vphaddubq , VexRm , V(XOP_M9,D3,_,0,0,_,_,_ ), 0 , 72 , 0 , 7411 , 181, 124), // #1190
- INST(Vphaddubw , VexRm , V(XOP_M9,D1,_,0,0,_,_,_ ), 0 , 72 , 0 , 7421 , 181, 124), // #1191
- INST(Vphaddudq , VexRm , V(XOP_M9,DB,_,0,0,_,_,_ ), 0 , 72 , 0 , 7431 , 181, 124), // #1192
- INST(Vphadduwd , VexRm , V(XOP_M9,D6,_,0,0,_,_,_ ), 0 , 72 , 0 , 7441 , 181, 124), // #1193
- INST(Vphadduwq , VexRm , V(XOP_M9,D7,_,0,0,_,_,_ ), 0 , 72 , 0 , 7451 , 181, 124), // #1194
- INST(Vphaddw , VexRvm_Lx , V(660F38,01,_,x,I,_,_,_ ), 0 , 88 , 0 , 7461 , 179, 128), // #1195
- INST(Vphaddwd , VexRm , V(XOP_M9,C6,_,0,0,_,_,_ ), 0 , 72 , 0 , 7469 , 181, 124), // #1196
- INST(Vphaddwq , VexRm , V(XOP_M9,C7,_,0,0,_,_,_ ), 0 , 72 , 0 , 7478 , 181, 124), // #1197
- INST(Vphminposuw , VexRm , V(660F38,41,_,0,I,_,_,_ ), 0 , 88 , 0 , 7487 , 181, 108), // #1198
- INST(Vphsubbw , VexRm , V(XOP_M9,E1,_,0,0,_,_,_ ), 0 , 72 , 0 , 7499 , 181, 124), // #1199
- INST(Vphsubd , VexRvm_Lx , V(660F38,06,_,x,I,_,_,_ ), 0 , 88 , 0 , 7508 , 179, 128), // #1200
- INST(Vphsubdq , VexRm , V(XOP_M9,E3,_,0,0,_,_,_ ), 0 , 72 , 0 , 7516 , 181, 124), // #1201
- INST(Vphsubsw , VexRvm_Lx , V(660F38,07,_,x,I,_,_,_ ), 0 , 88 , 0 , 7525 , 179, 128), // #1202
- INST(Vphsubw , VexRvm_Lx , V(660F38,05,_,x,I,_,_,_ ), 0 , 88 , 0 , 7534 , 179, 128), // #1203
- INST(Vphsubwd , VexRm , V(XOP_M9,E2,_,0,0,_,_,_ ), 0 , 72 , 0 , 7542 , 181, 124), // #1204
- INST(Vpinsrb , VexRvmi , V(660F3A,20,_,0,0,I,0,T1S), 0 , 190, 0 , 7551 , 333, 138), // #1205
- INST(Vpinsrd , VexRvmi , V(660F3A,22,_,0,0,0,2,T1S), 0 , 150, 0 , 7559 , 334, 139), // #1206
- INST(Vpinsrq , VexRvmi , V(660F3A,22,_,0,1,1,3,T1S), 0 , 191, 0 , 7567 , 335, 139), // #1207
- INST(Vpinsrw , VexRvmi , V(660F00,C4,_,0,0,I,1,T1S), 0 , 193, 0 , 7575 , 336, 138), // #1208
- INST(Vplzcntd , VexRm_Lx , E(660F38,44,_,x,_,0,4,FV ), 0 , 102, 0 , 7583 , 324, 132), // #1209
- INST(Vplzcntq , VexRm_Lx , E(660F38,44,_,x,_,1,4,FV ), 0 , 103, 0 , 7592 , 337, 132), // #1210
- INST(Vpmacsdd , VexRvmr , V(XOP_M8,9E,_,0,0,_,_,_ ), 0 , 183, 0 , 7601 , 338, 124), // #1211
- INST(Vpmacsdqh , VexRvmr , V(XOP_M8,9F,_,0,0,_,_,_ ), 0 , 183, 0 , 7610 , 338, 124), // #1212
- INST(Vpmacsdql , VexRvmr , V(XOP_M8,97,_,0,0,_,_,_ ), 0 , 183, 0 , 7620 , 338, 124), // #1213
- INST(Vpmacssdd , VexRvmr , V(XOP_M8,8E,_,0,0,_,_,_ ), 0 , 183, 0 , 7630 , 338, 124), // #1214
- INST(Vpmacssdqh , VexRvmr , V(XOP_M8,8F,_,0,0,_,_,_ ), 0 , 183, 0 , 7640 , 338, 124), // #1215
- INST(Vpmacssdql , VexRvmr , V(XOP_M8,87,_,0,0,_,_,_ ), 0 , 183, 0 , 7651 , 338, 124), // #1216
- INST(Vpmacsswd , VexRvmr , V(XOP_M8,86,_,0,0,_,_,_ ), 0 , 183, 0 , 7662 , 338, 124), // #1217
- INST(Vpmacssww , VexRvmr , V(XOP_M8,85,_,0,0,_,_,_ ), 0 , 183, 0 , 7672 , 338, 124), // #1218
- INST(Vpmacswd , VexRvmr , V(XOP_M8,96,_,0,0,_,_,_ ), 0 , 183, 0 , 7682 , 338, 124), // #1219
- INST(Vpmacsww , VexRvmr , V(XOP_M8,95,_,0,0,_,_,_ ), 0 , 183, 0 , 7691 , 338, 124), // #1220
- INST(Vpmadcsswd , VexRvmr , V(XOP_M8,A6,_,0,0,_,_,_ ), 0 , 183, 0 , 7700 , 338, 124), // #1221
- INST(Vpmadcswd , VexRvmr , V(XOP_M8,B6,_,0,0,_,_,_ ), 0 , 183, 0 , 7711 , 338, 124), // #1222
- INST(Vpmadd52huq , VexRvm_Lx , E(660F38,B5,_,x,_,1,4,FV ), 0 , 103, 0 , 7721 , 191, 140), // #1223
- INST(Vpmadd52luq , VexRvm_Lx , E(660F38,B4,_,x,_,1,4,FV ), 0 , 103, 0 , 7733 , 191, 140), // #1224
- INST(Vpmaddubsw , VexRvm_Lx , V(660F38,04,_,x,I,I,4,FVM), 0 , 98 , 0 , 7745 , 272, 130), // #1225
- INST(Vpmaddwd , VexRvm_Lx , V(660F00,F5,_,x,I,I,4,FVM), 0 , 175, 0 , 7756 , 272, 130), // #1226
- INST(Vpmaskmovd , VexRvmMvr_Lx , V(660F38,8C,_,x,0,_,_,_ ), V(660F38,8E,_,x,0,_,_,_ ), 88 , 117, 7765 , 280, 115), // #1227
- INST(Vpmaskmovq , VexRvmMvr_Lx , V(660F38,8C,_,x,1,_,_,_ ), V(660F38,8E,_,x,1,_,_,_ ), 156, 118, 7776 , 280, 115), // #1228
- INST(Vpmaxsb , VexRvm_Lx , V(660F38,3C,_,x,I,I,4,FVM), 0 , 98 , 0 , 7787 , 339, 130), // #1229
- INST(Vpmaxsd , VexRvm_Lx , V(660F38,3D,_,x,I,0,4,FV ), 0 , 154, 0 , 7795 , 188, 116), // #1230
- INST(Vpmaxsq , VexRvm_Lx , E(660F38,3D,_,x,_,1,4,FV ), 0 , 103, 0 , 7803 , 191, 111), // #1231
- INST(Vpmaxsw , VexRvm_Lx , V(660F00,EE,_,x,I,I,4,FVM), 0 , 175, 0 , 7811 , 339, 130), // #1232
- INST(Vpmaxub , VexRvm_Lx , V(660F00,DE,_,x,I,I,4,FVM), 0 , 175, 0 , 7819 , 339, 130), // #1233
- INST(Vpmaxud , VexRvm_Lx , V(660F38,3F,_,x,I,0,4,FV ), 0 , 154, 0 , 7827 , 188, 116), // #1234
- INST(Vpmaxuq , VexRvm_Lx , E(660F38,3F,_,x,_,1,4,FV ), 0 , 103, 0 , 7835 , 191, 111), // #1235
- INST(Vpmaxuw , VexRvm_Lx , V(660F38,3E,_,x,I,I,4,FVM), 0 , 98 , 0 , 7843 , 339, 130), // #1236
- INST(Vpminsb , VexRvm_Lx , V(660F38,38,_,x,I,I,4,FVM), 0 , 98 , 0 , 7851 , 339, 130), // #1237
- INST(Vpminsd , VexRvm_Lx , V(660F38,39,_,x,I,0,4,FV ), 0 , 154, 0 , 7859 , 188, 116), // #1238
- INST(Vpminsq , VexRvm_Lx , E(660F38,39,_,x,_,1,4,FV ), 0 , 103, 0 , 7867 , 191, 111), // #1239
- INST(Vpminsw , VexRvm_Lx , V(660F00,EA,_,x,I,I,4,FVM), 0 , 175, 0 , 7875 , 339, 130), // #1240
- INST(Vpminub , VexRvm_Lx , V(660F00,DA,_,x,I,_,4,FVM), 0 , 175, 0 , 7883 , 339, 130), // #1241
- INST(Vpminud , VexRvm_Lx , V(660F38,3B,_,x,I,0,4,FV ), 0 , 154, 0 , 7891 , 188, 116), // #1242
- INST(Vpminuq , VexRvm_Lx , E(660F38,3B,_,x,_,1,4,FV ), 0 , 103, 0 , 7899 , 191, 111), // #1243
- INST(Vpminuw , VexRvm_Lx , V(660F38,3A,_,x,I,_,4,FVM), 0 , 98 , 0 , 7907 , 339, 130), // #1244
- INST(Vpmovb2m , VexRm_Lx , E(F30F38,29,_,x,_,0,_,_ ), 0 , 119, 0 , 7915 , 340, 113), // #1245
- INST(Vpmovd2m , VexRm_Lx , E(F30F38,39,_,x,_,0,_,_ ), 0 , 119, 0 , 7924 , 340, 114), // #1246
- INST(Vpmovdb , VexMr_Lx , E(F30F38,31,_,x,_,0,2,QVM), 0 , 194, 0 , 7933 , 341, 111), // #1247
- INST(Vpmovdw , VexMr_Lx , E(F30F38,33,_,x,_,0,3,HVM), 0 , 195, 0 , 7941 , 342, 111), // #1248
- INST(Vpmovm2b , VexRm_Lx , E(F30F38,28,_,x,_,0,_,_ ), 0 , 119, 0 , 7949 , 310, 113), // #1249
- INST(Vpmovm2d , VexRm_Lx , E(F30F38,38,_,x,_,0,_,_ ), 0 , 119, 0 , 7958 , 310, 114), // #1250
- INST(Vpmovm2q , VexRm_Lx , E(F30F38,38,_,x,_,1,_,_ ), 0 , 181, 0 , 7967 , 310, 114), // #1251
- INST(Vpmovm2w , VexRm_Lx , E(F30F38,28,_,x,_,1,_,_ ), 0 , 181, 0 , 7976 , 310, 113), // #1252
- INST(Vpmovmskb , VexRm_Lx , V(660F00,D7,_,x,I,_,_,_ ), 0 , 63 , 0 , 7985 , 293, 128), // #1253
- INST(Vpmovq2m , VexRm_Lx , E(F30F38,39,_,x,_,1,_,_ ), 0 , 181, 0 , 7995 , 340, 114), // #1254
- INST(Vpmovqb , VexMr_Lx , E(F30F38,32,_,x,_,0,1,OVM), 0 , 196, 0 , 8004 , 343, 111), // #1255
- INST(Vpmovqd , VexMr_Lx , E(F30F38,35,_,x,_,0,3,HVM), 0 , 195, 0 , 8012 , 342, 111), // #1256
- INST(Vpmovqw , VexMr_Lx , E(F30F38,34,_,x,_,0,2,QVM), 0 , 194, 0 , 8020 , 341, 111), // #1257
- INST(Vpmovsdb , VexMr_Lx , E(F30F38,21,_,x,_,0,2,QVM), 0 , 194, 0 , 8028 , 341, 111), // #1258
- INST(Vpmovsdw , VexMr_Lx , E(F30F38,23,_,x,_,0,3,HVM), 0 , 195, 0 , 8037 , 342, 111), // #1259
- INST(Vpmovsqb , VexMr_Lx , E(F30F38,22,_,x,_,0,1,OVM), 0 , 196, 0 , 8046 , 343, 111), // #1260
- INST(Vpmovsqd , VexMr_Lx , E(F30F38,25,_,x,_,0,3,HVM), 0 , 195, 0 , 8055 , 342, 111), // #1261
- INST(Vpmovsqw , VexMr_Lx , E(F30F38,24,_,x,_,0,2,QVM), 0 , 194, 0 , 8064 , 341, 111), // #1262
- INST(Vpmovswb , VexMr_Lx , E(F30F38,20,_,x,_,0,3,HVM), 0 , 195, 0 , 8073 , 342, 113), // #1263
- INST(Vpmovsxbd , VexRm_Lx , V(660F38,21,_,x,I,I,2,QVM), 0 , 197, 0 , 8082 , 344, 116), // #1264
- INST(Vpmovsxbq , VexRm_Lx , V(660F38,22,_,x,I,I,1,OVM), 0 , 198, 0 , 8092 , 345, 116), // #1265
- INST(Vpmovsxbw , VexRm_Lx , V(660F38,20,_,x,I,I,3,HVM), 0 , 123, 0 , 8102 , 346, 130), // #1266
- INST(Vpmovsxdq , VexRm_Lx , V(660F38,25,_,x,I,0,3,HVM), 0 , 123, 0 , 8112 , 346, 116), // #1267
- INST(Vpmovsxwd , VexRm_Lx , V(660F38,23,_,x,I,I,3,HVM), 0 , 123, 0 , 8122 , 346, 116), // #1268
- INST(Vpmovsxwq , VexRm_Lx , V(660F38,24,_,x,I,I,2,QVM), 0 , 197, 0 , 8132 , 344, 116), // #1269
- INST(Vpmovusdb , VexMr_Lx , E(F30F38,11,_,x,_,0,2,QVM), 0 , 194, 0 , 8142 , 341, 111), // #1270
- INST(Vpmovusdw , VexMr_Lx , E(F30F38,13,_,x,_,0,3,HVM), 0 , 195, 0 , 8152 , 342, 111), // #1271
- INST(Vpmovusqb , VexMr_Lx , E(F30F38,12,_,x,_,0,1,OVM), 0 , 196, 0 , 8162 , 343, 111), // #1272
- INST(Vpmovusqd , VexMr_Lx , E(F30F38,15,_,x,_,0,3,HVM), 0 , 195, 0 , 8172 , 342, 111), // #1273
- INST(Vpmovusqw , VexMr_Lx , E(F30F38,14,_,x,_,0,2,QVM), 0 , 194, 0 , 8182 , 341, 111), // #1274
- INST(Vpmovuswb , VexMr_Lx , E(F30F38,10,_,x,_,0,3,HVM), 0 , 195, 0 , 8192 , 342, 113), // #1275
- INST(Vpmovw2m , VexRm_Lx , E(F30F38,29,_,x,_,1,_,_ ), 0 , 181, 0 , 8202 , 340, 113), // #1276
- INST(Vpmovwb , VexMr_Lx , E(F30F38,30,_,x,_,0,3,HVM), 0 , 195, 0 , 8211 , 342, 113), // #1277
- INST(Vpmovzxbd , VexRm_Lx , V(660F38,31,_,x,I,I,2,QVM), 0 , 197, 0 , 8219 , 344, 116), // #1278
- INST(Vpmovzxbq , VexRm_Lx , V(660F38,32,_,x,I,I,1,OVM), 0 , 198, 0 , 8229 , 345, 116), // #1279
- INST(Vpmovzxbw , VexRm_Lx , V(660F38,30,_,x,I,I,3,HVM), 0 , 123, 0 , 8239 , 346, 130), // #1280
- INST(Vpmovzxdq , VexRm_Lx , V(660F38,35,_,x,I,0,3,HVM), 0 , 123, 0 , 8249 , 346, 116), // #1281
- INST(Vpmovzxwd , VexRm_Lx , V(660F38,33,_,x,I,I,3,HVM), 0 , 123, 0 , 8259 , 346, 116), // #1282
- INST(Vpmovzxwq , VexRm_Lx , V(660F38,34,_,x,I,I,2,QVM), 0 , 197, 0 , 8269 , 344, 116), // #1283
- INST(Vpmuldq , VexRvm_Lx , V(660F38,28,_,x,I,1,4,FV ), 0 , 188, 0 , 8279 , 185, 116), // #1284
- INST(Vpmulhrsw , VexRvm_Lx , V(660F38,0B,_,x,I,I,4,FVM), 0 , 98 , 0 , 8287 , 272, 130), // #1285
- INST(Vpmulhuw , VexRvm_Lx , V(660F00,E4,_,x,I,I,4,FVM), 0 , 175, 0 , 8297 , 272, 130), // #1286
- INST(Vpmulhw , VexRvm_Lx , V(660F00,E5,_,x,I,I,4,FVM), 0 , 175, 0 , 8306 , 272, 130), // #1287
- INST(Vpmulld , VexRvm_Lx , V(660F38,40,_,x,I,0,4,FV ), 0 , 154, 0 , 8314 , 186, 116), // #1288
- INST(Vpmullq , VexRvm_Lx , E(660F38,40,_,x,_,1,4,FV ), 0 , 103, 0 , 8322 , 191, 114), // #1289
- INST(Vpmullw , VexRvm_Lx , V(660F00,D5,_,x,I,I,4,FVM), 0 , 175, 0 , 8330 , 272, 130), // #1290
- INST(Vpmultishiftqb , VexRvm_Lx , E(660F38,83,_,x,_,1,4,FV ), 0 , 103, 0 , 8338 , 191, 137), // #1291
- INST(Vpmuludq , VexRvm_Lx , V(660F00,F4,_,x,I,1,4,FV ), 0 , 93 , 0 , 8353 , 185, 116), // #1292
- INST(Vpopcntb , VexRm_Lx , E(660F38,54,_,x,_,0,4,FV ), 0 , 102, 0 , 8362 , 241, 141), // #1293
- INST(Vpopcntd , VexRm_Lx , E(660F38,55,_,x,_,0,4,FVM), 0 , 101, 0 , 8371 , 324, 142), // #1294
- INST(Vpopcntq , VexRm_Lx , E(660F38,55,_,x,_,1,4,FVM), 0 , 104, 0 , 8380 , 337, 142), // #1295
- INST(Vpopcntw , VexRm_Lx , E(660F38,54,_,x,_,1,4,FV ), 0 , 103, 0 , 8389 , 241, 141), // #1296
- INST(Vpor , VexRvm_Lx , V(660F00,EB,_,x,I,_,_,_ ), 0 , 63 , 0 , 8398 , 302, 128), // #1297
- INST(Vpord , VexRvm_Lx , E(660F00,EB,_,x,_,0,4,FV ), 0 , 179, 0 , 8403 , 303, 111), // #1298
- INST(Vporq , VexRvm_Lx , E(660F00,EB,_,x,_,1,4,FV ), 0 , 121, 0 , 8409 , 307, 111), // #1299
- INST(Vpperm , VexRvrmRvmr , V(XOP_M8,A3,_,0,x,_,_,_ ), 0 , 183, 0 , 8415 , 347, 124), // #1300
- INST(Vprold , VexVmi_Lx , E(660F00,72,1,x,_,0,4,FV ), 0 , 199, 0 , 8422 , 348, 111), // #1301
- INST(Vprolq , VexVmi_Lx , E(660F00,72,1,x,_,1,4,FV ), 0 , 200, 0 , 8429 , 349, 111), // #1302
- INST(Vprolvd , VexRvm_Lx , E(660F38,15,_,x,_,0,4,FV ), 0 , 102, 0 , 8436 , 190, 111), // #1303
- INST(Vprolvq , VexRvm_Lx , E(660F38,15,_,x,_,1,4,FV ), 0 , 103, 0 , 8444 , 191, 111), // #1304
- INST(Vprord , VexVmi_Lx , E(660F00,72,0,x,_,0,4,FV ), 0 , 179, 0 , 8452 , 348, 111), // #1305
- INST(Vprorq , VexVmi_Lx , E(660F00,72,0,x,_,1,4,FV ), 0 , 121, 0 , 8459 , 349, 111), // #1306
- INST(Vprorvd , VexRvm_Lx , E(660F38,14,_,x,_,0,4,FV ), 0 , 102, 0 , 8466 , 190, 111), // #1307
- INST(Vprorvq , VexRvm_Lx , E(660F38,14,_,x,_,1,4,FV ), 0 , 103, 0 , 8474 , 191, 111), // #1308
- INST(Vprotb , VexRvmRmvRmi , V(XOP_M9,90,_,0,x,_,_,_ ), V(XOP_M8,C0,_,0,x,_,_,_ ), 72 , 119, 8482 , 350, 124), // #1309
- INST(Vprotd , VexRvmRmvRmi , V(XOP_M9,92,_,0,x,_,_,_ ), V(XOP_M8,C2,_,0,x,_,_,_ ), 72 , 120, 8489 , 350, 124), // #1310
- INST(Vprotq , VexRvmRmvRmi , V(XOP_M9,93,_,0,x,_,_,_ ), V(XOP_M8,C3,_,0,x,_,_,_ ), 72 , 121, 8496 , 350, 124), // #1311
- INST(Vprotw , VexRvmRmvRmi , V(XOP_M9,91,_,0,x,_,_,_ ), V(XOP_M8,C1,_,0,x,_,_,_ ), 72 , 122, 8503 , 350, 124), // #1312
- INST(Vpsadbw , VexRvm_Lx , V(660F00,F6,_,x,I,I,4,FVM), 0 , 175, 0 , 8510 , 180, 130), // #1313
- INST(Vpscatterdd , VexMr_VM , E(660F38,A0,_,x,_,0,2,T1S), 0 , 116, 0 , 8518 , 351, 111), // #1314
- INST(Vpscatterdq , VexMr_VM , E(660F38,A0,_,x,_,1,3,T1S), 0 , 115, 0 , 8530 , 351, 111), // #1315
- INST(Vpscatterqd , VexMr_VM , E(660F38,A1,_,x,_,0,2,T1S), 0 , 116, 0 , 8542 , 352, 111), // #1316
- INST(Vpscatterqq , VexMr_VM , E(660F38,A1,_,x,_,1,3,T1S), 0 , 115, 0 , 8554 , 353, 111), // #1317
- INST(Vpshab , VexRvmRmv , V(XOP_M9,98,_,0,x,_,_,_ ), 0 , 72 , 0 , 8566 , 354, 124), // #1318
- INST(Vpshad , VexRvmRmv , V(XOP_M9,9A,_,0,x,_,_,_ ), 0 , 72 , 0 , 8573 , 354, 124), // #1319
- INST(Vpshaq , VexRvmRmv , V(XOP_M9,9B,_,0,x,_,_,_ ), 0 , 72 , 0 , 8580 , 354, 124), // #1320
- INST(Vpshaw , VexRvmRmv , V(XOP_M9,99,_,0,x,_,_,_ ), 0 , 72 , 0 , 8587 , 354, 124), // #1321
- INST(Vpshlb , VexRvmRmv , V(XOP_M9,94,_,0,x,_,_,_ ), 0 , 72 , 0 , 8594 , 354, 124), // #1322
- INST(Vpshld , VexRvmRmv , V(XOP_M9,96,_,0,x,_,_,_ ), 0 , 72 , 0 , 8601 , 354, 124), // #1323
- INST(Vpshldd , VexRvmi_Lx , E(660F3A,71,_,x,_,0,4,FV ), 0 , 99 , 0 , 8608 , 183, 135), // #1324
- INST(Vpshldq , VexRvmi_Lx , E(660F3A,71,_,x,_,1,4,FV ), 0 , 100, 0 , 8616 , 184, 135), // #1325
- INST(Vpshldvd , VexRvm_Lx , E(660F38,71,_,x,_,0,4,FV ), 0 , 102, 0 , 8624 , 190, 135), // #1326
- INST(Vpshldvq , VexRvm_Lx , E(660F38,71,_,x,_,1,4,FV ), 0 , 103, 0 , 8633 , 191, 135), // #1327
- INST(Vpshldvw , VexRvm_Lx , E(660F38,70,_,x,_,0,4,FVM), 0 , 101, 0 , 8642 , 189, 135), // #1328
- INST(Vpshldw , VexRvmi_Lx , E(660F3A,70,_,x,_,0,4,FVM), 0 , 142, 0 , 8651 , 237, 135), // #1329
- INST(Vpshlq , VexRvmRmv , V(XOP_M9,97,_,0,x,_,_,_ ), 0 , 72 , 0 , 8659 , 354, 124), // #1330
- INST(Vpshlw , VexRvmRmv , V(XOP_M9,95,_,0,x,_,_,_ ), 0 , 72 , 0 , 8666 , 354, 124), // #1331
- INST(Vpshrdd , VexRvmi_Lx , E(660F3A,73,_,x,_,0,4,FV ), 0 , 99 , 0 , 8673 , 183, 135), // #1332
- INST(Vpshrdq , VexRvmi_Lx , E(660F3A,73,_,x,_,1,4,FV ), 0 , 100, 0 , 8681 , 184, 135), // #1333
- INST(Vpshrdvd , VexRvm_Lx , E(660F38,73,_,x,_,0,4,FV ), 0 , 102, 0 , 8689 , 190, 135), // #1334
- INST(Vpshrdvq , VexRvm_Lx , E(660F38,73,_,x,_,1,4,FV ), 0 , 103, 0 , 8698 , 191, 135), // #1335
- INST(Vpshrdvw , VexRvm_Lx , E(660F38,72,_,x,_,0,4,FVM), 0 , 101, 0 , 8707 , 189, 135), // #1336
- INST(Vpshrdw , VexRvmi_Lx , E(660F3A,72,_,x,_,0,4,FVM), 0 , 142, 0 , 8716 , 237, 135), // #1337
- INST(Vpshufb , VexRvm_Lx , V(660F38,00,_,x,I,I,4,FVM), 0 , 98 , 0 , 8724 , 272, 130), // #1338
- INST(Vpshufbitqmb , VexRvm_Lx , E(660F38,8F,_,x,0,0,4,FVM), 0 , 101, 0 , 8732 , 355, 141), // #1339
- INST(Vpshufd , VexRmi_Lx , V(660F00,70,_,x,I,0,4,FV ), 0 , 124, 0 , 8745 , 356, 116), // #1340
- INST(Vpshufhw , VexRmi_Lx , V(F30F00,70,_,x,I,I,4,FVM), 0 , 176, 0 , 8753 , 357, 130), // #1341
- INST(Vpshuflw , VexRmi_Lx , V(F20F00,70,_,x,I,I,4,FVM), 0 , 201, 0 , 8762 , 357, 130), // #1342
- INST(Vpsignb , VexRvm_Lx , V(660F38,08,_,x,I,_,_,_ ), 0 , 88 , 0 , 8771 , 179, 128), // #1343
- INST(Vpsignd , VexRvm_Lx , V(660F38,0A,_,x,I,_,_,_ ), 0 , 88 , 0 , 8779 , 179, 128), // #1344
- INST(Vpsignw , VexRvm_Lx , V(660F38,09,_,x,I,_,_,_ ), 0 , 88 , 0 , 8787 , 179, 128), // #1345
- INST(Vpslld , VexRvmVmi_Lx , V(660F00,F2,_,x,I,0,4,128), V(660F00,72,6,x,I,0,4,FV ), 202, 123, 8795 , 358, 116), // #1346
- INST(Vpslldq , VexEvexVmi_Lx , V(660F00,73,7,x,I,I,4,FVM), 0 , 203, 0 , 8802 , 359, 130), // #1347
- INST(Vpsllq , VexRvmVmi_Lx , V(660F00,F3,_,x,I,1,4,128), V(660F00,73,6,x,I,1,4,FV ), 204, 124, 8810 , 360, 116), // #1348
- INST(Vpsllvd , VexRvm_Lx , V(660F38,47,_,x,0,0,4,FV ), 0 , 154, 0 , 8817 , 186, 125), // #1349
- INST(Vpsllvq , VexRvm_Lx , V(660F38,47,_,x,1,1,4,FV ), 0 , 153, 0 , 8825 , 185, 125), // #1350
- INST(Vpsllvw , VexRvm_Lx , E(660F38,12,_,x,_,1,4,FVM), 0 , 104, 0 , 8833 , 189, 113), // #1351
- INST(Vpsllw , VexRvmVmi_Lx , V(660F00,F1,_,x,I,I,4,FVM), V(660F00,71,6,x,I,I,4,FVM), 175, 125, 8841 , 361, 130), // #1352
- INST(Vpsrad , VexRvmVmi_Lx , V(660F00,E2,_,x,I,0,4,128), V(660F00,72,4,x,I,0,4,FV ), 202, 126, 8848 , 358, 116), // #1353
- INST(Vpsraq , VexRvmVmi_Lx , E(660F00,E2,_,x,_,1,4,128), E(660F00,72,4,x,_,1,4,FV ), 205, 127, 8855 , 362, 111), // #1354
- INST(Vpsravd , VexRvm_Lx , V(660F38,46,_,x,0,0,4,FV ), 0 , 154, 0 , 8862 , 186, 125), // #1355
- INST(Vpsravq , VexRvm_Lx , E(660F38,46,_,x,_,1,4,FV ), 0 , 103, 0 , 8870 , 191, 111), // #1356
- INST(Vpsravw , VexRvm_Lx , E(660F38,11,_,x,_,1,4,FVM), 0 , 104, 0 , 8878 , 189, 113), // #1357
- INST(Vpsraw , VexRvmVmi_Lx , V(660F00,E1,_,x,I,I,4,128), V(660F00,71,4,x,I,I,4,FVM), 202, 128, 8886 , 361, 130), // #1358
- INST(Vpsrld , VexRvmVmi_Lx , V(660F00,D2,_,x,I,0,4,128), V(660F00,72,2,x,I,0,4,FV ), 202, 129, 8893 , 358, 116), // #1359
- INST(Vpsrldq , VexEvexVmi_Lx , V(660F00,73,3,x,I,I,4,FVM), 0 , 206, 0 , 8900 , 359, 130), // #1360
- INST(Vpsrlq , VexRvmVmi_Lx , V(660F00,D3,_,x,I,1,4,128), V(660F00,73,2,x,I,1,4,FV ), 204, 130, 8908 , 360, 116), // #1361
- INST(Vpsrlvd , VexRvm_Lx , V(660F38,45,_,x,0,0,4,FV ), 0 , 154, 0 , 8915 , 186, 125), // #1362
- INST(Vpsrlvq , VexRvm_Lx , V(660F38,45,_,x,1,1,4,FV ), 0 , 153, 0 , 8923 , 185, 125), // #1363
- INST(Vpsrlvw , VexRvm_Lx , E(660F38,10,_,x,_,1,4,FVM), 0 , 104, 0 , 8931 , 189, 113), // #1364
- INST(Vpsrlw , VexRvmVmi_Lx , V(660F00,D1,_,x,I,I,4,128), V(660F00,71,2,x,I,I,4,FVM), 202, 131, 8939 , 361, 130), // #1365
- INST(Vpsubb , VexRvm_Lx , V(660F00,F8,_,x,I,I,4,FVM), 0 , 175, 0 , 8946 , 363, 130), // #1366
- INST(Vpsubd , VexRvm_Lx , V(660F00,FA,_,x,I,0,4,FV ), 0 , 124, 0 , 8953 , 364, 116), // #1367
- INST(Vpsubq , VexRvm_Lx , V(660F00,FB,_,x,I,1,4,FV ), 0 , 93 , 0 , 8960 , 365, 116), // #1368
- INST(Vpsubsb , VexRvm_Lx , V(660F00,E8,_,x,I,I,4,FVM), 0 , 175, 0 , 8967 , 363, 130), // #1369
- INST(Vpsubsw , VexRvm_Lx , V(660F00,E9,_,x,I,I,4,FVM), 0 , 175, 0 , 8975 , 363, 130), // #1370
- INST(Vpsubusb , VexRvm_Lx , V(660F00,D8,_,x,I,I,4,FVM), 0 , 175, 0 , 8983 , 363, 130), // #1371
- INST(Vpsubusw , VexRvm_Lx , V(660F00,D9,_,x,I,I,4,FVM), 0 , 175, 0 , 8992 , 363, 130), // #1372
- INST(Vpsubw , VexRvm_Lx , V(660F00,F9,_,x,I,I,4,FVM), 0 , 175, 0 , 9001 , 363, 130), // #1373
- INST(Vpternlogd , VexRvmi_Lx , E(660F3A,25,_,x,_,0,4,FV ), 0 , 99 , 0 , 9008 , 183, 111), // #1374
- INST(Vpternlogq , VexRvmi_Lx , E(660F3A,25,_,x,_,1,4,FV ), 0 , 100, 0 , 9019 , 184, 111), // #1375
- INST(Vptest , VexRm_Lx , V(660F38,17,_,x,I,_,_,_ ), 0 , 88 , 0 , 9030 , 257, 134), // #1376
- INST(Vptestmb , VexRvm_Lx , E(660F38,26,_,x,_,0,4,FVM), 0 , 101, 0 , 9037 , 355, 113), // #1377
- INST(Vptestmd , VexRvm_Lx , E(660F38,27,_,x,_,0,4,FV ), 0 , 102, 0 , 9046 , 366, 111), // #1378
- INST(Vptestmq , VexRvm_Lx , E(660F38,27,_,x,_,1,4,FV ), 0 , 103, 0 , 9055 , 367, 111), // #1379
- INST(Vptestmw , VexRvm_Lx , E(660F38,26,_,x,_,1,4,FVM), 0 , 104, 0 , 9064 , 355, 113), // #1380
- INST(Vptestnmb , VexRvm_Lx , E(F30F38,26,_,x,_,0,4,FVM), 0 , 207, 0 , 9073 , 355, 113), // #1381
- INST(Vptestnmd , VexRvm_Lx , E(F30F38,27,_,x,_,0,4,FV ), 0 , 208, 0 , 9083 , 366, 111), // #1382
- INST(Vptestnmq , VexRvm_Lx , E(F30F38,27,_,x,_,1,4,FV ), 0 , 209, 0 , 9093 , 367, 111), // #1383
- INST(Vptestnmw , VexRvm_Lx , E(F30F38,26,_,x,_,1,4,FVM), 0 , 210, 0 , 9103 , 355, 113), // #1384
- INST(Vpunpckhbw , VexRvm_Lx , V(660F00,68,_,x,I,I,4,FVM), 0 , 175, 0 , 9113 , 272, 130), // #1385
- INST(Vpunpckhdq , VexRvm_Lx , V(660F00,6A,_,x,I,0,4,FV ), 0 , 124, 0 , 9124 , 186, 116), // #1386
- INST(Vpunpckhqdq , VexRvm_Lx , V(660F00,6D,_,x,I,1,4,FV ), 0 , 93 , 0 , 9135 , 185, 116), // #1387
- INST(Vpunpckhwd , VexRvm_Lx , V(660F00,69,_,x,I,I,4,FVM), 0 , 175, 0 , 9147 , 272, 130), // #1388
- INST(Vpunpcklbw , VexRvm_Lx , V(660F00,60,_,x,I,I,4,FVM), 0 , 175, 0 , 9158 , 272, 130), // #1389
- INST(Vpunpckldq , VexRvm_Lx , V(660F00,62,_,x,I,0,4,FV ), 0 , 124, 0 , 9169 , 186, 116), // #1390
- INST(Vpunpcklqdq , VexRvm_Lx , V(660F00,6C,_,x,I,1,4,FV ), 0 , 93 , 0 , 9180 , 185, 116), // #1391
- INST(Vpunpcklwd , VexRvm_Lx , V(660F00,61,_,x,I,I,4,FVM), 0 , 175, 0 , 9192 , 272, 130), // #1392
- INST(Vpxor , VexRvm_Lx , V(660F00,EF,_,x,I,_,_,_ ), 0 , 63 , 0 , 9203 , 304, 128), // #1393
- INST(Vpxord , VexRvm_Lx , E(660F00,EF,_,x,_,0,4,FV ), 0 , 179, 0 , 9209 , 305, 111), // #1394
- INST(Vpxorq , VexRvm_Lx , E(660F00,EF,_,x,_,1,4,FV ), 0 , 121, 0 , 9216 , 306, 111), // #1395
- INST(Vrangepd , VexRvmi_Lx , E(660F3A,50,_,x,_,1,4,FV ), 0 , 100, 0 , 9223 , 246, 114), // #1396
- INST(Vrangeps , VexRvmi_Lx , E(660F3A,50,_,x,_,0,4,FV ), 0 , 99 , 0 , 9232 , 247, 114), // #1397
- INST(Vrangesd , VexRvmi , E(660F3A,51,_,I,_,1,3,T1S), 0 , 151, 0 , 9241 , 248, 61 ), // #1398
- INST(Vrangess , VexRvmi , E(660F3A,51,_,I,_,0,2,T1S), 0 , 152, 0 , 9250 , 249, 61 ), // #1399
- INST(Vrcp14pd , VexRm_Lx , E(660F38,4C,_,x,_,1,4,FV ), 0 , 103, 0 , 9259 , 337, 111), // #1400
- INST(Vrcp14ps , VexRm_Lx , E(660F38,4C,_,x,_,0,4,FV ), 0 , 102, 0 , 9268 , 324, 111), // #1401
- INST(Vrcp14sd , VexRvm , E(660F38,4D,_,I,_,1,3,T1S), 0 , 115, 0 , 9277 , 368, 63 ), // #1402
- INST(Vrcp14ss , VexRvm , E(660F38,4D,_,I,_,0,2,T1S), 0 , 116, 0 , 9286 , 369, 63 ), // #1403
- INST(Vrcp28pd , VexRm , E(660F38,CA,_,2,_,1,4,FV ), 0 , 143, 0 , 9295 , 239, 120), // #1404
- INST(Vrcp28ps , VexRm , E(660F38,CA,_,2,_,0,4,FV ), 0 , 144, 0 , 9304 , 240, 120), // #1405
- INST(Vrcp28sd , VexRvm , E(660F38,CB,_,I,_,1,3,T1S), 0 , 115, 0 , 9313 , 267, 120), // #1406
- INST(Vrcp28ss , VexRvm , E(660F38,CB,_,I,_,0,2,T1S), 0 , 116, 0 , 9322 , 268, 120), // #1407
- INST(Vrcpps , VexRm_Lx , V(000F00,53,_,x,I,_,_,_ ), 0 , 66 , 0 , 9331 , 257, 108), // #1408
- INST(Vrcpss , VexRvm , V(F30F00,53,_,I,I,_,_,_ ), 0 , 169, 0 , 9338 , 370, 108), // #1409
- INST(Vreducepd , VexRmi_Lx , E(660F3A,56,_,x,_,1,4,FV ), 0 , 100, 0 , 9345 , 349, 114), // #1410
- INST(Vreduceps , VexRmi_Lx , E(660F3A,56,_,x,_,0,4,FV ), 0 , 99 , 0 , 9355 , 348, 114), // #1411
- INST(Vreducesd , VexRvmi , E(660F3A,57,_,I,_,1,3,T1S), 0 , 151, 0 , 9365 , 371, 61 ), // #1412
- INST(Vreducess , VexRvmi , E(660F3A,57,_,I,_,0,2,T1S), 0 , 152, 0 , 9375 , 372, 61 ), // #1413
- INST(Vrndscalepd , VexRmi_Lx , E(660F3A,09,_,x,_,1,4,FV ), 0 , 100, 0 , 9385 , 269, 111), // #1414
- INST(Vrndscaleps , VexRmi_Lx , E(660F3A,08,_,x,_,0,4,FV ), 0 , 99 , 0 , 9397 , 270, 111), // #1415
- INST(Vrndscalesd , VexRvmi , E(660F3A,0B,_,I,_,1,3,T1S), 0 , 151, 0 , 9409 , 248, 63 ), // #1416
- INST(Vrndscaless , VexRvmi , E(660F3A,0A,_,I,_,0,2,T1S), 0 , 152, 0 , 9421 , 249, 63 ), // #1417
- INST(Vroundpd , VexRmi_Lx , V(660F3A,09,_,x,I,_,_,_ ), 0 , 67 , 0 , 9433 , 373, 108), // #1418
- INST(Vroundps , VexRmi_Lx , V(660F3A,08,_,x,I,_,_,_ ), 0 , 67 , 0 , 9442 , 373, 108), // #1419
- INST(Vroundsd , VexRvmi , V(660F3A,0B,_,I,I,_,_,_ ), 0 , 67 , 0 , 9451 , 374, 108), // #1420
- INST(Vroundss , VexRvmi , V(660F3A,0A,_,I,I,_,_,_ ), 0 , 67 , 0 , 9460 , 375, 108), // #1421
- INST(Vrsqrt14pd , VexRm_Lx , E(660F38,4E,_,x,_,1,4,FV ), 0 , 103, 0 , 9469 , 337, 111), // #1422
- INST(Vrsqrt14ps , VexRm_Lx , E(660F38,4E,_,x,_,0,4,FV ), 0 , 102, 0 , 9480 , 324, 111), // #1423
- INST(Vrsqrt14sd , VexRvm , E(660F38,4F,_,I,_,1,3,T1S), 0 , 115, 0 , 9491 , 368, 63 ), // #1424
- INST(Vrsqrt14ss , VexRvm , E(660F38,4F,_,I,_,0,2,T1S), 0 , 116, 0 , 9502 , 369, 63 ), // #1425
- INST(Vrsqrt28pd , VexRm , E(660F38,CC,_,2,_,1,4,FV ), 0 , 143, 0 , 9513 , 239, 120), // #1426
- INST(Vrsqrt28ps , VexRm , E(660F38,CC,_,2,_,0,4,FV ), 0 , 144, 0 , 9524 , 240, 120), // #1427
- INST(Vrsqrt28sd , VexRvm , E(660F38,CD,_,I,_,1,3,T1S), 0 , 115, 0 , 9535 , 267, 120), // #1428
- INST(Vrsqrt28ss , VexRvm , E(660F38,CD,_,I,_,0,2,T1S), 0 , 116, 0 , 9546 , 268, 120), // #1429
- INST(Vrsqrtps , VexRm_Lx , V(000F00,52,_,x,I,_,_,_ ), 0 , 66 , 0 , 9557 , 257, 108), // #1430
- INST(Vrsqrtss , VexRvm , V(F30F00,52,_,I,I,_,_,_ ), 0 , 169, 0 , 9566 , 370, 108), // #1431
- INST(Vscalefpd , VexRvm_Lx , E(660F38,2C,_,x,_,1,4,FV ), 0 , 103, 0 , 9575 , 376, 111), // #1432
- INST(Vscalefps , VexRvm_Lx , E(660F38,2C,_,x,_,0,4,FV ), 0 , 102, 0 , 9585 , 377, 111), // #1433
- INST(Vscalefsd , VexRvm , E(660F38,2D,_,I,_,1,3,T1S), 0 , 115, 0 , 9595 , 378, 63 ), // #1434
- INST(Vscalefss , VexRvm , E(660F38,2D,_,I,_,0,2,T1S), 0 , 116, 0 , 9605 , 379, 63 ), // #1435
- INST(Vscatterdpd , VexMr_Lx , E(660F38,A2,_,x,_,1,3,T1S), 0 , 115, 0 , 9615 , 380, 111), // #1436
- INST(Vscatterdps , VexMr_Lx , E(660F38,A2,_,x,_,0,2,T1S), 0 , 116, 0 , 9627 , 351, 111), // #1437
- INST(Vscatterpf0dpd , VexM_VM , E(660F38,C6,5,2,_,1,3,T1S), 0 , 211, 0 , 9639 , 262, 126), // #1438
- INST(Vscatterpf0dps , VexM_VM , E(660F38,C6,5,2,_,0,2,T1S), 0 , 212, 0 , 9654 , 263, 126), // #1439
- INST(Vscatterpf0qpd , VexM_VM , E(660F38,C7,5,2,_,1,3,T1S), 0 , 211, 0 , 9669 , 264, 126), // #1440
- INST(Vscatterpf0qps , VexM_VM , E(660F38,C7,5,2,_,0,2,T1S), 0 , 212, 0 , 9684 , 264, 126), // #1441
- INST(Vscatterpf1dpd , VexM_VM , E(660F38,C6,6,2,_,1,3,T1S), 0 , 213, 0 , 9699 , 262, 126), // #1442
- INST(Vscatterpf1dps , VexM_VM , E(660F38,C6,6,2,_,0,2,T1S), 0 , 214, 0 , 9714 , 263, 126), // #1443
- INST(Vscatterpf1qpd , VexM_VM , E(660F38,C7,6,2,_,1,3,T1S), 0 , 213, 0 , 9729 , 264, 126), // #1444
- INST(Vscatterpf1qps , VexM_VM , E(660F38,C7,6,2,_,0,2,T1S), 0 , 214, 0 , 9744 , 264, 126), // #1445
- INST(Vscatterqpd , VexMr_Lx , E(660F38,A3,_,x,_,1,3,T1S), 0 , 115, 0 , 9759 , 353, 111), // #1446
- INST(Vscatterqps , VexMr_Lx , E(660F38,A3,_,x,_,0,2,T1S), 0 , 116, 0 , 9771 , 352, 111), // #1447
- INST(Vshuff32x4 , VexRvmi_Lx , E(660F3A,23,_,x,_,0,4,FV ), 0 , 99 , 0 , 9783 , 381, 111), // #1448
- INST(Vshuff64x2 , VexRvmi_Lx , E(660F3A,23,_,x,_,1,4,FV ), 0 , 100, 0 , 9794 , 382, 111), // #1449
- INST(Vshufi32x4 , VexRvmi_Lx , E(660F3A,43,_,x,_,0,4,FV ), 0 , 99 , 0 , 9805 , 381, 111), // #1450
- INST(Vshufi64x2 , VexRvmi_Lx , E(660F3A,43,_,x,_,1,4,FV ), 0 , 100, 0 , 9816 , 382, 111), // #1451
- INST(Vshufpd , VexRvmi_Lx , V(660F00,C6,_,x,I,1,4,FV ), 0 , 93 , 0 , 9827 , 383, 106), // #1452
- INST(Vshufps , VexRvmi_Lx , V(000F00,C6,_,x,I,0,4,FV ), 0 , 94 , 0 , 9835 , 384, 106), // #1453
- INST(Vsqrtpd , VexRm_Lx , V(660F00,51,_,x,I,1,4,FV ), 0 , 93 , 0 , 9843 , 385, 106), // #1454
- INST(Vsqrtps , VexRm_Lx , V(000F00,51,_,x,I,0,4,FV ), 0 , 94 , 0 , 9851 , 209, 106), // #1455
- INST(Vsqrtsd , VexRvm , V(F20F00,51,_,I,I,1,3,T1S), 0 , 95 , 0 , 9859 , 177, 107), // #1456
- INST(Vsqrtss , VexRvm , V(F30F00,51,_,I,I,0,2,T1S), 0 , 96 , 0 , 9867 , 178, 107), // #1457
- INST(Vstmxcsr , VexM , V(000F00,AE,3,0,I,_,_,_ ), 0 , 215, 0 , 9875 , 278, 108), // #1458
- INST(Vsubpd , VexRvm_Lx , V(660F00,5C,_,x,I,1,4,FV ), 0 , 93 , 0 , 9884 , 175, 106), // #1459
- INST(Vsubps , VexRvm_Lx , V(000F00,5C,_,x,I,0,4,FV ), 0 , 94 , 0 , 9891 , 176, 106), // #1460
- INST(Vsubsd , VexRvm , V(F20F00,5C,_,I,I,1,3,T1S), 0 , 95 , 0 , 9898 , 177, 107), // #1461
- INST(Vsubss , VexRvm , V(F30F00,5C,_,I,I,0,2,T1S), 0 , 96 , 0 , 9905 , 178, 107), // #1462
- INST(Vtestpd , VexRm_Lx , V(660F38,0F,_,x,0,_,_,_ ), 0 , 88 , 0 , 9912 , 257, 134), // #1463
- INST(Vtestps , VexRm_Lx , V(660F38,0E,_,x,0,_,_,_ ), 0 , 88 , 0 , 9920 , 257, 134), // #1464
- INST(Vucomisd , VexRm , V(660F00,2E,_,I,I,1,3,T1S), 0 , 113, 0 , 9928 , 205, 117), // #1465
- INST(Vucomiss , VexRm , V(000F00,2E,_,I,I,0,2,T1S), 0 , 114, 0 , 9937 , 206, 117), // #1466
- INST(Vunpckhpd , VexRvm_Lx , V(660F00,15,_,x,I,1,4,FV ), 0 , 93 , 0 , 9946 , 185, 106), // #1467
- INST(Vunpckhps , VexRvm_Lx , V(000F00,15,_,x,I,0,4,FV ), 0 , 94 , 0 , 9956 , 186, 106), // #1468
- INST(Vunpcklpd , VexRvm_Lx , V(660F00,14,_,x,I,1,4,FV ), 0 , 93 , 0 , 9966 , 185, 106), // #1469
- INST(Vunpcklps , VexRvm_Lx , V(000F00,14,_,x,I,0,4,FV ), 0 , 94 , 0 , 9976 , 186, 106), // #1470
- INST(Vxorpd , VexRvm_Lx , V(660F00,57,_,x,I,1,4,FV ), 0 , 93 , 0 , 9986 , 365, 112), // #1471
- INST(Vxorps , VexRvm_Lx , V(000F00,57,_,x,I,0,4,FV ), 0 , 94 , 0 , 9993 , 364, 112), // #1472
- INST(Vzeroall , VexOp , V(000F00,77,_,1,I,_,_,_ ), 0 , 62 , 0 , 10000, 386, 108), // #1473
- INST(Vzeroupper , VexOp , V(000F00,77,_,0,I,_,_,_ ), 0 , 66 , 0 , 10009, 386, 108), // #1474
- INST(Wbinvd , X86Op , O(000F00,09,_,_,_,_,_,_ ), 0 , 4 , 0 , 10020, 30 , 0 ), // #1475
- INST(Wbnoinvd , X86Op , O(F30F00,09,_,_,_,_,_,_ ), 0 , 6 , 0 , 10027, 30 , 143), // #1476
- INST(Wrfsbase , X86M , O(F30F00,AE,2,_,x,_,_,_ ), 0 , 216, 0 , 10036, 161, 94 ), // #1477
- INST(Wrgsbase , X86M , O(F30F00,AE,3,_,x,_,_,_ ), 0 , 217, 0 , 10045, 161, 94 ), // #1478
- INST(Wrmsr , X86Op , O(000F00,30,_,_,_,_,_,_ ), 0 , 4 , 0 , 10054, 162, 95 ), // #1479
- INST(Xabort , X86Op_O_I8 , O(000000,C6,7,_,_,_,_,_ ), 0 , 25 , 0 , 10060, 74 , 144), // #1480
- INST(Xadd , X86Xadd , O(000F00,C0,_,_,x,_,_,_ ), 0 , 4 , 0 , 10067, 387, 36 ), // #1481
- INST(Xbegin , X86JmpRel , O(000000,C7,7,_,_,_,_,_ ), 0 , 25 , 0 , 10072, 388, 144), // #1482
- INST(Xchg , X86Xchg , O(000000,86,_,_,x,_,_,_ ), 0 , 0 , 0 , 448 , 389, 0 ), // #1483
- INST(Xend , X86Op , O(000F01,D5,_,_,_,_,_,_ ), 0 , 21 , 0 , 10079, 30 , 144), // #1484
- INST(Xgetbv , X86Op , O(000F01,D0,_,_,_,_,_,_ ), 0 , 21 , 0 , 10084, 162, 145), // #1485
- INST(Xlatb , X86Op , O(000000,D7,_,_,_,_,_,_ ), 0 , 0 , 0 , 10091, 30 , 0 ), // #1486
- INST(Xor , X86Arith , O(000000,30,6,_,x,_,_,_ ), 0 , 30 , 0 , 9205 , 166, 1 ), // #1487
- INST(Xorpd , ExtRm , O(660F00,57,_,_,_,_,_,_ ), 0 , 3 , 0 , 9987 , 140, 4 ), // #1488
- INST(Xorps , ExtRm , O(000F00,57,_,_,_,_,_,_ ), 0 , 4 , 0 , 9994 , 140, 5 ), // #1489
- INST(Xrstor , X86M_Only , O(000F00,AE,5,_,_,_,_,_ ), 0 , 70 , 0 , 1134 , 390, 145), // #1490
- INST(Xrstor64 , X86M_Only , O(000F00,AE,5,_,1,_,_,_ ), 0 , 218, 0 , 1142 , 391, 145), // #1491
- INST(Xrstors , X86M_Only , O(000F00,C7,3,_,_,_,_,_ ), 0 , 71 , 0 , 10097, 390, 146), // #1492
- INST(Xrstors64 , X86M_Only , O(000F00,C7,3,_,1,_,_,_ ), 0 , 219, 0 , 10105, 391, 146), // #1493
- INST(Xsave , X86M_Only , O(000F00,AE,4,_,_,_,_,_ ), 0 , 89 , 0 , 1152 , 390, 145), // #1494
- INST(Xsave64 , X86M_Only , O(000F00,AE,4,_,1,_,_,_ ), 0 , 220, 0 , 1159 , 391, 145), // #1495
- INST(Xsavec , X86M_Only , O(000F00,C7,4,_,_,_,_,_ ), 0 , 89 , 0 , 10115, 390, 147), // #1496
- INST(Xsavec64 , X86M_Only , O(000F00,C7,4,_,1,_,_,_ ), 0 , 220, 0 , 10122, 391, 147), // #1497
- INST(Xsaveopt , X86M_Only , O(000F00,AE,6,_,_,_,_,_ ), 0 , 73 , 0 , 10131, 390, 148), // #1498
- INST(Xsaveopt64 , X86M_Only , O(000F00,AE,6,_,1,_,_,_ ), 0 , 221, 0 , 10140, 391, 148), // #1499
- INST(Xsaves , X86M_Only , O(000F00,C7,5,_,_,_,_,_ ), 0 , 70 , 0 , 10151, 390, 146), // #1500
- INST(Xsaves64 , X86M_Only , O(000F00,C7,5,_,1,_,_,_ ), 0 , 218, 0 , 10158, 391, 146), // #1501
- INST(Xsetbv , X86Op , O(000F01,D1,_,_,_,_,_,_ ), 0 , 21 , 0 , 10167, 162, 145), // #1502
- INST(Xtest , X86Op , O(000F01,D6,_,_,_,_,_,_ ), 0 , 21 , 0 , 10174, 30 , 149) // #1503
+ INST(Ldtilecfg , AmxCfg , V(000F38,49,_,0,0,_,_,_ ), 0 , 10 , 0 , 1767 , 95 , 68 ), // #374
+ INST(Lea , X86Lea , O(000000,8D,_,_,x,_,_,_ ), 0 , 0 , 0 , 1777 , 96 , 0 ), // #375
+ INST(Leave , X86Op , O(000000,C9,_,_,_,_,_,_ ), 0 , 0 , 0 , 1781 , 30 , 0 ), // #376
+ INST(Les , X86Rm , O(000000,C4,_,_,_,_,_,_ ), 0 , 0 , 0 , 1787 , 94 , 0 ), // #377
+ INST(Lfence , X86Fence , O(000F00,AE,5,_,_,_,_,_ ), 0 , 70 , 0 , 1791 , 30 , 4 ), // #378
+ INST(Lfs , X86Rm , O(000F00,B4,_,_,_,_,_,_ ), 0 , 4 , 0 , 1798 , 97 , 0 ), // #379
+ INST(Lgdt , X86M_Only , O(000F00,01,2,_,_,_,_,_ ), 0 , 69 , 0 , 1802 , 31 , 0 ), // #380
+ INST(Lgs , X86Rm , O(000F00,B5,_,_,_,_,_,_ ), 0 , 4 , 0 , 1807 , 97 , 0 ), // #381
+ INST(Lidt , X86M_Only , O(000F00,01,3,_,_,_,_,_ ), 0 , 71 , 0 , 1811 , 31 , 0 ), // #382
+ INST(Lldt , X86M_NoSize , O(000F00,00,2,_,_,_,_,_ ), 0 , 69 , 0 , 1816 , 98 , 0 ), // #383
+ INST(Llwpcb , VexR_Wx , V(XOP_M9,12,0,0,x,_,_,_ ), 0 , 72 , 0 , 1821 , 99 , 69 ), // #384
+ INST(Lmsw , X86M_NoSize , O(000F00,01,6,_,_,_,_,_ ), 0 , 73 , 0 , 1828 , 98 , 0 ), // #385
+ INST(Lods , X86StrRm , O(000000,AC,_,_,_,_,_,_ ), 0 , 0 , 0 , 1833 , 100, 70 ), // #386
+ INST(Loop , X86JecxzLoop , 0 , O(000000,E2,_,_,_,_,_,_ ), 0 , 40 , 1838 , 101, 0 ), // #387
+ INST(Loope , X86JecxzLoop , 0 , O(000000,E1,_,_,_,_,_,_ ), 0 , 41 , 1843 , 101, 56 ), // #388
+ INST(Loopne , X86JecxzLoop , 0 , O(000000,E0,_,_,_,_,_,_ ), 0 , 42 , 1849 , 101, 56 ), // #389
+ INST(Lsl , X86Rm , O(000F00,03,_,_,_,_,_,_ ), 0 , 4 , 0 , 1856 , 102, 10 ), // #390
+ INST(Lss , X86Rm , O(000F00,B2,_,_,_,_,_,_ ), 0 , 4 , 0 , 6477 , 97 , 0 ), // #391
+ INST(Ltr , X86M_NoSize , O(000F00,00,3,_,_,_,_,_ ), 0 , 71 , 0 , 1860 , 98 , 0 ), // #392
+ INST(Lwpins , VexVmi4_Wx , V(XOP_MA,12,0,0,x,_,_,_ ), 0 , 74 , 0 , 1864 , 103, 69 ), // #393
+ INST(Lwpval , VexVmi4_Wx , V(XOP_MA,12,1,0,x,_,_,_ ), 0 , 75 , 0 , 1871 , 103, 69 ), // #394
+ INST(Lzcnt , X86Rm_Raw66H , O(F30F00,BD,_,_,x,_,_,_ ), 0 , 6 , 0 , 1878 , 22 , 71 ), // #395
+ INST(Maskmovdqu , ExtRm_ZDI , O(660F00,57,_,_,_,_,_,_ ), 0 , 3 , 0 , 5995 , 104, 4 ), // #396
+ INST(Maskmovq , ExtRm_ZDI , O(000F00,F7,_,_,_,_,_,_ ), 0 , 4 , 0 , 7994 , 105, 72 ), // #397
+ INST(Maxpd , ExtRm , O(660F00,5F,_,_,_,_,_,_ ), 0 , 3 , 0 , 6029 , 5 , 4 ), // #398
+ INST(Maxps , ExtRm , O(000F00,5F,_,_,_,_,_,_ ), 0 , 4 , 0 , 6036 , 5 , 5 ), // #399
+ INST(Maxsd , ExtRm , O(F20F00,5F,_,_,_,_,_,_ ), 0 , 5 , 0 , 8013 , 6 , 4 ), // #400
+ INST(Maxss , ExtRm , O(F30F00,5F,_,_,_,_,_,_ ), 0 , 6 , 0 , 6050 , 7 , 5 ), // #401
+ INST(Mcommit , X86Op , O(F30F01,FA,_,_,_,_,_,_ ), 0 , 76 , 0 , 1884 , 30 , 73 ), // #402
+ INST(Mfence , X86Fence , O(000F00,AE,6,_,_,_,_,_ ), 0 , 73 , 0 , 1892 , 30 , 4 ), // #403
+ INST(Minpd , ExtRm , O(660F00,5D,_,_,_,_,_,_ ), 0 , 3 , 0 , 6079 , 5 , 4 ), // #404
+ INST(Minps , ExtRm , O(000F00,5D,_,_,_,_,_,_ ), 0 , 4 , 0 , 6086 , 5 , 5 ), // #405
+ INST(Minsd , ExtRm , O(F20F00,5D,_,_,_,_,_,_ ), 0 , 5 , 0 , 8077 , 6 , 4 ), // #406
+ INST(Minss , ExtRm , O(F30F00,5D,_,_,_,_,_,_ ), 0 , 6 , 0 , 6100 , 7 , 5 ), // #407
+ INST(Monitor , X86Op , O(000F01,C8,_,_,_,_,_,_ ), 0 , 21 , 0 , 3092 , 106, 74 ), // #408
+ INST(Monitorx , X86Op , O(000F01,FA,_,_,_,_,_,_ ), 0 , 21 , 0 , 1899 , 106, 75 ), // #409
+ INST(Mov , X86Mov , 0 , 0 , 0 , 0 , 138 , 107, 0 ), // #410
+ INST(Movapd , ExtMov , O(660F00,28,_,_,_,_,_,_ ), O(660F00,29,_,_,_,_,_,_ ), 3 , 43 , 6131 , 108, 4 ), // #411
+ INST(Movaps , ExtMov , O(000F00,28,_,_,_,_,_,_ ), O(000F00,29,_,_,_,_,_,_ ), 4 , 44 , 6139 , 108, 5 ), // #412
+ INST(Movbe , ExtMovbe , O(000F38,F0,_,_,x,_,_,_ ), O(000F38,F1,_,_,x,_,_,_ ), 77 , 45 , 626 , 109, 76 ), // #413
+ INST(Movd , ExtMovd , O(000F00,6E,_,_,_,_,_,_ ), O(000F00,7E,_,_,_,_,_,_ ), 4 , 46 , 7987 , 110, 77 ), // #414
+ INST(Movddup , ExtMov , O(F20F00,12,_,_,_,_,_,_ ), 0 , 5 , 0 , 6153 , 6 , 6 ), // #415
+ INST(Movdir64b , X86EnqcmdMovdir64b , O(660F38,F8,_,_,_,_,_,_ ), 0 , 2 , 0 , 1908 , 111, 78 ), // #416
+ INST(Movdiri , X86MovntiMovdiri , O(000F38,F9,_,_,_,_,_,_ ), 0 , 77 , 0 , 1918 , 112, 79 ), // #417
+ INST(Movdq2q , ExtMov , O(F20F00,D6,_,_,_,_,_,_ ), 0 , 5 , 0 , 1926 , 113, 4 ), // #418
+ INST(Movdqa , ExtMov , O(660F00,6F,_,_,_,_,_,_ ), O(660F00,7F,_,_,_,_,_,_ ), 3 , 47 , 6162 , 108, 4 ), // #419
+ INST(Movdqu , ExtMov , O(F30F00,6F,_,_,_,_,_,_ ), O(F30F00,7F,_,_,_,_,_,_ ), 6 , 48 , 5999 , 108, 4 ), // #420
+ INST(Movhlps , ExtMov , O(000F00,12,_,_,_,_,_,_ ), 0 , 4 , 0 , 6237 , 114, 5 ), // #421
+ INST(Movhpd , ExtMov , O(660F00,16,_,_,_,_,_,_ ), O(660F00,17,_,_,_,_,_,_ ), 3 , 49 , 6246 , 115, 4 ), // #422
+ INST(Movhps , ExtMov , O(000F00,16,_,_,_,_,_,_ ), O(000F00,17,_,_,_,_,_,_ ), 4 , 50 , 6254 , 115, 5 ), // #423
+ INST(Movlhps , ExtMov , O(000F00,16,_,_,_,_,_,_ ), 0 , 4 , 0 , 6262 , 114, 5 ), // #424
+ INST(Movlpd , ExtMov , O(660F00,12,_,_,_,_,_,_ ), O(660F00,13,_,_,_,_,_,_ ), 3 , 51 , 6271 , 115, 4 ), // #425
+ INST(Movlps , ExtMov , O(000F00,12,_,_,_,_,_,_ ), O(000F00,13,_,_,_,_,_,_ ), 4 , 52 , 6279 , 115, 5 ), // #426
+ INST(Movmskpd , ExtMov , O(660F00,50,_,_,_,_,_,_ ), 0 , 3 , 0 , 6287 , 116, 4 ), // #427
+ INST(Movmskps , ExtMov , O(000F00,50,_,_,_,_,_,_ ), 0 , 4 , 0 , 6297 , 116, 5 ), // #428
+ INST(Movntdq , ExtMov , 0 , O(660F00,E7,_,_,_,_,_,_ ), 0 , 53 , 6307 , 117, 4 ), // #429
+ INST(Movntdqa , ExtMov , O(660F38,2A,_,_,_,_,_,_ ), 0 , 2 , 0 , 6316 , 92 , 12 ), // #430
+ INST(Movnti , X86MovntiMovdiri , O(000F00,C3,_,_,x,_,_,_ ), 0 , 4 , 0 , 1934 , 112, 4 ), // #431
+ INST(Movntpd , ExtMov , 0 , O(660F00,2B,_,_,_,_,_,_ ), 0 , 54 , 6326 , 117, 4 ), // #432
+ INST(Movntps , ExtMov , 0 , O(000F00,2B,_,_,_,_,_,_ ), 0 , 55 , 6335 , 117, 5 ), // #433
+ INST(Movntq , ExtMov , 0 , O(000F00,E7,_,_,_,_,_,_ ), 0 , 56 , 1941 , 118, 72 ), // #434
+ INST(Movntsd , ExtMov , 0 , O(F20F00,2B,_,_,_,_,_,_ ), 0 , 57 , 1948 , 119, 46 ), // #435
+ INST(Movntss , ExtMov , 0 , O(F30F00,2B,_,_,_,_,_,_ ), 0 , 58 , 1956 , 120, 46 ), // #436
+ INST(Movq , ExtMovq , O(000F00,6E,_,_,x,_,_,_ ), O(000F00,7E,_,_,x,_,_,_ ), 4 , 59 , 7998 , 121, 77 ), // #437
+ INST(Movq2dq , ExtRm , O(F30F00,D6,_,_,_,_,_,_ ), 0 , 6 , 0 , 1964 , 122, 4 ), // #438
+ INST(Movs , X86StrMm , O(000000,A4,_,_,_,_,_,_ ), 0 , 0 , 0 , 425 , 123, 70 ), // #439
+ INST(Movsd , ExtMov , O(F20F00,10,_,_,_,_,_,_ ), O(F20F00,11,_,_,_,_,_,_ ), 5 , 60 , 6350 , 124, 4 ), // #440
+ INST(Movshdup , ExtRm , O(F30F00,16,_,_,_,_,_,_ ), 0 , 6 , 0 , 6357 , 5 , 6 ), // #441
+ INST(Movsldup , ExtRm , O(F30F00,12,_,_,_,_,_,_ ), 0 , 6 , 0 , 6367 , 5 , 6 ), // #442
+ INST(Movss , ExtMov , O(F30F00,10,_,_,_,_,_,_ ), O(F30F00,11,_,_,_,_,_,_ ), 6 , 61 , 6377 , 125, 5 ), // #443
+ INST(Movsx , X86MovsxMovzx , O(000F00,BE,_,_,x,_,_,_ ), 0 , 4 , 0 , 1972 , 126, 0 ), // #444
+ INST(Movsxd , X86Rm , O(000000,63,_,_,x,_,_,_ ), 0 , 0 , 0 , 1978 , 127, 0 ), // #445
+ INST(Movupd , ExtMov , O(660F00,10,_,_,_,_,_,_ ), O(660F00,11,_,_,_,_,_,_ ), 3 , 62 , 6384 , 108, 4 ), // #446
+ INST(Movups , ExtMov , O(000F00,10,_,_,_,_,_,_ ), O(000F00,11,_,_,_,_,_,_ ), 4 , 63 , 6392 , 108, 5 ), // #447
+ INST(Movzx , X86MovsxMovzx , O(000F00,B6,_,_,x,_,_,_ ), 0 , 4 , 0 , 1985 , 126, 0 ), // #448
+ INST(Mpsadbw , ExtRmi , O(660F3A,42,_,_,_,_,_,_ ), 0 , 8 , 0 , 6400 , 8 , 12 ), // #449
+ INST(Mul , X86M_GPB_MulDiv , O(000000,F6,4,_,x,_,_,_ ), 0 , 9 , 0 , 798 , 52 , 1 ), // #450
+ INST(Mulpd , ExtRm , O(660F00,59,_,_,_,_,_,_ ), 0 , 3 , 0 , 6454 , 5 , 4 ), // #451
+ INST(Mulps , ExtRm , O(000F00,59,_,_,_,_,_,_ ), 0 , 4 , 0 , 6461 , 5 , 5 ), // #452
+ INST(Mulsd , ExtRm , O(F20F00,59,_,_,_,_,_,_ ), 0 , 5 , 0 , 6468 , 6 , 4 ), // #453
+ INST(Mulss , ExtRm , O(F30F00,59,_,_,_,_,_,_ ), 0 , 6 , 0 , 6475 , 7 , 5 ), // #454
+ INST(Mulx , VexRvm_ZDX_Wx , V(F20F38,F6,_,0,x,_,_,_ ), 0 , 78 , 0 , 1991 , 128, 80 ), // #455
+ INST(Mwait , X86Op , O(000F01,C9,_,_,_,_,_,_ ), 0 , 21 , 0 , 3101 , 129, 74 ), // #456
+ INST(Mwaitx , X86Op , O(000F01,FB,_,_,_,_,_,_ ), 0 , 21 , 0 , 1996 , 130, 75 ), // #457
+ INST(Neg , X86M_GPB , O(000000,F6,3,_,x,_,_,_ ), 0 , 79 , 0 , 2003 , 131, 1 ), // #458
+ INST(Nop , X86M_Nop , O(000000,90,_,_,_,_,_,_ ), 0 , 0 , 0 , 929 , 132, 0 ), // #459
+ INST(Not , X86M_GPB , O(000000,F6,2,_,x,_,_,_ ), 0 , 1 , 0 , 2007 , 131, 0 ), // #460
+ INST(Or , X86Arith , O(000000,08,1,_,x,_,_,_ ), 0 , 29 , 0 , 3097 , 133, 1 ), // #461
+ INST(Orpd , ExtRm , O(660F00,56,_,_,_,_,_,_ ), 0 , 3 , 0 , 10204, 11 , 4 ), // #462
+ INST(Orps , ExtRm , O(000F00,56,_,_,_,_,_,_ ), 0 , 4 , 0 , 10211, 11 , 5 ), // #463
+ INST(Out , X86Out , O(000000,EE,_,_,_,_,_,_ ), O(000000,E6,_,_,_,_,_,_ ), 0 , 64 , 2011 , 134, 0 ), // #464
+ INST(Outs , X86Outs , O(000000,6E,_,_,_,_,_,_ ), 0 , 0 , 0 , 2015 , 135, 0 ), // #465
+ INST(Pabsb , ExtRm_P , O(000F38,1C,_,_,_,_,_,_ ), 0 , 77 , 0 , 6557 , 136, 81 ), // #466
+ INST(Pabsd , ExtRm_P , O(000F38,1E,_,_,_,_,_,_ ), 0 , 77 , 0 , 6564 , 136, 81 ), // #467
+ INST(Pabsw , ExtRm_P , O(000F38,1D,_,_,_,_,_,_ ), 0 , 77 , 0 , 6578 , 136, 81 ), // #468
+ INST(Packssdw , ExtRm_P , O(000F00,6B,_,_,_,_,_,_ ), 0 , 4 , 0 , 6585 , 136, 77 ), // #469
+ INST(Packsswb , ExtRm_P , O(000F00,63,_,_,_,_,_,_ ), 0 , 4 , 0 , 6595 , 136, 77 ), // #470
+ INST(Packusdw , ExtRm , O(660F38,2B,_,_,_,_,_,_ ), 0 , 2 , 0 , 6605 , 5 , 12 ), // #471
+ INST(Packuswb , ExtRm_P , O(000F00,67,_,_,_,_,_,_ ), 0 , 4 , 0 , 6615 , 136, 77 ), // #472
+ INST(Paddb , ExtRm_P , O(000F00,FC,_,_,_,_,_,_ ), 0 , 4 , 0 , 6625 , 136, 77 ), // #473
+ INST(Paddd , ExtRm_P , O(000F00,FE,_,_,_,_,_,_ ), 0 , 4 , 0 , 6632 , 136, 77 ), // #474
+ INST(Paddq , ExtRm_P , O(000F00,D4,_,_,_,_,_,_ ), 0 , 4 , 0 , 6639 , 136, 4 ), // #475
+ INST(Paddsb , ExtRm_P , O(000F00,EC,_,_,_,_,_,_ ), 0 , 4 , 0 , 6646 , 136, 77 ), // #476
+ INST(Paddsw , ExtRm_P , O(000F00,ED,_,_,_,_,_,_ ), 0 , 4 , 0 , 6654 , 136, 77 ), // #477
+ INST(Paddusb , ExtRm_P , O(000F00,DC,_,_,_,_,_,_ ), 0 , 4 , 0 , 6662 , 136, 77 ), // #478
+ INST(Paddusw , ExtRm_P , O(000F00,DD,_,_,_,_,_,_ ), 0 , 4 , 0 , 6671 , 136, 77 ), // #479
+ INST(Paddw , ExtRm_P , O(000F00,FD,_,_,_,_,_,_ ), 0 , 4 , 0 , 6680 , 136, 77 ), // #480
+ INST(Palignr , ExtRmi_P , O(000F3A,0F,_,_,_,_,_,_ ), 0 , 80 , 0 , 6687 , 137, 6 ), // #481
+ INST(Pand , ExtRm_P , O(000F00,DB,_,_,_,_,_,_ ), 0 , 4 , 0 , 6696 , 138, 77 ), // #482
+ INST(Pandn , ExtRm_P , O(000F00,DF,_,_,_,_,_,_ ), 0 , 4 , 0 , 6709 , 139, 77 ), // #483
+ INST(Pause , X86Op , O(F30000,90,_,_,_,_,_,_ ), 0 , 81 , 0 , 3069 , 30 , 0 ), // #484
+ INST(Pavgb , ExtRm_P , O(000F00,E0,_,_,_,_,_,_ ), 0 , 4 , 0 , 6739 , 136, 82 ), // #485
+ INST(Pavgusb , Ext3dNow , O(000F0F,BF,_,_,_,_,_,_ ), 0 , 82 , 0 , 2020 , 140, 48 ), // #486
+ INST(Pavgw , ExtRm_P , O(000F00,E3,_,_,_,_,_,_ ), 0 , 4 , 0 , 6746 , 136, 82 ), // #487
+ INST(Pblendvb , ExtRm_XMM0 , O(660F38,10,_,_,_,_,_,_ ), 0 , 2 , 0 , 6762 , 15 , 12 ), // #488
+ INST(Pblendw , ExtRmi , O(660F3A,0E,_,_,_,_,_,_ ), 0 , 8 , 0 , 6772 , 8 , 12 ), // #489
+ INST(Pclmulqdq , ExtRmi , O(660F3A,44,_,_,_,_,_,_ ), 0 , 8 , 0 , 6865 , 8 , 83 ), // #490
+ INST(Pcmpeqb , ExtRm_P , O(000F00,74,_,_,_,_,_,_ ), 0 , 4 , 0 , 6897 , 139, 77 ), // #491
+ INST(Pcmpeqd , ExtRm_P , O(000F00,76,_,_,_,_,_,_ ), 0 , 4 , 0 , 6906 , 139, 77 ), // #492
+ INST(Pcmpeqq , ExtRm , O(660F38,29,_,_,_,_,_,_ ), 0 , 2 , 0 , 6915 , 141, 12 ), // #493
+ INST(Pcmpeqw , ExtRm_P , O(000F00,75,_,_,_,_,_,_ ), 0 , 4 , 0 , 6924 , 139, 77 ), // #494
+ INST(Pcmpestri , ExtRmi , O(660F3A,61,_,_,_,_,_,_ ), 0 , 8 , 0 , 6933 , 142, 84 ), // #495
+ INST(Pcmpestrm , ExtRmi , O(660F3A,60,_,_,_,_,_,_ ), 0 , 8 , 0 , 6944 , 143, 84 ), // #496
+ INST(Pcmpgtb , ExtRm_P , O(000F00,64,_,_,_,_,_,_ ), 0 , 4 , 0 , 6955 , 139, 77 ), // #497
+ INST(Pcmpgtd , ExtRm_P , O(000F00,66,_,_,_,_,_,_ ), 0 , 4 , 0 , 6964 , 139, 77 ), // #498
+ INST(Pcmpgtq , ExtRm , O(660F38,37,_,_,_,_,_,_ ), 0 , 2 , 0 , 6973 , 141, 42 ), // #499
+ INST(Pcmpgtw , ExtRm_P , O(000F00,65,_,_,_,_,_,_ ), 0 , 4 , 0 , 6982 , 139, 77 ), // #500
+ INST(Pcmpistri , ExtRmi , O(660F3A,63,_,_,_,_,_,_ ), 0 , 8 , 0 , 6991 , 144, 84 ), // #501
+ INST(Pcmpistrm , ExtRmi , O(660F3A,62,_,_,_,_,_,_ ), 0 , 8 , 0 , 7002 , 145, 84 ), // #502
+ INST(Pcommit , X86Op_O , O(660F00,AE,7,_,_,_,_,_ ), 0 , 23 , 0 , 2028 , 30 , 85 ), // #503
+ INST(Pconfig , X86Op , O(000F01,C5,_,_,_,_,_,_ ), 0 , 21 , 0 , 2036 , 30 , 86 ), // #504
+ INST(Pdep , VexRvm_Wx , V(F20F38,F5,_,0,x,_,_,_ ), 0 , 78 , 0 , 2044 , 10 , 80 ), // #505
+ INST(Pext , VexRvm_Wx , V(F30F38,F5,_,0,x,_,_,_ ), 0 , 83 , 0 , 2049 , 10 , 80 ), // #506
+ INST(Pextrb , ExtExtract , O(000F3A,14,_,_,_,_,_,_ ), 0 , 80 , 0 , 7489 , 146, 12 ), // #507
+ INST(Pextrd , ExtExtract , O(000F3A,16,_,_,_,_,_,_ ), 0 , 80 , 0 , 7497 , 56 , 12 ), // #508
+ INST(Pextrq , ExtExtract , O(000F3A,16,_,_,1,_,_,_ ), 0 , 84 , 0 , 7505 , 147, 12 ), // #509
+ INST(Pextrw , ExtPextrw , O(000F00,C5,_,_,_,_,_,_ ), O(000F3A,15,_,_,_,_,_,_ ), 4 , 65 , 7513 , 148, 87 ), // #510
+ INST(Pf2id , Ext3dNow , O(000F0F,1D,_,_,_,_,_,_ ), 0 , 82 , 0 , 2054 , 140, 48 ), // #511
+ INST(Pf2iw , Ext3dNow , O(000F0F,1C,_,_,_,_,_,_ ), 0 , 82 , 0 , 2060 , 140, 88 ), // #512
+ INST(Pfacc , Ext3dNow , O(000F0F,AE,_,_,_,_,_,_ ), 0 , 82 , 0 , 2066 , 140, 48 ), // #513
+ INST(Pfadd , Ext3dNow , O(000F0F,9E,_,_,_,_,_,_ ), 0 , 82 , 0 , 2072 , 140, 48 ), // #514
+ INST(Pfcmpeq , Ext3dNow , O(000F0F,B0,_,_,_,_,_,_ ), 0 , 82 , 0 , 2078 , 140, 48 ), // #515
+ INST(Pfcmpge , Ext3dNow , O(000F0F,90,_,_,_,_,_,_ ), 0 , 82 , 0 , 2086 , 140, 48 ), // #516
+ INST(Pfcmpgt , Ext3dNow , O(000F0F,A0,_,_,_,_,_,_ ), 0 , 82 , 0 , 2094 , 140, 48 ), // #517
+ INST(Pfmax , Ext3dNow , O(000F0F,A4,_,_,_,_,_,_ ), 0 , 82 , 0 , 2102 , 140, 48 ), // #518
+ INST(Pfmin , Ext3dNow , O(000F0F,94,_,_,_,_,_,_ ), 0 , 82 , 0 , 2108 , 140, 48 ), // #519
+ INST(Pfmul , Ext3dNow , O(000F0F,B4,_,_,_,_,_,_ ), 0 , 82 , 0 , 2114 , 140, 48 ), // #520
+ INST(Pfnacc , Ext3dNow , O(000F0F,8A,_,_,_,_,_,_ ), 0 , 82 , 0 , 2120 , 140, 88 ), // #521
+ INST(Pfpnacc , Ext3dNow , O(000F0F,8E,_,_,_,_,_,_ ), 0 , 82 , 0 , 2127 , 140, 88 ), // #522
+ INST(Pfrcp , Ext3dNow , O(000F0F,96,_,_,_,_,_,_ ), 0 , 82 , 0 , 2135 , 140, 48 ), // #523
+ INST(Pfrcpit1 , Ext3dNow , O(000F0F,A6,_,_,_,_,_,_ ), 0 , 82 , 0 , 2141 , 140, 48 ), // #524
+ INST(Pfrcpit2 , Ext3dNow , O(000F0F,B6,_,_,_,_,_,_ ), 0 , 82 , 0 , 2150 , 140, 48 ), // #525
+ INST(Pfrcpv , Ext3dNow , O(000F0F,86,_,_,_,_,_,_ ), 0 , 82 , 0 , 2159 , 140, 89 ), // #526
+ INST(Pfrsqit1 , Ext3dNow , O(000F0F,A7,_,_,_,_,_,_ ), 0 , 82 , 0 , 2166 , 140, 48 ), // #527
+ INST(Pfrsqrt , Ext3dNow , O(000F0F,97,_,_,_,_,_,_ ), 0 , 82 , 0 , 2175 , 140, 48 ), // #528
+ INST(Pfrsqrtv , Ext3dNow , O(000F0F,87,_,_,_,_,_,_ ), 0 , 82 , 0 , 2183 , 140, 89 ), // #529
+ INST(Pfsub , Ext3dNow , O(000F0F,9A,_,_,_,_,_,_ ), 0 , 82 , 0 , 2192 , 140, 48 ), // #530
+ INST(Pfsubr , Ext3dNow , O(000F0F,AA,_,_,_,_,_,_ ), 0 , 82 , 0 , 2198 , 140, 48 ), // #531
+ INST(Phaddd , ExtRm_P , O(000F38,02,_,_,_,_,_,_ ), 0 , 77 , 0 , 7592 , 136, 81 ), // #532
+ INST(Phaddsw , ExtRm_P , O(000F38,03,_,_,_,_,_,_ ), 0 , 77 , 0 , 7609 , 136, 81 ), // #533
+ INST(Phaddw , ExtRm_P , O(000F38,01,_,_,_,_,_,_ ), 0 , 77 , 0 , 7678 , 136, 81 ), // #534
+ INST(Phminposuw , ExtRm , O(660F38,41,_,_,_,_,_,_ ), 0 , 2 , 0 , 7704 , 5 , 12 ), // #535
+ INST(Phsubd , ExtRm_P , O(000F38,06,_,_,_,_,_,_ ), 0 , 77 , 0 , 7725 , 136, 81 ), // #536
+ INST(Phsubsw , ExtRm_P , O(000F38,07,_,_,_,_,_,_ ), 0 , 77 , 0 , 7742 , 136, 81 ), // #537
+ INST(Phsubw , ExtRm_P , O(000F38,05,_,_,_,_,_,_ ), 0 , 77 , 0 , 7751 , 136, 81 ), // #538
+ INST(Pi2fd , Ext3dNow , O(000F0F,0D,_,_,_,_,_,_ ), 0 , 82 , 0 , 2205 , 140, 48 ), // #539
+ INST(Pi2fw , Ext3dNow , O(000F0F,0C,_,_,_,_,_,_ ), 0 , 82 , 0 , 2211 , 140, 88 ), // #540
+ INST(Pinsrb , ExtRmi , O(660F3A,20,_,_,_,_,_,_ ), 0 , 8 , 0 , 7768 , 149, 12 ), // #541
+ INST(Pinsrd , ExtRmi , O(660F3A,22,_,_,_,_,_,_ ), 0 , 8 , 0 , 7776 , 150, 12 ), // #542
+ INST(Pinsrq , ExtRmi , O(660F3A,22,_,_,1,_,_,_ ), 0 , 85 , 0 , 7784 , 151, 12 ), // #543
+ INST(Pinsrw , ExtRmi_P , O(000F00,C4,_,_,_,_,_,_ ), 0 , 4 , 0 , 7792 , 152, 82 ), // #544
+ INST(Pmaddubsw , ExtRm_P , O(000F38,04,_,_,_,_,_,_ ), 0 , 77 , 0 , 7962 , 136, 81 ), // #545
+ INST(Pmaddwd , ExtRm_P , O(000F00,F5,_,_,_,_,_,_ ), 0 , 4 , 0 , 7973 , 136, 77 ), // #546
+ INST(Pmaxsb , ExtRm , O(660F38,3C,_,_,_,_,_,_ ), 0 , 2 , 0 , 8004 , 11 , 12 ), // #547
+ INST(Pmaxsd , ExtRm , O(660F38,3D,_,_,_,_,_,_ ), 0 , 2 , 0 , 8012 , 11 , 12 ), // #548
+ INST(Pmaxsw , ExtRm_P , O(000F00,EE,_,_,_,_,_,_ ), 0 , 4 , 0 , 8028 , 138, 82 ), // #549
+ INST(Pmaxub , ExtRm_P , O(000F00,DE,_,_,_,_,_,_ ), 0 , 4 , 0 , 8036 , 138, 82 ), // #550
+ INST(Pmaxud , ExtRm , O(660F38,3F,_,_,_,_,_,_ ), 0 , 2 , 0 , 8044 , 11 , 12 ), // #551
+ INST(Pmaxuw , ExtRm , O(660F38,3E,_,_,_,_,_,_ ), 0 , 2 , 0 , 8060 , 11 , 12 ), // #552
+ INST(Pminsb , ExtRm , O(660F38,38,_,_,_,_,_,_ ), 0 , 2 , 0 , 8068 , 11 , 12 ), // #553
+ INST(Pminsd , ExtRm , O(660F38,39,_,_,_,_,_,_ ), 0 , 2 , 0 , 8076 , 11 , 12 ), // #554
+ INST(Pminsw , ExtRm_P , O(000F00,EA,_,_,_,_,_,_ ), 0 , 4 , 0 , 8092 , 138, 82 ), // #555
+ INST(Pminub , ExtRm_P , O(000F00,DA,_,_,_,_,_,_ ), 0 , 4 , 0 , 8100 , 138, 82 ), // #556
+ INST(Pminud , ExtRm , O(660F38,3B,_,_,_,_,_,_ ), 0 , 2 , 0 , 8108 , 11 , 12 ), // #557
+ INST(Pminuw , ExtRm , O(660F38,3A,_,_,_,_,_,_ ), 0 , 2 , 0 , 8124 , 11 , 12 ), // #558
+ INST(Pmovmskb , ExtRm_P , O(000F00,D7,_,_,_,_,_,_ ), 0 , 4 , 0 , 8202 , 153, 82 ), // #559
+ INST(Pmovsxbd , ExtRm , O(660F38,21,_,_,_,_,_,_ ), 0 , 2 , 0 , 8299 , 7 , 12 ), // #560
+ INST(Pmovsxbq , ExtRm , O(660F38,22,_,_,_,_,_,_ ), 0 , 2 , 0 , 8309 , 154, 12 ), // #561
+ INST(Pmovsxbw , ExtRm , O(660F38,20,_,_,_,_,_,_ ), 0 , 2 , 0 , 8319 , 6 , 12 ), // #562
+ INST(Pmovsxdq , ExtRm , O(660F38,25,_,_,_,_,_,_ ), 0 , 2 , 0 , 8329 , 6 , 12 ), // #563
+ INST(Pmovsxwd , ExtRm , O(660F38,23,_,_,_,_,_,_ ), 0 , 2 , 0 , 8339 , 6 , 12 ), // #564
+ INST(Pmovsxwq , ExtRm , O(660F38,24,_,_,_,_,_,_ ), 0 , 2 , 0 , 8349 , 7 , 12 ), // #565
+ INST(Pmovzxbd , ExtRm , O(660F38,31,_,_,_,_,_,_ ), 0 , 2 , 0 , 8436 , 7 , 12 ), // #566
+ INST(Pmovzxbq , ExtRm , O(660F38,32,_,_,_,_,_,_ ), 0 , 2 , 0 , 8446 , 154, 12 ), // #567
+ INST(Pmovzxbw , ExtRm , O(660F38,30,_,_,_,_,_,_ ), 0 , 2 , 0 , 8456 , 6 , 12 ), // #568
+ INST(Pmovzxdq , ExtRm , O(660F38,35,_,_,_,_,_,_ ), 0 , 2 , 0 , 8466 , 6 , 12 ), // #569
+ INST(Pmovzxwd , ExtRm , O(660F38,33,_,_,_,_,_,_ ), 0 , 2 , 0 , 8476 , 6 , 12 ), // #570
+ INST(Pmovzxwq , ExtRm , O(660F38,34,_,_,_,_,_,_ ), 0 , 2 , 0 , 8486 , 7 , 12 ), // #571
+ INST(Pmuldq , ExtRm , O(660F38,28,_,_,_,_,_,_ ), 0 , 2 , 0 , 8496 , 5 , 12 ), // #572
+ INST(Pmulhrsw , ExtRm_P , O(000F38,0B,_,_,_,_,_,_ ), 0 , 77 , 0 , 8504 , 136, 81 ), // #573
+ INST(Pmulhrw , Ext3dNow , O(000F0F,B7,_,_,_,_,_,_ ), 0 , 82 , 0 , 2217 , 140, 48 ), // #574
+ INST(Pmulhuw , ExtRm_P , O(000F00,E4,_,_,_,_,_,_ ), 0 , 4 , 0 , 8514 , 136, 82 ), // #575
+ INST(Pmulhw , ExtRm_P , O(000F00,E5,_,_,_,_,_,_ ), 0 , 4 , 0 , 8523 , 136, 77 ), // #576
+ INST(Pmulld , ExtRm , O(660F38,40,_,_,_,_,_,_ ), 0 , 2 , 0 , 8531 , 5 , 12 ), // #577
+ INST(Pmullw , ExtRm_P , O(000F00,D5,_,_,_,_,_,_ ), 0 , 4 , 0 , 8547 , 136, 77 ), // #578
+ INST(Pmuludq , ExtRm_P , O(000F00,F4,_,_,_,_,_,_ ), 0 , 4 , 0 , 8570 , 136, 4 ), // #579
+ INST(Pop , X86Pop , O(000000,8F,0,_,_,_,_,_ ), O(000000,58,_,_,_,_,_,_ ), 0 , 66 , 2225 , 155, 0 ), // #580
+ INST(Popa , X86Op , O(660000,61,_,_,_,_,_,_ ), 0 , 19 , 0 , 2229 , 75 , 0 ), // #581
+ INST(Popad , X86Op , O(000000,61,_,_,_,_,_,_ ), 0 , 0 , 0 , 2234 , 75 , 0 ), // #582
+ INST(Popcnt , X86Rm_Raw66H , O(F30F00,B8,_,_,x,_,_,_ ), 0 , 6 , 0 , 2240 , 22 , 90 ), // #583
+ INST(Popf , X86Op , O(660000,9D,_,_,_,_,_,_ ), 0 , 19 , 0 , 2247 , 30 , 91 ), // #584
+ INST(Popfd , X86Op , O(000000,9D,_,_,_,_,_,_ ), 0 , 0 , 0 , 2252 , 75 , 91 ), // #585
+ INST(Popfq , X86Op , O(000000,9D,_,_,_,_,_,_ ), 0 , 0 , 0 , 2258 , 156, 91 ), // #586
+ INST(Por , ExtRm_P , O(000F00,EB,_,_,_,_,_,_ ), 0 , 4 , 0 , 8615 , 138, 77 ), // #587
+ INST(Prefetch , X86M_Only , O(000F00,0D,0,_,_,_,_,_ ), 0 , 4 , 0 , 2264 , 31 , 48 ), // #588
+ INST(Prefetchnta , X86M_Only , O(000F00,18,0,_,_,_,_,_ ), 0 , 4 , 0 , 2273 , 31 , 72 ), // #589
+ INST(Prefetcht0 , X86M_Only , O(000F00,18,1,_,_,_,_,_ ), 0 , 27 , 0 , 2285 , 31 , 72 ), // #590
+ INST(Prefetcht1 , X86M_Only , O(000F00,18,2,_,_,_,_,_ ), 0 , 69 , 0 , 2296 , 31 , 72 ), // #591
+ INST(Prefetcht2 , X86M_Only , O(000F00,18,3,_,_,_,_,_ ), 0 , 71 , 0 , 2307 , 31 , 72 ), // #592
+ INST(Prefetchw , X86M_Only , O(000F00,0D,1,_,_,_,_,_ ), 0 , 27 , 0 , 2318 , 31 , 92 ), // #593
+ INST(Prefetchwt1 , X86M_Only , O(000F00,0D,2,_,_,_,_,_ ), 0 , 69 , 0 , 2328 , 31 , 93 ), // #594
+ INST(Psadbw , ExtRm_P , O(000F00,F6,_,_,_,_,_,_ ), 0 , 4 , 0 , 4168 , 136, 82 ), // #595
+ INST(Pshufb , ExtRm_P , O(000F38,00,_,_,_,_,_,_ ), 0 , 77 , 0 , 8941 , 136, 81 ), // #596
+ INST(Pshufd , ExtRmi , O(660F00,70,_,_,_,_,_,_ ), 0 , 3 , 0 , 8962 , 8 , 4 ), // #597
+ INST(Pshufhw , ExtRmi , O(F30F00,70,_,_,_,_,_,_ ), 0 , 6 , 0 , 8970 , 8 , 4 ), // #598
+ INST(Pshuflw , ExtRmi , O(F20F00,70,_,_,_,_,_,_ ), 0 , 5 , 0 , 8979 , 8 , 4 ), // #599
+ INST(Pshufw , ExtRmi_P , O(000F00,70,_,_,_,_,_,_ ), 0 , 4 , 0 , 2340 , 157, 72 ), // #600
+ INST(Psignb , ExtRm_P , O(000F38,08,_,_,_,_,_,_ ), 0 , 77 , 0 , 8988 , 136, 81 ), // #601
+ INST(Psignd , ExtRm_P , O(000F38,0A,_,_,_,_,_,_ ), 0 , 77 , 0 , 8996 , 136, 81 ), // #602
+ INST(Psignw , ExtRm_P , O(000F38,09,_,_,_,_,_,_ ), 0 , 77 , 0 , 9004 , 136, 81 ), // #603
+ INST(Pslld , ExtRmRi_P , O(000F00,F2,_,_,_,_,_,_ ), O(000F00,72,6,_,_,_,_,_ ), 4 , 67 , 9012 , 158, 77 ), // #604
+ INST(Pslldq , ExtRmRi , 0 , O(660F00,73,7,_,_,_,_,_ ), 0 , 68 , 9019 , 159, 4 ), // #605
+ INST(Psllq , ExtRmRi_P , O(000F00,F3,_,_,_,_,_,_ ), O(000F00,73,6,_,_,_,_,_ ), 4 , 69 , 9027 , 158, 77 ), // #606
+ INST(Psllw , ExtRmRi_P , O(000F00,F1,_,_,_,_,_,_ ), O(000F00,71,6,_,_,_,_,_ ), 4 , 70 , 9058 , 158, 77 ), // #607
+ INST(Psmash , X86Op , O(F30F01,FF,_,_,_,_,_,_ ), 0 , 76 , 0 , 2347 , 156, 94 ), // #608
+ INST(Psrad , ExtRmRi_P , O(000F00,E2,_,_,_,_,_,_ ), O(000F00,72,4,_,_,_,_,_ ), 4 , 71 , 9065 , 158, 77 ), // #609
+ INST(Psraw , ExtRmRi_P , O(000F00,E1,_,_,_,_,_,_ ), O(000F00,71,4,_,_,_,_,_ ), 4 , 72 , 9103 , 158, 77 ), // #610
+ INST(Psrld , ExtRmRi_P , O(000F00,D2,_,_,_,_,_,_ ), O(000F00,72,2,_,_,_,_,_ ), 4 , 73 , 9110 , 158, 77 ), // #611
+ INST(Psrldq , ExtRmRi , 0 , O(660F00,73,3,_,_,_,_,_ ), 0 , 74 , 9117 , 159, 4 ), // #612
+ INST(Psrlq , ExtRmRi_P , O(000F00,D3,_,_,_,_,_,_ ), O(000F00,73,2,_,_,_,_,_ ), 4 , 75 , 9125 , 158, 77 ), // #613
+ INST(Psrlw , ExtRmRi_P , O(000F00,D1,_,_,_,_,_,_ ), O(000F00,71,2,_,_,_,_,_ ), 4 , 76 , 9156 , 158, 77 ), // #614
+ INST(Psubb , ExtRm_P , O(000F00,F8,_,_,_,_,_,_ ), 0 , 4 , 0 , 9163 , 139, 77 ), // #615
+ INST(Psubd , ExtRm_P , O(000F00,FA,_,_,_,_,_,_ ), 0 , 4 , 0 , 9170 , 139, 77 ), // #616
+ INST(Psubq , ExtRm_P , O(000F00,FB,_,_,_,_,_,_ ), 0 , 4 , 0 , 9177 , 139, 4 ), // #617
+ INST(Psubsb , ExtRm_P , O(000F00,E8,_,_,_,_,_,_ ), 0 , 4 , 0 , 9184 , 139, 77 ), // #618
+ INST(Psubsw , ExtRm_P , O(000F00,E9,_,_,_,_,_,_ ), 0 , 4 , 0 , 9192 , 139, 77 ), // #619
+ INST(Psubusb , ExtRm_P , O(000F00,D8,_,_,_,_,_,_ ), 0 , 4 , 0 , 9200 , 139, 77 ), // #620
+ INST(Psubusw , ExtRm_P , O(000F00,D9,_,_,_,_,_,_ ), 0 , 4 , 0 , 9209 , 139, 77 ), // #621
+ INST(Psubw , ExtRm_P , O(000F00,F9,_,_,_,_,_,_ ), 0 , 4 , 0 , 9218 , 139, 77 ), // #622
+ INST(Pswapd , Ext3dNow , O(000F0F,BB,_,_,_,_,_,_ ), 0 , 82 , 0 , 2354 , 140, 88 ), // #623
+ INST(Ptest , ExtRm , O(660F38,17,_,_,_,_,_,_ ), 0 , 2 , 0 , 9247 , 5 , 95 ), // #624
+ INST(Punpckhbw , ExtRm_P , O(000F00,68,_,_,_,_,_,_ ), 0 , 4 , 0 , 9330 , 136, 77 ), // #625
+ INST(Punpckhdq , ExtRm_P , O(000F00,6A,_,_,_,_,_,_ ), 0 , 4 , 0 , 9341 , 136, 77 ), // #626
+ INST(Punpckhqdq , ExtRm , O(660F00,6D,_,_,_,_,_,_ ), 0 , 3 , 0 , 9352 , 5 , 4 ), // #627
+ INST(Punpckhwd , ExtRm_P , O(000F00,69,_,_,_,_,_,_ ), 0 , 4 , 0 , 9364 , 136, 77 ), // #628
+ INST(Punpcklbw , ExtRm_P , O(000F00,60,_,_,_,_,_,_ ), 0 , 4 , 0 , 9375 , 136, 77 ), // #629
+ INST(Punpckldq , ExtRm_P , O(000F00,62,_,_,_,_,_,_ ), 0 , 4 , 0 , 9386 , 136, 77 ), // #630
+ INST(Punpcklqdq , ExtRm , O(660F00,6C,_,_,_,_,_,_ ), 0 , 3 , 0 , 9397 , 5 , 4 ), // #631
+ INST(Punpcklwd , ExtRm_P , O(000F00,61,_,_,_,_,_,_ ), 0 , 4 , 0 , 9409 , 136, 77 ), // #632
+ INST(Push , X86Push , O(000000,FF,6,_,_,_,_,_ ), O(000000,50,_,_,_,_,_,_ ), 30 , 77 , 2361 , 160, 0 ), // #633
+ INST(Pusha , X86Op , O(660000,60,_,_,_,_,_,_ ), 0 , 19 , 0 , 2366 , 75 , 0 ), // #634
+ INST(Pushad , X86Op , O(000000,60,_,_,_,_,_,_ ), 0 , 0 , 0 , 2372 , 75 , 0 ), // #635
+ INST(Pushf , X86Op , O(660000,9C,_,_,_,_,_,_ ), 0 , 19 , 0 , 2379 , 30 , 96 ), // #636
+ INST(Pushfd , X86Op , O(000000,9C,_,_,_,_,_,_ ), 0 , 0 , 0 , 2385 , 75 , 96 ), // #637
+ INST(Pushfq , X86Op , O(000000,9C,_,_,_,_,_,_ ), 0 , 0 , 0 , 2392 , 156, 96 ), // #638
+ INST(Pvalidate , X86Op , O(F20F01,FF,_,_,_,_,_,_ ), 0 , 86 , 0 , 2399 , 30 , 97 ), // #639
+ INST(Pxor , ExtRm_P , O(000F00,EF,_,_,_,_,_,_ ), 0 , 4 , 0 , 9420 , 139, 77 ), // #640
+ INST(Rcl , X86Rot , O(000000,D0,2,_,x,_,_,_ ), 0 , 1 , 0 , 2409 , 161, 98 ), // #641
+ INST(Rcpps , ExtRm , O(000F00,53,_,_,_,_,_,_ ), 0 , 4 , 0 , 9548 , 5 , 5 ), // #642
+ INST(Rcpss , ExtRm , O(F30F00,53,_,_,_,_,_,_ ), 0 , 6 , 0 , 9555 , 7 , 5 ), // #643
+ INST(Rcr , X86Rot , O(000000,D0,3,_,x,_,_,_ ), 0 , 79 , 0 , 2413 , 161, 98 ), // #644
+ INST(Rdfsbase , X86M , O(F30F00,AE,0,_,x,_,_,_ ), 0 , 6 , 0 , 2417 , 162, 99 ), // #645
+ INST(Rdgsbase , X86M , O(F30F00,AE,1,_,x,_,_,_ ), 0 , 87 , 0 , 2426 , 162, 99 ), // #646
+ INST(Rdmsr , X86Op , O(000F00,32,_,_,_,_,_,_ ), 0 , 4 , 0 , 2435 , 163, 100), // #647
+ INST(Rdpid , X86R_Native , O(F30F00,C7,7,_,_,_,_,_ ), 0 , 88 , 0 , 2441 , 164, 101), // #648
+ INST(Rdpmc , X86Op , O(000F00,33,_,_,_,_,_,_ ), 0 , 4 , 0 , 2447 , 163, 0 ), // #649
+ INST(Rdpru , X86Op , O(000F01,FD,_,_,_,_,_,_ ), 0 , 21 , 0 , 2453 , 165, 102), // #650
+ INST(Rdrand , X86M , O(000F00,C7,6,_,x,_,_,_ ), 0 , 73 , 0 , 2459 , 23 , 103), // #651
+ INST(Rdseed , X86M , O(000F00,C7,7,_,x,_,_,_ ), 0 , 22 , 0 , 2466 , 23 , 104), // #652
+ INST(Rdtsc , X86Op , O(000F00,31,_,_,_,_,_,_ ), 0 , 4 , 0 , 2473 , 28 , 105), // #653
+ INST(Rdtscp , X86Op , O(000F01,F9,_,_,_,_,_,_ ), 0 , 21 , 0 , 2479 , 163, 106), // #654
+ INST(Ret , X86Ret , O(000000,C2,_,_,_,_,_,_ ), 0 , 0 , 0 , 2952 , 166, 0 ), // #655
+ INST(Rmpadjust , X86Op , O(F30F01,FE,_,_,_,_,_,_ ), 0 , 76 , 0 , 2486 , 156, 94 ), // #656
+ INST(Rmpupdate , X86Op , O(F20F01,FE,_,_,_,_,_,_ ), 0 , 86 , 0 , 2496 , 156, 94 ), // #657
+ INST(Rol , X86Rot , O(000000,D0,0,_,x,_,_,_ ), 0 , 0 , 0 , 2506 , 161, 107), // #658
+ INST(Ror , X86Rot , O(000000,D0,1,_,x,_,_,_ ), 0 , 29 , 0 , 2510 , 161, 107), // #659
+ INST(Rorx , VexRmi_Wx , V(F20F3A,F0,_,0,x,_,_,_ ), 0 , 89 , 0 , 2514 , 167, 80 ), // #660
+ INST(Roundpd , ExtRmi , O(660F3A,09,_,_,_,_,_,_ ), 0 , 8 , 0 , 9650 , 8 , 12 ), // #661
+ INST(Roundps , ExtRmi , O(660F3A,08,_,_,_,_,_,_ ), 0 , 8 , 0 , 9659 , 8 , 12 ), // #662
+ INST(Roundsd , ExtRmi , O(660F3A,0B,_,_,_,_,_,_ ), 0 , 8 , 0 , 9668 , 35 , 12 ), // #663
+ INST(Roundss , ExtRmi , O(660F3A,0A,_,_,_,_,_,_ ), 0 , 8 , 0 , 9677 , 36 , 12 ), // #664
+ INST(Rsm , X86Op , O(000F00,AA,_,_,_,_,_,_ ), 0 , 4 , 0 , 2519 , 75 , 1 ), // #665
+ INST(Rsqrtps , ExtRm , O(000F00,52,_,_,_,_,_,_ ), 0 , 4 , 0 , 9774 , 5 , 5 ), // #666
+ INST(Rsqrtss , ExtRm , O(F30F00,52,_,_,_,_,_,_ ), 0 , 6 , 0 , 9783 , 7 , 5 ), // #667
+ INST(Sahf , X86Op , O(000000,9E,_,_,_,_,_,_ ), 0 , 0 , 0 , 2523 , 90 , 108), // #668
+ INST(Sal , X86Rot , O(000000,D0,4,_,x,_,_,_ ), 0 , 9 , 0 , 2528 , 161, 1 ), // #669
+ INST(Sar , X86Rot , O(000000,D0,7,_,x,_,_,_ ), 0 , 25 , 0 , 2532 , 161, 1 ), // #670
+ INST(Sarx , VexRmv_Wx , V(F30F38,F7,_,0,x,_,_,_ ), 0 , 83 , 0 , 2536 , 13 , 80 ), // #671
+ INST(Sbb , X86Arith , O(000000,18,3,_,x,_,_,_ ), 0 , 79 , 0 , 2541 , 168, 2 ), // #672
+ INST(Scas , X86StrRm , O(000000,AE,_,_,_,_,_,_ ), 0 , 0 , 0 , 2545 , 169, 35 ), // #673
+ INST(Serialize , X86Op , O(000F01,E8,_,_,_,_,_,_ ), 0 , 21 , 0 , 2550 , 30 , 109), // #674
+ INST(Seta , X86Set , O(000F00,97,_,_,_,_,_,_ ), 0 , 4 , 0 , 2560 , 170, 54 ), // #675
+ INST(Setae , X86Set , O(000F00,93,_,_,_,_,_,_ ), 0 , 4 , 0 , 2565 , 170, 55 ), // #676
+ INST(Setb , X86Set , O(000F00,92,_,_,_,_,_,_ ), 0 , 4 , 0 , 2571 , 170, 55 ), // #677
+ INST(Setbe , X86Set , O(000F00,96,_,_,_,_,_,_ ), 0 , 4 , 0 , 2576 , 170, 54 ), // #678
+ INST(Setc , X86Set , O(000F00,92,_,_,_,_,_,_ ), 0 , 4 , 0 , 2582 , 170, 55 ), // #679
+ INST(Sete , X86Set , O(000F00,94,_,_,_,_,_,_ ), 0 , 4 , 0 , 2587 , 170, 56 ), // #680
+ INST(Setg , X86Set , O(000F00,9F,_,_,_,_,_,_ ), 0 , 4 , 0 , 2592 , 170, 57 ), // #681
+ INST(Setge , X86Set , O(000F00,9D,_,_,_,_,_,_ ), 0 , 4 , 0 , 2597 , 170, 58 ), // #682
+ INST(Setl , X86Set , O(000F00,9C,_,_,_,_,_,_ ), 0 , 4 , 0 , 2603 , 170, 58 ), // #683
+ INST(Setle , X86Set , O(000F00,9E,_,_,_,_,_,_ ), 0 , 4 , 0 , 2608 , 170, 57 ), // #684
+ INST(Setna , X86Set , O(000F00,96,_,_,_,_,_,_ ), 0 , 4 , 0 , 2614 , 170, 54 ), // #685
+ INST(Setnae , X86Set , O(000F00,92,_,_,_,_,_,_ ), 0 , 4 , 0 , 2620 , 170, 55 ), // #686
+ INST(Setnb , X86Set , O(000F00,93,_,_,_,_,_,_ ), 0 , 4 , 0 , 2627 , 170, 55 ), // #687
+ INST(Setnbe , X86Set , O(000F00,97,_,_,_,_,_,_ ), 0 , 4 , 0 , 2633 , 170, 54 ), // #688
+ INST(Setnc , X86Set , O(000F00,93,_,_,_,_,_,_ ), 0 , 4 , 0 , 2640 , 170, 55 ), // #689
+ INST(Setne , X86Set , O(000F00,95,_,_,_,_,_,_ ), 0 , 4 , 0 , 2646 , 170, 56 ), // #690
+ INST(Setng , X86Set , O(000F00,9E,_,_,_,_,_,_ ), 0 , 4 , 0 , 2652 , 170, 57 ), // #691
+ INST(Setnge , X86Set , O(000F00,9C,_,_,_,_,_,_ ), 0 , 4 , 0 , 2658 , 170, 58 ), // #692
+ INST(Setnl , X86Set , O(000F00,9D,_,_,_,_,_,_ ), 0 , 4 , 0 , 2665 , 170, 58 ), // #693
+ INST(Setnle , X86Set , O(000F00,9F,_,_,_,_,_,_ ), 0 , 4 , 0 , 2671 , 170, 57 ), // #694
+ INST(Setno , X86Set , O(000F00,91,_,_,_,_,_,_ ), 0 , 4 , 0 , 2678 , 170, 52 ), // #695
+ INST(Setnp , X86Set , O(000F00,9B,_,_,_,_,_,_ ), 0 , 4 , 0 , 2684 , 170, 59 ), // #696
+ INST(Setns , X86Set , O(000F00,99,_,_,_,_,_,_ ), 0 , 4 , 0 , 2690 , 170, 60 ), // #697
+ INST(Setnz , X86Set , O(000F00,95,_,_,_,_,_,_ ), 0 , 4 , 0 , 2696 , 170, 56 ), // #698
+ INST(Seto , X86Set , O(000F00,90,_,_,_,_,_,_ ), 0 , 4 , 0 , 2702 , 170, 52 ), // #699
+ INST(Setp , X86Set , O(000F00,9A,_,_,_,_,_,_ ), 0 , 4 , 0 , 2707 , 170, 59 ), // #700
+ INST(Setpe , X86Set , O(000F00,9A,_,_,_,_,_,_ ), 0 , 4 , 0 , 2712 , 170, 59 ), // #701
+ INST(Setpo , X86Set , O(000F00,9B,_,_,_,_,_,_ ), 0 , 4 , 0 , 2718 , 170, 59 ), // #702
+ INST(Sets , X86Set , O(000F00,98,_,_,_,_,_,_ ), 0 , 4 , 0 , 2724 , 170, 60 ), // #703
+ INST(Setz , X86Set , O(000F00,94,_,_,_,_,_,_ ), 0 , 4 , 0 , 2729 , 170, 56 ), // #704
+ INST(Sfence , X86Fence , O(000F00,AE,7,_,_,_,_,_ ), 0 , 22 , 0 , 2734 , 30 , 72 ), // #705
+ INST(Sgdt , X86M_Only , O(000F00,01,0,_,_,_,_,_ ), 0 , 4 , 0 , 2741 , 31 , 0 ), // #706
+ INST(Sha1msg1 , ExtRm , O(000F38,C9,_,_,_,_,_,_ ), 0 , 77 , 0 , 2746 , 5 , 110), // #707
+ INST(Sha1msg2 , ExtRm , O(000F38,CA,_,_,_,_,_,_ ), 0 , 77 , 0 , 2755 , 5 , 110), // #708
+ INST(Sha1nexte , ExtRm , O(000F38,C8,_,_,_,_,_,_ ), 0 , 77 , 0 , 2764 , 5 , 110), // #709
+ INST(Sha1rnds4 , ExtRmi , O(000F3A,CC,_,_,_,_,_,_ ), 0 , 80 , 0 , 2774 , 8 , 110), // #710
+ INST(Sha256msg1 , ExtRm , O(000F38,CC,_,_,_,_,_,_ ), 0 , 77 , 0 , 2784 , 5 , 110), // #711
+ INST(Sha256msg2 , ExtRm , O(000F38,CD,_,_,_,_,_,_ ), 0 , 77 , 0 , 2795 , 5 , 110), // #712
+ INST(Sha256rnds2 , ExtRm_XMM0 , O(000F38,CB,_,_,_,_,_,_ ), 0 , 77 , 0 , 2806 , 15 , 110), // #713
+ INST(Shl , X86Rot , O(000000,D0,4,_,x,_,_,_ ), 0 , 9 , 0 , 2818 , 161, 1 ), // #714
+ INST(Shld , X86ShldShrd , O(000F00,A4,_,_,x,_,_,_ ), 0 , 4 , 0 , 8819 , 171, 1 ), // #715
+ INST(Shlx , VexRmv_Wx , V(660F38,F7,_,0,x,_,_,_ ), 0 , 90 , 0 , 2822 , 13 , 80 ), // #716
+ INST(Shr , X86Rot , O(000000,D0,5,_,x,_,_,_ ), 0 , 58 , 0 , 2827 , 161, 1 ), // #717
+ INST(Shrd , X86ShldShrd , O(000F00,AC,_,_,x,_,_,_ ), 0 , 4 , 0 , 2831 , 171, 1 ), // #718
+ INST(Shrx , VexRmv_Wx , V(F20F38,F7,_,0,x,_,_,_ ), 0 , 78 , 0 , 2836 , 13 , 80 ), // #719
+ INST(Shufpd , ExtRmi , O(660F00,C6,_,_,_,_,_,_ ), 0 , 3 , 0 , 10044, 8 , 4 ), // #720
+ INST(Shufps , ExtRmi , O(000F00,C6,_,_,_,_,_,_ ), 0 , 4 , 0 , 10052, 8 , 5 ), // #721
+ INST(Sidt , X86M_Only , O(000F00,01,1,_,_,_,_,_ ), 0 , 27 , 0 , 2841 , 31 , 0 ), // #722
+ INST(Skinit , X86Op_xAX , O(000F01,DE,_,_,_,_,_,_ ), 0 , 21 , 0 , 2846 , 50 , 111), // #723
+ INST(Sldt , X86M , O(000F00,00,0,_,_,_,_,_ ), 0 , 4 , 0 , 2853 , 172, 0 ), // #724
+ INST(Slwpcb , VexR_Wx , V(XOP_M9,12,1,0,x,_,_,_ ), 0 , 11 , 0 , 2858 , 99 , 69 ), // #725
+ INST(Smsw , X86M , O(000F00,01,4,_,_,_,_,_ ), 0 , 91 , 0 , 2865 , 172, 0 ), // #726
+ INST(Sqrtpd , ExtRm , O(660F00,51,_,_,_,_,_,_ ), 0 , 3 , 0 , 10060, 5 , 4 ), // #727
+ INST(Sqrtps , ExtRm , O(000F00,51,_,_,_,_,_,_ ), 0 , 4 , 0 , 9775 , 5 , 5 ), // #728
+ INST(Sqrtsd , ExtRm , O(F20F00,51,_,_,_,_,_,_ ), 0 , 5 , 0 , 10076, 6 , 4 ), // #729
+ INST(Sqrtss , ExtRm , O(F30F00,51,_,_,_,_,_,_ ), 0 , 6 , 0 , 9784 , 7 , 5 ), // #730
+ INST(Stac , X86Op , O(000F01,CB,_,_,_,_,_,_ ), 0 , 21 , 0 , 2870 , 30 , 16 ), // #731
+ INST(Stc , X86Op , O(000000,F9,_,_,_,_,_,_ ), 0 , 0 , 0 , 2875 , 30 , 17 ), // #732
+ INST(Std , X86Op , O(000000,FD,_,_,_,_,_,_ ), 0 , 0 , 0 , 6802 , 30 , 18 ), // #733
+ INST(Stgi , X86Op , O(000F01,DC,_,_,_,_,_,_ ), 0 , 21 , 0 , 2879 , 30 , 111), // #734
+ INST(Sti , X86Op , O(000000,FB,_,_,_,_,_,_ ), 0 , 0 , 0 , 2884 , 30 , 23 ), // #735
+ INST(Stmxcsr , X86M_Only , O(000F00,AE,3,_,_,_,_,_ ), 0 , 71 , 0 , 10092, 93 , 5 ), // #736
+ INST(Stos , X86StrMr , O(000000,AA,_,_,_,_,_,_ ), 0 , 0 , 0 , 2888 , 173, 70 ), // #737
+ INST(Str , X86M , O(000F00,00,1,_,_,_,_,_ ), 0 , 27 , 0 , 2893 , 172, 0 ), // #738
+ INST(Sttilecfg , AmxCfg , V(660F38,49,_,0,0,_,_,_ ), 0 , 90 , 0 , 2897 , 95 , 68 ), // #739
+ INST(Sub , X86Arith , O(000000,28,5,_,x,_,_,_ ), 0 , 58 , 0 , 836 , 168, 1 ), // #740
+ INST(Subpd , ExtRm , O(660F00,5C,_,_,_,_,_,_ ), 0 , 3 , 0 , 4744 , 5 , 4 ), // #741
+ INST(Subps , ExtRm , O(000F00,5C,_,_,_,_,_,_ ), 0 , 4 , 0 , 4756 , 5 , 5 ), // #742
+ INST(Subsd , ExtRm , O(F20F00,5C,_,_,_,_,_,_ ), 0 , 5 , 0 , 5432 , 6 , 4 ), // #743
+ INST(Subss , ExtRm , O(F30F00,5C,_,_,_,_,_,_ ), 0 , 6 , 0 , 5442 , 7 , 5 ), // #744
+ INST(Swapgs , X86Op , O(000F01,F8,_,_,_,_,_,_ ), 0 , 21 , 0 , 2907 , 156, 0 ), // #745
+ INST(Syscall , X86Op , O(000F00,05,_,_,_,_,_,_ ), 0 , 4 , 0 , 2914 , 156, 0 ), // #746
+ INST(Sysenter , X86Op , O(000F00,34,_,_,_,_,_,_ ), 0 , 4 , 0 , 2922 , 30 , 0 ), // #747
+ INST(Sysexit , X86Op , O(000F00,35,_,_,_,_,_,_ ), 0 , 4 , 0 , 2931 , 30 , 0 ), // #748
+ INST(Sysexit64 , X86Op , O(000F00,35,_,_,_,_,_,_ ), 0 , 4 , 0 , 2939 , 30 , 0 ), // #749
+ INST(Sysret , X86Op , O(000F00,07,_,_,_,_,_,_ ), 0 , 4 , 0 , 2949 , 156, 0 ), // #750
+ INST(Sysret64 , X86Op , O(000F00,07,_,_,_,_,_,_ ), 0 , 4 , 0 , 2956 , 156, 0 ), // #751
+ INST(T1mskc , VexVm_Wx , V(XOP_M9,01,7,0,x,_,_,_ ), 0 , 92 , 0 , 2965 , 14 , 11 ), // #752
+ INST(Tdpbf16ps , AmxRmv , V(F30F38,5C,_,0,0,_,_,_ ), 0 , 83 , 0 , 2972 , 174, 112), // #753
+ INST(Tdpbssd , AmxRmv , V(F20F38,5E,_,0,0,_,_,_ ), 0 , 78 , 0 , 2982 , 174, 113), // #754
+ INST(Tdpbsud , AmxRmv , V(F30F38,5E,_,0,0,_,_,_ ), 0 , 83 , 0 , 2990 , 174, 113), // #755
+ INST(Tdpbusd , AmxRmv , V(660F38,5E,_,0,0,_,_,_ ), 0 , 90 , 0 , 2998 , 174, 113), // #756
+ INST(Tdpbuud , AmxRmv , V(000F38,5E,_,0,0,_,_,_ ), 0 , 10 , 0 , 3006 , 174, 113), // #757
+ INST(Test , X86Test , O(000000,84,_,_,x,_,_,_ ), O(000000,F6,_,_,x,_,_,_ ), 0 , 78 , 9248 , 175, 1 ), // #758
+ INST(Tileloadd , AmxRm , V(F20F38,4B,_,0,0,_,_,_ ), 0 , 78 , 0 , 3014 , 176, 68 ), // #759
+ INST(Tileloaddt1 , AmxRm , V(660F38,4B,_,0,0,_,_,_ ), 0 , 90 , 0 , 3024 , 176, 68 ), // #760
+ INST(Tilerelease , VexOpMod , V(000F38,49,0,0,0,_,_,_ ), 0 , 10 , 0 , 3036 , 177, 68 ), // #761
+ INST(Tilestored , AmxMr , V(F30F38,4B,_,0,0,_,_,_ ), 0 , 83 , 0 , 3048 , 178, 68 ), // #762
+ INST(Tilezero , AmxR , V(F20F38,49,_,0,0,_,_,_ ), 0 , 78 , 0 , 3059 , 179, 68 ), // #763
+ INST(Tpause , X86R32_EDX_EAX , O(660F00,AE,6,_,_,_,_,_ ), 0 , 24 , 0 , 3068 , 180, 114), // #764
+ INST(Tzcnt , X86Rm_Raw66H , O(F30F00,BC,_,_,x,_,_,_ ), 0 , 6 , 0 , 3075 , 22 , 9 ), // #765
+ INST(Tzmsk , VexVm_Wx , V(XOP_M9,01,4,0,x,_,_,_ ), 0 , 93 , 0 , 3081 , 14 , 11 ), // #766
+ INST(Ucomisd , ExtRm , O(660F00,2E,_,_,_,_,_,_ ), 0 , 3 , 0 , 10145, 6 , 39 ), // #767
+ INST(Ucomiss , ExtRm , O(000F00,2E,_,_,_,_,_,_ ), 0 , 4 , 0 , 10154, 7 , 40 ), // #768
+ INST(Ud2 , X86Op , O(000F00,0B,_,_,_,_,_,_ ), 0 , 4 , 0 , 3087 , 30 , 0 ), // #769
+ INST(Umonitor , X86R_FromM , O(F30F00,AE,6,_,_,_,_,_ ), 0 , 94 , 0 , 3091 , 181, 115), // #770
+ INST(Umwait , X86R32_EDX_EAX , O(F20F00,AE,6,_,_,_,_,_ ), 0 , 95 , 0 , 3100 , 180, 114), // #771
+ INST(Unpckhpd , ExtRm , O(660F00,15,_,_,_,_,_,_ ), 0 , 3 , 0 , 10163, 5 , 4 ), // #772
+ INST(Unpckhps , ExtRm , O(000F00,15,_,_,_,_,_,_ ), 0 , 4 , 0 , 10173, 5 , 5 ), // #773
+ INST(Unpcklpd , ExtRm , O(660F00,14,_,_,_,_,_,_ ), 0 , 3 , 0 , 10183, 5 , 4 ), // #774
+ INST(Unpcklps , ExtRm , O(000F00,14,_,_,_,_,_,_ ), 0 , 4 , 0 , 10193, 5 , 5 ), // #775
+ INST(V4fmaddps , VexRm_T1_4X , E(F20F38,9A,_,2,_,0,2,T4X), 0 , 96 , 0 , 3107 , 182, 116), // #776
+ INST(V4fmaddss , VexRm_T1_4X , E(F20F38,9B,_,2,_,0,2,T4X), 0 , 96 , 0 , 3117 , 183, 116), // #777
+ INST(V4fnmaddps , VexRm_T1_4X , E(F20F38,AA,_,2,_,0,2,T4X), 0 , 96 , 0 , 3127 , 182, 116), // #778
+ INST(V4fnmaddss , VexRm_T1_4X , E(F20F38,AB,_,2,_,0,2,T4X), 0 , 96 , 0 , 3138 , 183, 116), // #779
+ INST(Vaddpd , VexRvm_Lx , V(660F00,58,_,x,I,1,4,FV ), 0 , 97 , 0 , 3149 , 184, 117), // #780
+ INST(Vaddps , VexRvm_Lx , V(000F00,58,_,x,I,0,4,FV ), 0 , 98 , 0 , 3156 , 185, 117), // #781
+ INST(Vaddsd , VexRvm , V(F20F00,58,_,I,I,1,3,T1S), 0 , 99 , 0 , 3163 , 186, 118), // #782
+ INST(Vaddss , VexRvm , V(F30F00,58,_,I,I,0,2,T1S), 0 , 100, 0 , 3170 , 187, 118), // #783
+ INST(Vaddsubpd , VexRvm_Lx , V(660F00,D0,_,x,I,_,_,_ ), 0 , 63 , 0 , 3177 , 188, 119), // #784
+ INST(Vaddsubps , VexRvm_Lx , V(F20F00,D0,_,x,I,_,_,_ ), 0 , 101, 0 , 3187 , 188, 119), // #785
+ INST(Vaesdec , VexRvm_Lx , V(660F38,DE,_,x,I,_,4,FVM), 0 , 102, 0 , 3197 , 189, 120), // #786
+ INST(Vaesdeclast , VexRvm_Lx , V(660F38,DF,_,x,I,_,4,FVM), 0 , 102, 0 , 3205 , 189, 120), // #787
+ INST(Vaesenc , VexRvm_Lx , V(660F38,DC,_,x,I,_,4,FVM), 0 , 102, 0 , 3217 , 189, 120), // #788
+ INST(Vaesenclast , VexRvm_Lx , V(660F38,DD,_,x,I,_,4,FVM), 0 , 102, 0 , 3225 , 189, 120), // #789
+ INST(Vaesimc , VexRm , V(660F38,DB,_,0,I,_,_,_ ), 0 , 90 , 0 , 3237 , 190, 121), // #790
+ INST(Vaeskeygenassist , VexRmi , V(660F3A,DF,_,0,I,_,_,_ ), 0 , 67 , 0 , 3245 , 191, 121), // #791
+ INST(Valignd , VexRvmi_Lx , E(660F3A,03,_,x,_,0,4,FV ), 0 , 103, 0 , 3262 , 192, 122), // #792
+ INST(Valignq , VexRvmi_Lx , E(660F3A,03,_,x,_,1,4,FV ), 0 , 104, 0 , 3270 , 193, 122), // #793
+ INST(Vandnpd , VexRvm_Lx , V(660F00,55,_,x,I,1,4,FV ), 0 , 97 , 0 , 3278 , 194, 123), // #794
+ INST(Vandnps , VexRvm_Lx , V(000F00,55,_,x,I,0,4,FV ), 0 , 98 , 0 , 3286 , 195, 123), // #795
+ INST(Vandpd , VexRvm_Lx , V(660F00,54,_,x,I,1,4,FV ), 0 , 97 , 0 , 3294 , 196, 123), // #796
+ INST(Vandps , VexRvm_Lx , V(000F00,54,_,x,I,0,4,FV ), 0 , 98 , 0 , 3301 , 197, 123), // #797
+ INST(Vblendmb , VexRvm_Lx , E(660F38,66,_,x,_,0,4,FVM), 0 , 105, 0 , 3308 , 198, 124), // #798
+ INST(Vblendmd , VexRvm_Lx , E(660F38,64,_,x,_,0,4,FV ), 0 , 106, 0 , 3317 , 199, 122), // #799
+ INST(Vblendmpd , VexRvm_Lx , E(660F38,65,_,x,_,1,4,FV ), 0 , 107, 0 , 3326 , 200, 122), // #800
+ INST(Vblendmps , VexRvm_Lx , E(660F38,65,_,x,_,0,4,FV ), 0 , 106, 0 , 3336 , 199, 122), // #801
+ INST(Vblendmq , VexRvm_Lx , E(660F38,64,_,x,_,1,4,FV ), 0 , 107, 0 , 3346 , 200, 122), // #802
+ INST(Vblendmw , VexRvm_Lx , E(660F38,66,_,x,_,1,4,FVM), 0 , 108, 0 , 3355 , 198, 124), // #803
+ INST(Vblendpd , VexRvmi_Lx , V(660F3A,0D,_,x,I,_,_,_ ), 0 , 67 , 0 , 3364 , 201, 119), // #804
+ INST(Vblendps , VexRvmi_Lx , V(660F3A,0C,_,x,I,_,_,_ ), 0 , 67 , 0 , 3373 , 201, 119), // #805
+ INST(Vblendvpd , VexRvmr_Lx , V(660F3A,4B,_,x,0,_,_,_ ), 0 , 67 , 0 , 3382 , 202, 119), // #806
+ INST(Vblendvps , VexRvmr_Lx , V(660F3A,4A,_,x,0,_,_,_ ), 0 , 67 , 0 , 3392 , 202, 119), // #807
+ INST(Vbroadcastf128 , VexRm , V(660F38,1A,_,1,0,_,_,_ ), 0 , 109, 0 , 3402 , 203, 119), // #808
+ INST(Vbroadcastf32x2 , VexRm_Lx , E(660F38,19,_,x,_,0,3,T2 ), 0 , 110, 0 , 3417 , 204, 125), // #809
+ INST(Vbroadcastf32x4 , VexRm_Lx , E(660F38,1A,_,x,_,0,4,T4 ), 0 , 111, 0 , 3433 , 205, 63 ), // #810
+ INST(Vbroadcastf32x8 , VexRm , E(660F38,1B,_,2,_,0,5,T8 ), 0 , 112, 0 , 3449 , 206, 61 ), // #811
+ INST(Vbroadcastf64x2 , VexRm_Lx , E(660F38,1A,_,x,_,1,4,T2 ), 0 , 113, 0 , 3465 , 205, 125), // #812
+ INST(Vbroadcastf64x4 , VexRm , E(660F38,1B,_,2,_,1,5,T4 ), 0 , 114, 0 , 3481 , 206, 63 ), // #813
+ INST(Vbroadcasti128 , VexRm , V(660F38,5A,_,1,0,_,_,_ ), 0 , 109, 0 , 3497 , 203, 126), // #814
+ INST(Vbroadcasti32x2 , VexRm_Lx , E(660F38,59,_,x,_,0,3,T2 ), 0 , 110, 0 , 3512 , 207, 125), // #815
+ INST(Vbroadcasti32x4 , VexRm_Lx , E(660F38,5A,_,x,_,0,4,T4 ), 0 , 111, 0 , 3528 , 205, 122), // #816
+ INST(Vbroadcasti32x8 , VexRm , E(660F38,5B,_,2,_,0,5,T8 ), 0 , 112, 0 , 3544 , 206, 61 ), // #817
+ INST(Vbroadcasti64x2 , VexRm_Lx , E(660F38,5A,_,x,_,1,4,T2 ), 0 , 113, 0 , 3560 , 205, 125), // #818
+ INST(Vbroadcasti64x4 , VexRm , E(660F38,5B,_,2,_,1,5,T4 ), 0 , 114, 0 , 3576 , 206, 63 ), // #819
+ INST(Vbroadcastsd , VexRm_Lx , V(660F38,19,_,x,0,1,3,T1S), 0 , 115, 0 , 3592 , 208, 127), // #820
+ INST(Vbroadcastss , VexRm_Lx , V(660F38,18,_,x,0,0,2,T1S), 0 , 116, 0 , 3605 , 209, 127), // #821
+ INST(Vcmppd , VexRvmi_Lx , V(660F00,C2,_,x,I,1,4,FV ), 0 , 97 , 0 , 3618 , 210, 117), // #822
+ INST(Vcmpps , VexRvmi_Lx , V(000F00,C2,_,x,I,0,4,FV ), 0 , 98 , 0 , 3625 , 211, 117), // #823
+ INST(Vcmpsd , VexRvmi , V(F20F00,C2,_,I,I,1,3,T1S), 0 , 99 , 0 , 3632 , 212, 118), // #824
+ INST(Vcmpss , VexRvmi , V(F30F00,C2,_,I,I,0,2,T1S), 0 , 100, 0 , 3639 , 213, 118), // #825
+ INST(Vcomisd , VexRm , V(660F00,2F,_,I,I,1,3,T1S), 0 , 117, 0 , 3646 , 214, 128), // #826
+ INST(Vcomiss , VexRm , V(000F00,2F,_,I,I,0,2,T1S), 0 , 118, 0 , 3654 , 215, 128), // #827
+ INST(Vcompresspd , VexMr_Lx , E(660F38,8A,_,x,_,1,3,T1S), 0 , 119, 0 , 3662 , 216, 122), // #828
+ INST(Vcompressps , VexMr_Lx , E(660F38,8A,_,x,_,0,2,T1S), 0 , 120, 0 , 3674 , 216, 122), // #829
+ INST(Vcvtdq2pd , VexRm_Lx , V(F30F00,E6,_,x,I,0,3,HV ), 0 , 121, 0 , 3686 , 217, 117), // #830
+ INST(Vcvtdq2ps , VexRm_Lx , V(000F00,5B,_,x,I,0,4,FV ), 0 , 98 , 0 , 3696 , 218, 117), // #831
+ INST(Vcvtne2ps2bf16 , VexRvm , E(F20F38,72,_,_,_,0,_,_ ), 0 , 122, 0 , 3706 , 199, 129), // #832
+ INST(Vcvtneps2bf16 , VexRm , E(F30F38,72,_,_,_,0,_,_ ), 0 , 123, 0 , 3721 , 219, 129), // #833
+ INST(Vcvtpd2dq , VexRm_Lx , V(F20F00,E6,_,x,I,1,4,FV ), 0 , 124, 0 , 3735 , 220, 117), // #834
+ INST(Vcvtpd2ps , VexRm_Lx , V(660F00,5A,_,x,I,1,4,FV ), 0 , 97 , 0 , 3745 , 220, 117), // #835
+ INST(Vcvtpd2qq , VexRm_Lx , E(660F00,7B,_,x,_,1,4,FV ), 0 , 125, 0 , 3755 , 221, 125), // #836
+ INST(Vcvtpd2udq , VexRm_Lx , E(000F00,79,_,x,_,1,4,FV ), 0 , 126, 0 , 3765 , 222, 122), // #837
+ INST(Vcvtpd2uqq , VexRm_Lx , E(660F00,79,_,x,_,1,4,FV ), 0 , 125, 0 , 3776 , 221, 125), // #838
+ INST(Vcvtph2ps , VexRm_Lx , V(660F38,13,_,x,0,0,3,HVM), 0 , 127, 0 , 3787 , 223, 130), // #839
+ INST(Vcvtps2dq , VexRm_Lx , V(660F00,5B,_,x,I,0,4,FV ), 0 , 128, 0 , 3797 , 218, 117), // #840
+ INST(Vcvtps2pd , VexRm_Lx , V(000F00,5A,_,x,I,0,4,HV ), 0 , 129, 0 , 3807 , 224, 117), // #841
+ INST(Vcvtps2ph , VexMri_Lx , V(660F3A,1D,_,x,0,0,3,HVM), 0 , 130, 0 , 3817 , 225, 130), // #842
+ INST(Vcvtps2qq , VexRm_Lx , E(660F00,7B,_,x,_,0,3,HV ), 0 , 131, 0 , 3827 , 226, 125), // #843
+ INST(Vcvtps2udq , VexRm_Lx , E(000F00,79,_,x,_,0,4,FV ), 0 , 132, 0 , 3837 , 227, 122), // #844
+ INST(Vcvtps2uqq , VexRm_Lx , E(660F00,79,_,x,_,0,3,HV ), 0 , 131, 0 , 3848 , 226, 125), // #845
+ INST(Vcvtqq2pd , VexRm_Lx , E(F30F00,E6,_,x,_,1,4,FV ), 0 , 133, 0 , 3859 , 221, 125), // #846
+ INST(Vcvtqq2ps , VexRm_Lx , E(000F00,5B,_,x,_,1,4,FV ), 0 , 126, 0 , 3869 , 222, 125), // #847
+ INST(Vcvtsd2si , VexRm_Wx , V(F20F00,2D,_,I,x,x,3,T1F), 0 , 134, 0 , 3879 , 228, 118), // #848
+ INST(Vcvtsd2ss , VexRvm , V(F20F00,5A,_,I,I,1,3,T1S), 0 , 99 , 0 , 3889 , 186, 118), // #849
+ INST(Vcvtsd2usi , VexRm_Wx , E(F20F00,79,_,I,_,x,3,T1F), 0 , 135, 0 , 3899 , 229, 63 ), // #850
+ INST(Vcvtsi2sd , VexRvm_Wx , V(F20F00,2A,_,I,x,x,2,T1W), 0 , 136, 0 , 3910 , 230, 118), // #851
+ INST(Vcvtsi2ss , VexRvm_Wx , V(F30F00,2A,_,I,x,x,2,T1W), 0 , 137, 0 , 3920 , 230, 118), // #852
+ INST(Vcvtss2sd , VexRvm , V(F30F00,5A,_,I,I,0,2,T1S), 0 , 100, 0 , 3930 , 231, 118), // #853
+ INST(Vcvtss2si , VexRm_Wx , V(F30F00,2D,_,I,x,x,2,T1F), 0 , 138, 0 , 3940 , 232, 118), // #854
+ INST(Vcvtss2usi , VexRm_Wx , E(F30F00,79,_,I,_,x,2,T1F), 0 , 139, 0 , 3950 , 233, 63 ), // #855
+ INST(Vcvttpd2dq , VexRm_Lx , V(660F00,E6,_,x,I,1,4,FV ), 0 , 97 , 0 , 3961 , 234, 117), // #856
+ INST(Vcvttpd2qq , VexRm_Lx , E(660F00,7A,_,x,_,1,4,FV ), 0 , 125, 0 , 3972 , 235, 122), // #857
+ INST(Vcvttpd2udq , VexRm_Lx , E(000F00,78,_,x,_,1,4,FV ), 0 , 126, 0 , 3983 , 236, 122), // #858
+ INST(Vcvttpd2uqq , VexRm_Lx , E(660F00,78,_,x,_,1,4,FV ), 0 , 125, 0 , 3995 , 235, 125), // #859
+ INST(Vcvttps2dq , VexRm_Lx , V(F30F00,5B,_,x,I,0,4,FV ), 0 , 140, 0 , 4007 , 237, 117), // #860
+ INST(Vcvttps2qq , VexRm_Lx , E(660F00,7A,_,x,_,0,3,HV ), 0 , 131, 0 , 4018 , 238, 125), // #861
+ INST(Vcvttps2udq , VexRm_Lx , E(000F00,78,_,x,_,0,4,FV ), 0 , 132, 0 , 4029 , 239, 122), // #862
+ INST(Vcvttps2uqq , VexRm_Lx , E(660F00,78,_,x,_,0,3,HV ), 0 , 131, 0 , 4041 , 238, 125), // #863
+ INST(Vcvttsd2si , VexRm_Wx , V(F20F00,2C,_,I,x,x,3,T1F), 0 , 134, 0 , 4053 , 240, 118), // #864
+ INST(Vcvttsd2usi , VexRm_Wx , E(F20F00,78,_,I,_,x,3,T1F), 0 , 135, 0 , 4064 , 241, 63 ), // #865
+ INST(Vcvttss2si , VexRm_Wx , V(F30F00,2C,_,I,x,x,2,T1F), 0 , 138, 0 , 4076 , 242, 118), // #866
+ INST(Vcvttss2usi , VexRm_Wx , E(F30F00,78,_,I,_,x,2,T1F), 0 , 139, 0 , 4087 , 243, 63 ), // #867
+ INST(Vcvtudq2pd , VexRm_Lx , E(F30F00,7A,_,x,_,0,3,HV ), 0 , 141, 0 , 4099 , 244, 122), // #868
+ INST(Vcvtudq2ps , VexRm_Lx , E(F20F00,7A,_,x,_,0,4,FV ), 0 , 142, 0 , 4110 , 227, 122), // #869
+ INST(Vcvtuqq2pd , VexRm_Lx , E(F30F00,7A,_,x,_,1,4,FV ), 0 , 133, 0 , 4121 , 221, 125), // #870
+ INST(Vcvtuqq2ps , VexRm_Lx , E(F20F00,7A,_,x,_,1,4,FV ), 0 , 143, 0 , 4132 , 222, 125), // #871
+ INST(Vcvtusi2sd , VexRvm_Wx , E(F20F00,7B,_,I,_,x,2,T1W), 0 , 144, 0 , 4143 , 245, 63 ), // #872
+ INST(Vcvtusi2ss , VexRvm_Wx , E(F30F00,7B,_,I,_,x,2,T1W), 0 , 145, 0 , 4154 , 245, 63 ), // #873
+ INST(Vdbpsadbw , VexRvmi_Lx , E(660F3A,42,_,x,_,0,4,FVM), 0 , 146, 0 , 4165 , 246, 124), // #874
+ INST(Vdivpd , VexRvm_Lx , V(660F00,5E,_,x,I,1,4,FV ), 0 , 97 , 0 , 4175 , 184, 117), // #875
+ INST(Vdivps , VexRvm_Lx , V(000F00,5E,_,x,I,0,4,FV ), 0 , 98 , 0 , 4182 , 185, 117), // #876
+ INST(Vdivsd , VexRvm , V(F20F00,5E,_,I,I,1,3,T1S), 0 , 99 , 0 , 4189 , 186, 118), // #877
+ INST(Vdivss , VexRvm , V(F30F00,5E,_,I,I,0,2,T1S), 0 , 100, 0 , 4196 , 187, 118), // #878
+ INST(Vdpbf16ps , VexRvm , E(F30F38,52,_,_,_,0,_,_ ), 0 , 123, 0 , 4203 , 199, 129), // #879
+ INST(Vdppd , VexRvmi_Lx , V(660F3A,41,_,x,I,_,_,_ ), 0 , 67 , 0 , 4213 , 247, 119), // #880
+ INST(Vdpps , VexRvmi_Lx , V(660F3A,40,_,x,I,_,_,_ ), 0 , 67 , 0 , 4219 , 201, 119), // #881
+ INST(Verr , X86M_NoSize , O(000F00,00,4,_,_,_,_,_ ), 0 , 91 , 0 , 4225 , 98 , 10 ), // #882
+ INST(Verw , X86M_NoSize , O(000F00,00,5,_,_,_,_,_ ), 0 , 70 , 0 , 4230 , 98 , 10 ), // #883
+ INST(Vexp2pd , VexRm , E(660F38,C8,_,2,_,1,4,FV ), 0 , 147, 0 , 4235 , 248, 131), // #884
+ INST(Vexp2ps , VexRm , E(660F38,C8,_,2,_,0,4,FV ), 0 , 148, 0 , 4243 , 249, 131), // #885
+ INST(Vexpandpd , VexRm_Lx , E(660F38,88,_,x,_,1,3,T1S), 0 , 119, 0 , 4251 , 250, 122), // #886
+ INST(Vexpandps , VexRm_Lx , E(660F38,88,_,x,_,0,2,T1S), 0 , 120, 0 , 4261 , 250, 122), // #887
+ INST(Vextractf128 , VexMri , V(660F3A,19,_,1,0,_,_,_ ), 0 , 149, 0 , 4271 , 251, 119), // #888
+ INST(Vextractf32x4 , VexMri_Lx , E(660F3A,19,_,x,_,0,4,T4 ), 0 , 150, 0 , 4284 , 252, 122), // #889
+ INST(Vextractf32x8 , VexMri , E(660F3A,1B,_,2,_,0,5,T8 ), 0 , 151, 0 , 4298 , 253, 61 ), // #890
+ INST(Vextractf64x2 , VexMri_Lx , E(660F3A,19,_,x,_,1,4,T2 ), 0 , 152, 0 , 4312 , 252, 125), // #891
+ INST(Vextractf64x4 , VexMri , E(660F3A,1B,_,2,_,1,5,T4 ), 0 , 153, 0 , 4326 , 253, 63 ), // #892
+ INST(Vextracti128 , VexMri , V(660F3A,39,_,1,0,_,_,_ ), 0 , 149, 0 , 4340 , 251, 126), // #893
+ INST(Vextracti32x4 , VexMri_Lx , E(660F3A,39,_,x,_,0,4,T4 ), 0 , 150, 0 , 4353 , 252, 122), // #894
+ INST(Vextracti32x8 , VexMri , E(660F3A,3B,_,2,_,0,5,T8 ), 0 , 151, 0 , 4367 , 253, 61 ), // #895
+ INST(Vextracti64x2 , VexMri_Lx , E(660F3A,39,_,x,_,1,4,T2 ), 0 , 152, 0 , 4381 , 252, 125), // #896
+ INST(Vextracti64x4 , VexMri , E(660F3A,3B,_,2,_,1,5,T4 ), 0 , 153, 0 , 4395 , 253, 63 ), // #897
+ INST(Vextractps , VexMri , V(660F3A,17,_,0,I,I,2,T1S), 0 , 154, 0 , 4409 , 254, 118), // #898
+ INST(Vfixupimmpd , VexRvmi_Lx , E(660F3A,54,_,x,_,1,4,FV ), 0 , 104, 0 , 4420 , 255, 122), // #899
+ INST(Vfixupimmps , VexRvmi_Lx , E(660F3A,54,_,x,_,0,4,FV ), 0 , 103, 0 , 4432 , 256, 122), // #900
+ INST(Vfixupimmsd , VexRvmi , E(660F3A,55,_,I,_,1,3,T1S), 0 , 155, 0 , 4444 , 257, 63 ), // #901
+ INST(Vfixupimmss , VexRvmi , E(660F3A,55,_,I,_,0,2,T1S), 0 , 156, 0 , 4456 , 258, 63 ), // #902
+ INST(Vfmadd132pd , VexRvm_Lx , V(660F38,98,_,x,1,1,4,FV ), 0 , 157, 0 , 4468 , 184, 132), // #903
+ INST(Vfmadd132ps , VexRvm_Lx , V(660F38,98,_,x,0,0,4,FV ), 0 , 158, 0 , 4480 , 185, 132), // #904
+ INST(Vfmadd132sd , VexRvm , V(660F38,99,_,I,1,1,3,T1S), 0 , 159, 0 , 4492 , 186, 133), // #905
+ INST(Vfmadd132ss , VexRvm , V(660F38,99,_,I,0,0,2,T1S), 0 , 116, 0 , 4504 , 187, 133), // #906
+ INST(Vfmadd213pd , VexRvm_Lx , V(660F38,A8,_,x,1,1,4,FV ), 0 , 157, 0 , 4516 , 184, 132), // #907
+ INST(Vfmadd213ps , VexRvm_Lx , V(660F38,A8,_,x,0,0,4,FV ), 0 , 158, 0 , 4528 , 185, 132), // #908
+ INST(Vfmadd213sd , VexRvm , V(660F38,A9,_,I,1,1,3,T1S), 0 , 159, 0 , 4540 , 186, 133), // #909
+ INST(Vfmadd213ss , VexRvm , V(660F38,A9,_,I,0,0,2,T1S), 0 , 116, 0 , 4552 , 187, 133), // #910
+ INST(Vfmadd231pd , VexRvm_Lx , V(660F38,B8,_,x,1,1,4,FV ), 0 , 157, 0 , 4564 , 184, 132), // #911
+ INST(Vfmadd231ps , VexRvm_Lx , V(660F38,B8,_,x,0,0,4,FV ), 0 , 158, 0 , 4576 , 185, 132), // #912
+ INST(Vfmadd231sd , VexRvm , V(660F38,B9,_,I,1,1,3,T1S), 0 , 159, 0 , 4588 , 186, 133), // #913
+ INST(Vfmadd231ss , VexRvm , V(660F38,B9,_,I,0,0,2,T1S), 0 , 116, 0 , 4600 , 187, 133), // #914
+ INST(Vfmaddpd , Fma4_Lx , V(660F3A,69,_,x,x,_,_,_ ), 0 , 67 , 0 , 4612 , 259, 134), // #915
+ INST(Vfmaddps , Fma4_Lx , V(660F3A,68,_,x,x,_,_,_ ), 0 , 67 , 0 , 4621 , 259, 134), // #916
+ INST(Vfmaddsd , Fma4 , V(660F3A,6B,_,0,x,_,_,_ ), 0 , 67 , 0 , 4630 , 260, 134), // #917
+ INST(Vfmaddss , Fma4 , V(660F3A,6A,_,0,x,_,_,_ ), 0 , 67 , 0 , 4639 , 261, 134), // #918
+ INST(Vfmaddsub132pd , VexRvm_Lx , V(660F38,96,_,x,1,1,4,FV ), 0 , 157, 0 , 4648 , 184, 132), // #919
+ INST(Vfmaddsub132ps , VexRvm_Lx , V(660F38,96,_,x,0,0,4,FV ), 0 , 158, 0 , 4663 , 185, 132), // #920
+ INST(Vfmaddsub213pd , VexRvm_Lx , V(660F38,A6,_,x,1,1,4,FV ), 0 , 157, 0 , 4678 , 184, 132), // #921
+ INST(Vfmaddsub213ps , VexRvm_Lx , V(660F38,A6,_,x,0,0,4,FV ), 0 , 158, 0 , 4693 , 185, 132), // #922
+ INST(Vfmaddsub231pd , VexRvm_Lx , V(660F38,B6,_,x,1,1,4,FV ), 0 , 157, 0 , 4708 , 184, 132), // #923
+ INST(Vfmaddsub231ps , VexRvm_Lx , V(660F38,B6,_,x,0,0,4,FV ), 0 , 158, 0 , 4723 , 185, 132), // #924
+ INST(Vfmaddsubpd , Fma4_Lx , V(660F3A,5D,_,x,x,_,_,_ ), 0 , 67 , 0 , 4738 , 259, 134), // #925
+ INST(Vfmaddsubps , Fma4_Lx , V(660F3A,5C,_,x,x,_,_,_ ), 0 , 67 , 0 , 4750 , 259, 134), // #926
+ INST(Vfmsub132pd , VexRvm_Lx , V(660F38,9A,_,x,1,1,4,FV ), 0 , 157, 0 , 4762 , 184, 132), // #927
+ INST(Vfmsub132ps , VexRvm_Lx , V(660F38,9A,_,x,0,0,4,FV ), 0 , 158, 0 , 4774 , 185, 132), // #928
+ INST(Vfmsub132sd , VexRvm , V(660F38,9B,_,I,1,1,3,T1S), 0 , 159, 0 , 4786 , 186, 133), // #929
+ INST(Vfmsub132ss , VexRvm , V(660F38,9B,_,I,0,0,2,T1S), 0 , 116, 0 , 4798 , 187, 133), // #930
+ INST(Vfmsub213pd , VexRvm_Lx , V(660F38,AA,_,x,1,1,4,FV ), 0 , 157, 0 , 4810 , 184, 132), // #931
+ INST(Vfmsub213ps , VexRvm_Lx , V(660F38,AA,_,x,0,0,4,FV ), 0 , 158, 0 , 4822 , 185, 132), // #932
+ INST(Vfmsub213sd , VexRvm , V(660F38,AB,_,I,1,1,3,T1S), 0 , 159, 0 , 4834 , 186, 133), // #933
+ INST(Vfmsub213ss , VexRvm , V(660F38,AB,_,I,0,0,2,T1S), 0 , 116, 0 , 4846 , 187, 133), // #934
+ INST(Vfmsub231pd , VexRvm_Lx , V(660F38,BA,_,x,1,1,4,FV ), 0 , 157, 0 , 4858 , 184, 132), // #935
+ INST(Vfmsub231ps , VexRvm_Lx , V(660F38,BA,_,x,0,0,4,FV ), 0 , 158, 0 , 4870 , 185, 132), // #936
+ INST(Vfmsub231sd , VexRvm , V(660F38,BB,_,I,1,1,3,T1S), 0 , 159, 0 , 4882 , 186, 133), // #937
+ INST(Vfmsub231ss , VexRvm , V(660F38,BB,_,I,0,0,2,T1S), 0 , 116, 0 , 4894 , 187, 133), // #938
+ INST(Vfmsubadd132pd , VexRvm_Lx , V(660F38,97,_,x,1,1,4,FV ), 0 , 157, 0 , 4906 , 184, 132), // #939
+ INST(Vfmsubadd132ps , VexRvm_Lx , V(660F38,97,_,x,0,0,4,FV ), 0 , 158, 0 , 4921 , 185, 132), // #940
+ INST(Vfmsubadd213pd , VexRvm_Lx , V(660F38,A7,_,x,1,1,4,FV ), 0 , 157, 0 , 4936 , 184, 132), // #941
+ INST(Vfmsubadd213ps , VexRvm_Lx , V(660F38,A7,_,x,0,0,4,FV ), 0 , 158, 0 , 4951 , 185, 132), // #942
+ INST(Vfmsubadd231pd , VexRvm_Lx , V(660F38,B7,_,x,1,1,4,FV ), 0 , 157, 0 , 4966 , 184, 132), // #943
+ INST(Vfmsubadd231ps , VexRvm_Lx , V(660F38,B7,_,x,0,0,4,FV ), 0 , 158, 0 , 4981 , 185, 132), // #944
+ INST(Vfmsubaddpd , Fma4_Lx , V(660F3A,5F,_,x,x,_,_,_ ), 0 , 67 , 0 , 4996 , 259, 134), // #945
+ INST(Vfmsubaddps , Fma4_Lx , V(660F3A,5E,_,x,x,_,_,_ ), 0 , 67 , 0 , 5008 , 259, 134), // #946
+ INST(Vfmsubpd , Fma4_Lx , V(660F3A,6D,_,x,x,_,_,_ ), 0 , 67 , 0 , 5020 , 259, 134), // #947
+ INST(Vfmsubps , Fma4_Lx , V(660F3A,6C,_,x,x,_,_,_ ), 0 , 67 , 0 , 5029 , 259, 134), // #948
+ INST(Vfmsubsd , Fma4 , V(660F3A,6F,_,0,x,_,_,_ ), 0 , 67 , 0 , 5038 , 260, 134), // #949
+ INST(Vfmsubss , Fma4 , V(660F3A,6E,_,0,x,_,_,_ ), 0 , 67 , 0 , 5047 , 261, 134), // #950
+ INST(Vfnmadd132pd , VexRvm_Lx , V(660F38,9C,_,x,1,1,4,FV ), 0 , 157, 0 , 5056 , 184, 132), // #951
+ INST(Vfnmadd132ps , VexRvm_Lx , V(660F38,9C,_,x,0,0,4,FV ), 0 , 158, 0 , 5069 , 185, 132), // #952
+ INST(Vfnmadd132sd , VexRvm , V(660F38,9D,_,I,1,1,3,T1S), 0 , 159, 0 , 5082 , 186, 133), // #953
+ INST(Vfnmadd132ss , VexRvm , V(660F38,9D,_,I,0,0,2,T1S), 0 , 116, 0 , 5095 , 187, 133), // #954
+ INST(Vfnmadd213pd , VexRvm_Lx , V(660F38,AC,_,x,1,1,4,FV ), 0 , 157, 0 , 5108 , 184, 132), // #955
+ INST(Vfnmadd213ps , VexRvm_Lx , V(660F38,AC,_,x,0,0,4,FV ), 0 , 158, 0 , 5121 , 185, 132), // #956
+ INST(Vfnmadd213sd , VexRvm , V(660F38,AD,_,I,1,1,3,T1S), 0 , 159, 0 , 5134 , 186, 133), // #957
+ INST(Vfnmadd213ss , VexRvm , V(660F38,AD,_,I,0,0,2,T1S), 0 , 116, 0 , 5147 , 187, 133), // #958
+ INST(Vfnmadd231pd , VexRvm_Lx , V(660F38,BC,_,x,1,1,4,FV ), 0 , 157, 0 , 5160 , 184, 132), // #959
+ INST(Vfnmadd231ps , VexRvm_Lx , V(660F38,BC,_,x,0,0,4,FV ), 0 , 158, 0 , 5173 , 185, 132), // #960
+ INST(Vfnmadd231sd , VexRvm , V(660F38,BC,_,I,1,1,3,T1S), 0 , 159, 0 , 5186 , 186, 133), // #961
+ INST(Vfnmadd231ss , VexRvm , V(660F38,BC,_,I,0,0,2,T1S), 0 , 116, 0 , 5199 , 187, 133), // #962
+ INST(Vfnmaddpd , Fma4_Lx , V(660F3A,79,_,x,x,_,_,_ ), 0 , 67 , 0 , 5212 , 259, 134), // #963
+ INST(Vfnmaddps , Fma4_Lx , V(660F3A,78,_,x,x,_,_,_ ), 0 , 67 , 0 , 5222 , 259, 134), // #964
+ INST(Vfnmaddsd , Fma4 , V(660F3A,7B,_,0,x,_,_,_ ), 0 , 67 , 0 , 5232 , 260, 134), // #965
+ INST(Vfnmaddss , Fma4 , V(660F3A,7A,_,0,x,_,_,_ ), 0 , 67 , 0 , 5242 , 261, 134), // #966
+ INST(Vfnmsub132pd , VexRvm_Lx , V(660F38,9E,_,x,1,1,4,FV ), 0 , 157, 0 , 5252 , 184, 132), // #967
+ INST(Vfnmsub132ps , VexRvm_Lx , V(660F38,9E,_,x,0,0,4,FV ), 0 , 158, 0 , 5265 , 185, 132), // #968
+ INST(Vfnmsub132sd , VexRvm , V(660F38,9F,_,I,1,1,3,T1S), 0 , 159, 0 , 5278 , 186, 133), // #969
+ INST(Vfnmsub132ss , VexRvm , V(660F38,9F,_,I,0,0,2,T1S), 0 , 116, 0 , 5291 , 187, 133), // #970
+ INST(Vfnmsub213pd , VexRvm_Lx , V(660F38,AE,_,x,1,1,4,FV ), 0 , 157, 0 , 5304 , 184, 132), // #971
+ INST(Vfnmsub213ps , VexRvm_Lx , V(660F38,AE,_,x,0,0,4,FV ), 0 , 158, 0 , 5317 , 185, 132), // #972
+ INST(Vfnmsub213sd , VexRvm , V(660F38,AF,_,I,1,1,3,T1S), 0 , 159, 0 , 5330 , 186, 133), // #973
+ INST(Vfnmsub213ss , VexRvm , V(660F38,AF,_,I,0,0,2,T1S), 0 , 116, 0 , 5343 , 187, 133), // #974
+ INST(Vfnmsub231pd , VexRvm_Lx , V(660F38,BE,_,x,1,1,4,FV ), 0 , 157, 0 , 5356 , 184, 132), // #975
+ INST(Vfnmsub231ps , VexRvm_Lx , V(660F38,BE,_,x,0,0,4,FV ), 0 , 158, 0 , 5369 , 185, 132), // #976
+ INST(Vfnmsub231sd , VexRvm , V(660F38,BF,_,I,1,1,3,T1S), 0 , 159, 0 , 5382 , 186, 133), // #977
+ INST(Vfnmsub231ss , VexRvm , V(660F38,BF,_,I,0,0,2,T1S), 0 , 116, 0 , 5395 , 187, 133), // #978
+ INST(Vfnmsubpd , Fma4_Lx , V(660F3A,7D,_,x,x,_,_,_ ), 0 , 67 , 0 , 5408 , 259, 134), // #979
+ INST(Vfnmsubps , Fma4_Lx , V(660F3A,7C,_,x,x,_,_,_ ), 0 , 67 , 0 , 5418 , 259, 134), // #980
+ INST(Vfnmsubsd , Fma4 , V(660F3A,7F,_,0,x,_,_,_ ), 0 , 67 , 0 , 5428 , 260, 134), // #981
+ INST(Vfnmsubss , Fma4 , V(660F3A,7E,_,0,x,_,_,_ ), 0 , 67 , 0 , 5438 , 261, 134), // #982
+ INST(Vfpclasspd , VexRmi_Lx , E(660F3A,66,_,x,_,1,4,FV ), 0 , 104, 0 , 5448 , 262, 125), // #983
+ INST(Vfpclassps , VexRmi_Lx , E(660F3A,66,_,x,_,0,4,FV ), 0 , 103, 0 , 5459 , 263, 125), // #984
+ INST(Vfpclasssd , VexRmi_Lx , E(660F3A,67,_,I,_,1,3,T1S), 0 , 155, 0 , 5470 , 264, 61 ), // #985
+ INST(Vfpclassss , VexRmi_Lx , E(660F3A,67,_,I,_,0,2,T1S), 0 , 156, 0 , 5481 , 265, 61 ), // #986
+ INST(Vfrczpd , VexRm_Lx , V(XOP_M9,81,_,x,0,_,_,_ ), 0 , 72 , 0 , 5492 , 266, 135), // #987
+ INST(Vfrczps , VexRm_Lx , V(XOP_M9,80,_,x,0,_,_,_ ), 0 , 72 , 0 , 5500 , 266, 135), // #988
+ INST(Vfrczsd , VexRm , V(XOP_M9,83,_,0,0,_,_,_ ), 0 , 72 , 0 , 5508 , 267, 135), // #989
+ INST(Vfrczss , VexRm , V(XOP_M9,82,_,0,0,_,_,_ ), 0 , 72 , 0 , 5516 , 268, 135), // #990
+ INST(Vgatherdpd , VexRmvRm_VM , V(660F38,92,_,x,1,_,_,_ ), V(660F38,92,_,x,_,1,3,T1S), 160, 79 , 5524 , 269, 136), // #991
+ INST(Vgatherdps , VexRmvRm_VM , V(660F38,92,_,x,0,_,_,_ ), V(660F38,92,_,x,_,0,2,T1S), 90 , 80 , 5535 , 270, 136), // #992
+ INST(Vgatherpf0dpd , VexM_VM , E(660F38,C6,1,2,_,1,3,T1S), 0 , 161, 0 , 5546 , 271, 137), // #993
+ INST(Vgatherpf0dps , VexM_VM , E(660F38,C6,1,2,_,0,2,T1S), 0 , 162, 0 , 5560 , 272, 137), // #994
+ INST(Vgatherpf0qpd , VexM_VM , E(660F38,C7,1,2,_,1,3,T1S), 0 , 161, 0 , 5574 , 273, 137), // #995
+ INST(Vgatherpf0qps , VexM_VM , E(660F38,C7,1,2,_,0,2,T1S), 0 , 162, 0 , 5588 , 273, 137), // #996
+ INST(Vgatherpf1dpd , VexM_VM , E(660F38,C6,2,2,_,1,3,T1S), 0 , 163, 0 , 5602 , 271, 137), // #997
+ INST(Vgatherpf1dps , VexM_VM , E(660F38,C6,2,2,_,0,2,T1S), 0 , 164, 0 , 5616 , 272, 137), // #998
+ INST(Vgatherpf1qpd , VexM_VM , E(660F38,C7,2,2,_,1,3,T1S), 0 , 163, 0 , 5630 , 273, 137), // #999
+ INST(Vgatherpf1qps , VexM_VM , E(660F38,C7,2,2,_,0,2,T1S), 0 , 164, 0 , 5644 , 273, 137), // #1000
+ INST(Vgatherqpd , VexRmvRm_VM , V(660F38,93,_,x,1,_,_,_ ), V(660F38,93,_,x,_,1,3,T1S), 160, 81 , 5658 , 274, 136), // #1001
+ INST(Vgatherqps , VexRmvRm_VM , V(660F38,93,_,x,0,_,_,_ ), V(660F38,93,_,x,_,0,2,T1S), 90 , 82 , 5669 , 275, 136), // #1002
+ INST(Vgetexppd , VexRm_Lx , E(660F38,42,_,x,_,1,4,FV ), 0 , 107, 0 , 5680 , 235, 122), // #1003
+ INST(Vgetexpps , VexRm_Lx , E(660F38,42,_,x,_,0,4,FV ), 0 , 106, 0 , 5690 , 239, 122), // #1004
+ INST(Vgetexpsd , VexRvm , E(660F38,43,_,I,_,1,3,T1S), 0 , 119, 0 , 5700 , 276, 63 ), // #1005
+ INST(Vgetexpss , VexRvm , E(660F38,43,_,I,_,0,2,T1S), 0 , 120, 0 , 5710 , 277, 63 ), // #1006
+ INST(Vgetmantpd , VexRmi_Lx , E(660F3A,26,_,x,_,1,4,FV ), 0 , 104, 0 , 5720 , 278, 122), // #1007
+ INST(Vgetmantps , VexRmi_Lx , E(660F3A,26,_,x,_,0,4,FV ), 0 , 103, 0 , 5731 , 279, 122), // #1008
+ INST(Vgetmantsd , VexRvmi , E(660F3A,27,_,I,_,1,3,T1S), 0 , 155, 0 , 5742 , 257, 63 ), // #1009
+ INST(Vgetmantss , VexRvmi , E(660F3A,27,_,I,_,0,2,T1S), 0 , 156, 0 , 5753 , 258, 63 ), // #1010
+ INST(Vgf2p8affineinvqb, VexRvmi_Lx , V(660F3A,CF,_,x,1,1,4,FV ), 0 , 165, 0 , 5764 , 280, 138), // #1011
+ INST(Vgf2p8affineqb , VexRvmi_Lx , V(660F3A,CE,_,x,1,1,4,FV ), 0 , 165, 0 , 5782 , 280, 138), // #1012
+ INST(Vgf2p8mulb , VexRvm_Lx , V(660F38,CF,_,x,0,0,4,FV ), 0 , 158, 0 , 5797 , 281, 138), // #1013
+ INST(Vhaddpd , VexRvm_Lx , V(660F00,7C,_,x,I,_,_,_ ), 0 , 63 , 0 , 5808 , 188, 119), // #1014
+ INST(Vhaddps , VexRvm_Lx , V(F20F00,7C,_,x,I,_,_,_ ), 0 , 101, 0 , 5816 , 188, 119), // #1015
+ INST(Vhsubpd , VexRvm_Lx , V(660F00,7D,_,x,I,_,_,_ ), 0 , 63 , 0 , 5824 , 188, 119), // #1016
+ INST(Vhsubps , VexRvm_Lx , V(F20F00,7D,_,x,I,_,_,_ ), 0 , 101, 0 , 5832 , 188, 119), // #1017
+ INST(Vinsertf128 , VexRvmi , V(660F3A,18,_,1,0,_,_,_ ), 0 , 149, 0 , 5840 , 282, 119), // #1018
+ INST(Vinsertf32x4 , VexRvmi_Lx , E(660F3A,18,_,x,_,0,4,T4 ), 0 , 150, 0 , 5852 , 283, 122), // #1019
+ INST(Vinsertf32x8 , VexRvmi , E(660F3A,1A,_,2,_,0,5,T8 ), 0 , 151, 0 , 5865 , 284, 61 ), // #1020
+ INST(Vinsertf64x2 , VexRvmi_Lx , E(660F3A,18,_,x,_,1,4,T2 ), 0 , 152, 0 , 5878 , 283, 125), // #1021
+ INST(Vinsertf64x4 , VexRvmi , E(660F3A,1A,_,2,_,1,5,T4 ), 0 , 153, 0 , 5891 , 284, 63 ), // #1022
+ INST(Vinserti128 , VexRvmi , V(660F3A,38,_,1,0,_,_,_ ), 0 , 149, 0 , 5904 , 282, 126), // #1023
+ INST(Vinserti32x4 , VexRvmi_Lx , E(660F3A,38,_,x,_,0,4,T4 ), 0 , 150, 0 , 5916 , 283, 122), // #1024
+ INST(Vinserti32x8 , VexRvmi , E(660F3A,3A,_,2,_,0,5,T8 ), 0 , 151, 0 , 5929 , 284, 61 ), // #1025
+ INST(Vinserti64x2 , VexRvmi_Lx , E(660F3A,38,_,x,_,1,4,T2 ), 0 , 152, 0 , 5942 , 283, 125), // #1026
+ INST(Vinserti64x4 , VexRvmi , E(660F3A,3A,_,2,_,1,5,T4 ), 0 , 153, 0 , 5955 , 284, 63 ), // #1027
+ INST(Vinsertps , VexRvmi , V(660F3A,21,_,0,I,0,2,T1S), 0 , 154, 0 , 5968 , 285, 118), // #1028
+ INST(Vlddqu , VexRm_Lx , V(F20F00,F0,_,x,I,_,_,_ ), 0 , 101, 0 , 5978 , 286, 119), // #1029
+ INST(Vldmxcsr , VexM , V(000F00,AE,2,0,I,_,_,_ ), 0 , 166, 0 , 5985 , 287, 119), // #1030
+ INST(Vmaskmovdqu , VexRm_ZDI , V(660F00,F7,_,0,I,_,_,_ ), 0 , 63 , 0 , 5994 , 288, 119), // #1031
+ INST(Vmaskmovpd , VexRvmMvr_Lx , V(660F38,2D,_,x,0,_,_,_ ), V(660F38,2F,_,x,0,_,_,_ ), 90 , 83 , 6006 , 289, 119), // #1032
+ INST(Vmaskmovps , VexRvmMvr_Lx , V(660F38,2C,_,x,0,_,_,_ ), V(660F38,2E,_,x,0,_,_,_ ), 90 , 84 , 6017 , 289, 119), // #1033
+ INST(Vmaxpd , VexRvm_Lx , V(660F00,5F,_,x,I,1,4,FV ), 0 , 97 , 0 , 6028 , 290, 117), // #1034
+ INST(Vmaxps , VexRvm_Lx , V(000F00,5F,_,x,I,0,4,FV ), 0 , 98 , 0 , 6035 , 291, 117), // #1035
+ INST(Vmaxsd , VexRvm , V(F20F00,5F,_,I,I,1,3,T1S), 0 , 99 , 0 , 6042 , 292, 117), // #1036
+ INST(Vmaxss , VexRvm , V(F30F00,5F,_,I,I,0,2,T1S), 0 , 100, 0 , 6049 , 231, 117), // #1037
+ INST(Vmcall , X86Op , O(000F01,C1,_,_,_,_,_,_ ), 0 , 21 , 0 , 6056 , 30 , 53 ), // #1038
+ INST(Vmclear , X86M_Only , O(660F00,C7,6,_,_,_,_,_ ), 0 , 24 , 0 , 6063 , 293, 53 ), // #1039
+ INST(Vmfunc , X86Op , O(000F01,D4,_,_,_,_,_,_ ), 0 , 21 , 0 , 6071 , 30 , 53 ), // #1040
+ INST(Vminpd , VexRvm_Lx , V(660F00,5D,_,x,I,1,4,FV ), 0 , 97 , 0 , 6078 , 290, 117), // #1041
+ INST(Vminps , VexRvm_Lx , V(000F00,5D,_,x,I,0,4,FV ), 0 , 98 , 0 , 6085 , 291, 117), // #1042
+ INST(Vminsd , VexRvm , V(F20F00,5D,_,I,I,1,3,T1S), 0 , 99 , 0 , 6092 , 292, 117), // #1043
+ INST(Vminss , VexRvm , V(F30F00,5D,_,I,I,0,2,T1S), 0 , 100, 0 , 6099 , 231, 117), // #1044
+ INST(Vmlaunch , X86Op , O(000F01,C2,_,_,_,_,_,_ ), 0 , 21 , 0 , 6106 , 30 , 53 ), // #1045
+ INST(Vmload , X86Op_xAX , O(000F01,DA,_,_,_,_,_,_ ), 0 , 21 , 0 , 6115 , 294, 22 ), // #1046
+ INST(Vmmcall , X86Op , O(000F01,D9,_,_,_,_,_,_ ), 0 , 21 , 0 , 6122 , 30 , 22 ), // #1047
+ INST(Vmovapd , VexRmMr_Lx , V(660F00,28,_,x,I,1,4,FVM), V(660F00,29,_,x,I,1,4,FVM), 167, 85 , 6130 , 295, 117), // #1048
+ INST(Vmovaps , VexRmMr_Lx , V(000F00,28,_,x,I,0,4,FVM), V(000F00,29,_,x,I,0,4,FVM), 168, 86 , 6138 , 295, 117), // #1049
+ INST(Vmovd , VexMovdMovq , V(660F00,6E,_,0,0,0,2,T1S), V(660F00,7E,_,0,0,0,2,T1S), 169, 87 , 6146 , 296, 118), // #1050
+ INST(Vmovddup , VexRm_Lx , V(F20F00,12,_,x,I,1,3,DUP), 0 , 170, 0 , 6152 , 297, 117), // #1051
+ INST(Vmovdqa , VexRmMr_Lx , V(660F00,6F,_,x,I,_,_,_ ), V(660F00,7F,_,x,I,_,_,_ ), 63 , 88 , 6161 , 298, 119), // #1052
+ INST(Vmovdqa32 , VexRmMr_Lx , E(660F00,6F,_,x,_,0,4,FVM), E(660F00,7F,_,x,_,0,4,FVM), 171, 89 , 6169 , 299, 122), // #1053
+ INST(Vmovdqa64 , VexRmMr_Lx , E(660F00,6F,_,x,_,1,4,FVM), E(660F00,7F,_,x,_,1,4,FVM), 172, 90 , 6179 , 299, 122), // #1054
+ INST(Vmovdqu , VexRmMr_Lx , V(F30F00,6F,_,x,I,_,_,_ ), V(F30F00,7F,_,x,I,_,_,_ ), 173, 91 , 6189 , 298, 119), // #1055
+ INST(Vmovdqu16 , VexRmMr_Lx , E(F20F00,6F,_,x,_,1,4,FVM), E(F20F00,7F,_,x,_,1,4,FVM), 174, 92 , 6197 , 299, 124), // #1056
+ INST(Vmovdqu32 , VexRmMr_Lx , E(F30F00,6F,_,x,_,0,4,FVM), E(F30F00,7F,_,x,_,0,4,FVM), 175, 93 , 6207 , 299, 122), // #1057
+ INST(Vmovdqu64 , VexRmMr_Lx , E(F30F00,6F,_,x,_,1,4,FVM), E(F30F00,7F,_,x,_,1,4,FVM), 176, 94 , 6217 , 299, 122), // #1058
+ INST(Vmovdqu8 , VexRmMr_Lx , E(F20F00,6F,_,x,_,0,4,FVM), E(F20F00,7F,_,x,_,0,4,FVM), 177, 95 , 6227 , 299, 124), // #1059
+ INST(Vmovhlps , VexRvm , V(000F00,12,_,0,I,0,_,_ ), 0 , 66 , 0 , 6236 , 300, 118), // #1060
+ INST(Vmovhpd , VexRvmMr , V(660F00,16,_,0,I,1,3,T1S), V(660F00,17,_,0,I,1,3,T1S), 117, 96 , 6245 , 301, 118), // #1061
+ INST(Vmovhps , VexRvmMr , V(000F00,16,_,0,I,0,3,T2 ), V(000F00,17,_,0,I,0,3,T2 ), 178, 97 , 6253 , 301, 118), // #1062
+ INST(Vmovlhps , VexRvm , V(000F00,16,_,0,I,0,_,_ ), 0 , 66 , 0 , 6261 , 300, 118), // #1063
+ INST(Vmovlpd , VexRvmMr , V(660F00,12,_,0,I,1,3,T1S), V(660F00,13,_,0,I,1,3,T1S), 117, 98 , 6270 , 301, 118), // #1064
+ INST(Vmovlps , VexRvmMr , V(000F00,12,_,0,I,0,3,T2 ), V(000F00,13,_,0,I,0,3,T2 ), 178, 99 , 6278 , 301, 118), // #1065
+ INST(Vmovmskpd , VexRm_Lx , V(660F00,50,_,x,I,_,_,_ ), 0 , 63 , 0 , 6286 , 302, 119), // #1066
+ INST(Vmovmskps , VexRm_Lx , V(000F00,50,_,x,I,_,_,_ ), 0 , 66 , 0 , 6296 , 302, 119), // #1067
+ INST(Vmovntdq , VexMr_Lx , V(660F00,E7,_,x,I,0,4,FVM), 0 , 179, 0 , 6306 , 303, 117), // #1068
+ INST(Vmovntdqa , VexRm_Lx , V(660F38,2A,_,x,I,0,4,FVM), 0 , 102, 0 , 6315 , 304, 127), // #1069
+ INST(Vmovntpd , VexMr_Lx , V(660F00,2B,_,x,I,1,4,FVM), 0 , 167, 0 , 6325 , 303, 117), // #1070
+ INST(Vmovntps , VexMr_Lx , V(000F00,2B,_,x,I,0,4,FVM), 0 , 168, 0 , 6334 , 303, 117), // #1071
+ INST(Vmovq , VexMovdMovq , V(660F00,6E,_,0,I,1,3,T1S), V(660F00,7E,_,0,I,1,3,T1S), 117, 100, 6343 , 305, 118), // #1072
+ INST(Vmovsd , VexMovssMovsd , V(F20F00,10,_,I,I,1,3,T1S), V(F20F00,11,_,I,I,1,3,T1S), 99 , 101, 6349 , 306, 118), // #1073
+ INST(Vmovshdup , VexRm_Lx , V(F30F00,16,_,x,I,0,4,FVM), 0 , 180, 0 , 6356 , 307, 117), // #1074
+ INST(Vmovsldup , VexRm_Lx , V(F30F00,12,_,x,I,0,4,FVM), 0 , 180, 0 , 6366 , 307, 117), // #1075
+ INST(Vmovss , VexMovssMovsd , V(F30F00,10,_,I,I,0,2,T1S), V(F30F00,11,_,I,I,0,2,T1S), 100, 102, 6376 , 308, 118), // #1076
+ INST(Vmovupd , VexRmMr_Lx , V(660F00,10,_,x,I,1,4,FVM), V(660F00,11,_,x,I,1,4,FVM), 167, 103, 6383 , 295, 117), // #1077
+ INST(Vmovups , VexRmMr_Lx , V(000F00,10,_,x,I,0,4,FVM), V(000F00,11,_,x,I,0,4,FVM), 168, 104, 6391 , 295, 117), // #1078
+ INST(Vmpsadbw , VexRvmi_Lx , V(660F3A,42,_,x,I,_,_,_ ), 0 , 67 , 0 , 6399 , 201, 139), // #1079
+ INST(Vmptrld , X86M_Only , O(000F00,C7,6,_,_,_,_,_ ), 0 , 73 , 0 , 6408 , 293, 53 ), // #1080
+ INST(Vmptrst , X86M_Only , O(000F00,C7,7,_,_,_,_,_ ), 0 , 22 , 0 , 6416 , 293, 53 ), // #1081
+ INST(Vmread , X86Mr_NoSize , O(000F00,78,_,_,_,_,_,_ ), 0 , 4 , 0 , 6424 , 309, 53 ), // #1082
+ INST(Vmresume , X86Op , O(000F01,C3,_,_,_,_,_,_ ), 0 , 21 , 0 , 6431 , 30 , 53 ), // #1083
+ INST(Vmrun , X86Op_xAX , O(000F01,D8,_,_,_,_,_,_ ), 0 , 21 , 0 , 6440 , 294, 22 ), // #1084
+ INST(Vmsave , X86Op_xAX , O(000F01,DB,_,_,_,_,_,_ ), 0 , 21 , 0 , 6446 , 294, 22 ), // #1085
+ INST(Vmulpd , VexRvm_Lx , V(660F00,59,_,x,I,1,4,FV ), 0 , 97 , 0 , 6453 , 184, 117), // #1086
+ INST(Vmulps , VexRvm_Lx , V(000F00,59,_,x,I,0,4,FV ), 0 , 98 , 0 , 6460 , 185, 117), // #1087
+ INST(Vmulsd , VexRvm_Lx , V(F20F00,59,_,I,I,1,3,T1S), 0 , 99 , 0 , 6467 , 186, 118), // #1088
+ INST(Vmulss , VexRvm_Lx , V(F30F00,59,_,I,I,0,2,T1S), 0 , 100, 0 , 6474 , 187, 118), // #1089
+ INST(Vmwrite , X86Rm_NoSize , O(000F00,79,_,_,_,_,_,_ ), 0 , 4 , 0 , 6481 , 310, 53 ), // #1090
+ INST(Vmxon , X86M_Only , O(F30F00,C7,6,_,_,_,_,_ ), 0 , 94 , 0 , 6489 , 293, 53 ), // #1091
+ INST(Vorpd , VexRvm_Lx , V(660F00,56,_,x,I,1,4,FV ), 0 , 97 , 0 , 6495 , 196, 123), // #1092
+ INST(Vorps , VexRvm_Lx , V(000F00,56,_,x,I,0,4,FV ), 0 , 98 , 0 , 6501 , 197, 123), // #1093
+ INST(Vp2intersectd , VexRvm_Lx_2xK , E(F20F38,68,_,_,_,0,4,FV ), 0 , 181, 0 , 6507 , 311, 140), // #1094
+ INST(Vp2intersectq , VexRvm_Lx_2xK , E(F20F38,68,_,_,_,1,4,FV ), 0 , 182, 0 , 6521 , 312, 140), // #1095
+ INST(Vp4dpwssd , VexRm_T1_4X , E(F20F38,52,_,2,_,0,2,T4X), 0 , 96 , 0 , 6535 , 182, 141), // #1096
+ INST(Vp4dpwssds , VexRm_T1_4X , E(F20F38,53,_,2,_,0,2,T4X), 0 , 96 , 0 , 6545 , 182, 141), // #1097
+ INST(Vpabsb , VexRm_Lx , V(660F38,1C,_,x,I,_,4,FVM), 0 , 102, 0 , 6556 , 307, 142), // #1098
+ INST(Vpabsd , VexRm_Lx , V(660F38,1E,_,x,I,0,4,FV ), 0 , 158, 0 , 6563 , 307, 127), // #1099
+ INST(Vpabsq , VexRm_Lx , E(660F38,1F,_,x,_,1,4,FV ), 0 , 107, 0 , 6570 , 250, 122), // #1100
+ INST(Vpabsw , VexRm_Lx , V(660F38,1D,_,x,I,_,4,FVM), 0 , 102, 0 , 6577 , 307, 142), // #1101
+ INST(Vpackssdw , VexRvm_Lx , V(660F00,6B,_,x,I,0,4,FV ), 0 , 128, 0 , 6584 , 195, 142), // #1102
+ INST(Vpacksswb , VexRvm_Lx , V(660F00,63,_,x,I,I,4,FVM), 0 , 179, 0 , 6594 , 281, 142), // #1103
+ INST(Vpackusdw , VexRvm_Lx , V(660F38,2B,_,x,I,0,4,FV ), 0 , 158, 0 , 6604 , 195, 142), // #1104
+ INST(Vpackuswb , VexRvm_Lx , V(660F00,67,_,x,I,I,4,FVM), 0 , 179, 0 , 6614 , 281, 142), // #1105
+ INST(Vpaddb , VexRvm_Lx , V(660F00,FC,_,x,I,I,4,FVM), 0 , 179, 0 , 6624 , 281, 142), // #1106
+ INST(Vpaddd , VexRvm_Lx , V(660F00,FE,_,x,I,0,4,FV ), 0 , 128, 0 , 6631 , 195, 127), // #1107
+ INST(Vpaddq , VexRvm_Lx , V(660F00,D4,_,x,I,1,4,FV ), 0 , 97 , 0 , 6638 , 194, 127), // #1108
+ INST(Vpaddsb , VexRvm_Lx , V(660F00,EC,_,x,I,I,4,FVM), 0 , 179, 0 , 6645 , 281, 142), // #1109
+ INST(Vpaddsw , VexRvm_Lx , V(660F00,ED,_,x,I,I,4,FVM), 0 , 179, 0 , 6653 , 281, 142), // #1110
+ INST(Vpaddusb , VexRvm_Lx , V(660F00,DC,_,x,I,I,4,FVM), 0 , 179, 0 , 6661 , 281, 142), // #1111
+ INST(Vpaddusw , VexRvm_Lx , V(660F00,DD,_,x,I,I,4,FVM), 0 , 179, 0 , 6670 , 281, 142), // #1112
+ INST(Vpaddw , VexRvm_Lx , V(660F00,FD,_,x,I,I,4,FVM), 0 , 179, 0 , 6679 , 281, 142), // #1113
+ INST(Vpalignr , VexRvmi_Lx , V(660F3A,0F,_,x,I,I,4,FVM), 0 , 183, 0 , 6686 , 280, 142), // #1114
+ INST(Vpand , VexRvm_Lx , V(660F00,DB,_,x,I,_,_,_ ), 0 , 63 , 0 , 6695 , 313, 139), // #1115
+ INST(Vpandd , VexRvm_Lx , E(660F00,DB,_,x,_,0,4,FV ), 0 , 184, 0 , 6701 , 314, 122), // #1116
+ INST(Vpandn , VexRvm_Lx , V(660F00,DF,_,x,I,_,_,_ ), 0 , 63 , 0 , 6708 , 315, 139), // #1117
+ INST(Vpandnd , VexRvm_Lx , E(660F00,DF,_,x,_,0,4,FV ), 0 , 184, 0 , 6715 , 316, 122), // #1118
+ INST(Vpandnq , VexRvm_Lx , E(660F00,DF,_,x,_,1,4,FV ), 0 , 125, 0 , 6723 , 317, 122), // #1119
+ INST(Vpandq , VexRvm_Lx , E(660F00,DB,_,x,_,1,4,FV ), 0 , 125, 0 , 6731 , 318, 122), // #1120
+ INST(Vpavgb , VexRvm_Lx , V(660F00,E0,_,x,I,I,4,FVM), 0 , 179, 0 , 6738 , 281, 142), // #1121
+ INST(Vpavgw , VexRvm_Lx , V(660F00,E3,_,x,I,I,4,FVM), 0 , 179, 0 , 6745 , 281, 142), // #1122
+ INST(Vpblendd , VexRvmi_Lx , V(660F3A,02,_,x,0,_,_,_ ), 0 , 67 , 0 , 6752 , 201, 126), // #1123
+ INST(Vpblendvb , VexRvmr , V(660F3A,4C,_,x,0,_,_,_ ), 0 , 67 , 0 , 6761 , 202, 139), // #1124
+ INST(Vpblendw , VexRvmi_Lx , V(660F3A,0E,_,x,I,_,_,_ ), 0 , 67 , 0 , 6771 , 201, 139), // #1125
+ INST(Vpbroadcastb , VexRm_Lx_Bcst , V(660F38,78,_,x,0,0,0,T1S), E(660F38,7A,_,x,0,0,0,T1S), 185, 105, 6780 , 319, 143), // #1126
+ INST(Vpbroadcastd , VexRm_Lx_Bcst , V(660F38,58,_,x,0,0,2,T1S), E(660F38,7C,_,x,0,0,0,T1S), 116, 106, 6793 , 320, 136), // #1127
+ INST(Vpbroadcastmb2d , VexRm_Lx , E(F30F38,3A,_,x,_,0,_,_ ), 0 , 123, 0 , 6806 , 321, 144), // #1128
+ INST(Vpbroadcastmb2q , VexRm_Lx , E(F30F38,2A,_,x,_,1,_,_ ), 0 , 186, 0 , 6822 , 321, 144), // #1129
+ INST(Vpbroadcastq , VexRm_Lx_Bcst , V(660F38,59,_,x,0,1,3,T1S), E(660F38,7C,_,x,0,1,0,T1S), 115, 107, 6838 , 322, 136), // #1130
+ INST(Vpbroadcastw , VexRm_Lx_Bcst , V(660F38,79,_,x,0,0,1,T1S), E(660F38,7B,_,x,0,0,0,T1S), 187, 108, 6851 , 323, 143), // #1131
+ INST(Vpclmulqdq , VexRvmi_Lx , V(660F3A,44,_,x,I,_,4,FVM), 0 , 183, 0 , 6864 , 324, 145), // #1132
+ INST(Vpcmov , VexRvrmRvmr_Lx , V(XOP_M8,A2,_,x,x,_,_,_ ), 0 , 188, 0 , 6875 , 259, 135), // #1133
+ INST(Vpcmpb , VexRvmi_Lx , E(660F3A,3F,_,x,_,0,4,FVM), 0 , 146, 0 , 6882 , 325, 124), // #1134
+ INST(Vpcmpd , VexRvmi_Lx , E(660F3A,1F,_,x,_,0,4,FV ), 0 , 103, 0 , 6889 , 326, 122), // #1135
+ INST(Vpcmpeqb , VexRvm_Lx , V(660F00,74,_,x,I,I,4,FV ), 0 , 128, 0 , 6896 , 327, 142), // #1136
+ INST(Vpcmpeqd , VexRvm_Lx , V(660F00,76,_,x,I,0,4,FVM), 0 , 179, 0 , 6905 , 328, 127), // #1137
+ INST(Vpcmpeqq , VexRvm_Lx , V(660F38,29,_,x,I,1,4,FVM), 0 , 189, 0 , 6914 , 329, 127), // #1138
+ INST(Vpcmpeqw , VexRvm_Lx , V(660F00,75,_,x,I,I,4,FV ), 0 , 128, 0 , 6923 , 327, 142), // #1139
+ INST(Vpcmpestri , VexRmi , V(660F3A,61,_,0,I,_,_,_ ), 0 , 67 , 0 , 6932 , 330, 146), // #1140
+ INST(Vpcmpestrm , VexRmi , V(660F3A,60,_,0,I,_,_,_ ), 0 , 67 , 0 , 6943 , 331, 146), // #1141
+ INST(Vpcmpgtb , VexRvm_Lx , V(660F00,64,_,x,I,I,4,FV ), 0 , 128, 0 , 6954 , 327, 142), // #1142
+ INST(Vpcmpgtd , VexRvm_Lx , V(660F00,66,_,x,I,0,4,FVM), 0 , 179, 0 , 6963 , 328, 127), // #1143
+ INST(Vpcmpgtq , VexRvm_Lx , V(660F38,37,_,x,I,1,4,FVM), 0 , 189, 0 , 6972 , 329, 127), // #1144
+ INST(Vpcmpgtw , VexRvm_Lx , V(660F00,65,_,x,I,I,4,FV ), 0 , 128, 0 , 6981 , 327, 142), // #1145
+ INST(Vpcmpistri , VexRmi , V(660F3A,63,_,0,I,_,_,_ ), 0 , 67 , 0 , 6990 , 332, 146), // #1146
+ INST(Vpcmpistrm , VexRmi , V(660F3A,62,_,0,I,_,_,_ ), 0 , 67 , 0 , 7001 , 333, 146), // #1147
+ INST(Vpcmpq , VexRvmi_Lx , E(660F3A,1F,_,x,_,1,4,FV ), 0 , 104, 0 , 7012 , 334, 122), // #1148
+ INST(Vpcmpub , VexRvmi_Lx , E(660F3A,3E,_,x,_,0,4,FVM), 0 , 146, 0 , 7019 , 325, 124), // #1149
+ INST(Vpcmpud , VexRvmi_Lx , E(660F3A,1E,_,x,_,0,4,FV ), 0 , 103, 0 , 7027 , 326, 122), // #1150
+ INST(Vpcmpuq , VexRvmi_Lx , E(660F3A,1E,_,x,_,1,4,FV ), 0 , 104, 0 , 7035 , 334, 122), // #1151
+ INST(Vpcmpuw , VexRvmi_Lx , E(660F3A,3E,_,x,_,1,4,FVM), 0 , 190, 0 , 7043 , 334, 124), // #1152
+ INST(Vpcmpw , VexRvmi_Lx , E(660F3A,3F,_,x,_,1,4,FVM), 0 , 190, 0 , 7051 , 334, 124), // #1153
+ INST(Vpcomb , VexRvmi , V(XOP_M8,CC,_,0,0,_,_,_ ), 0 , 188, 0 , 7058 , 247, 135), // #1154
+ INST(Vpcomd , VexRvmi , V(XOP_M8,CE,_,0,0,_,_,_ ), 0 , 188, 0 , 7065 , 247, 135), // #1155
+ INST(Vpcompressb , VexMr_Lx , E(660F38,63,_,x,_,0,0,T1S), 0 , 191, 0 , 7072 , 216, 147), // #1156
+ INST(Vpcompressd , VexMr_Lx , E(660F38,8B,_,x,_,0,2,T1S), 0 , 120, 0 , 7084 , 216, 122), // #1157
+ INST(Vpcompressq , VexMr_Lx , E(660F38,8B,_,x,_,1,3,T1S), 0 , 119, 0 , 7096 , 216, 122), // #1158
+ INST(Vpcompressw , VexMr_Lx , E(660F38,63,_,x,_,1,1,T1S), 0 , 192, 0 , 7108 , 216, 147), // #1159
+ INST(Vpcomq , VexRvmi , V(XOP_M8,CF,_,0,0,_,_,_ ), 0 , 188, 0 , 7120 , 247, 135), // #1160
+ INST(Vpcomub , VexRvmi , V(XOP_M8,EC,_,0,0,_,_,_ ), 0 , 188, 0 , 7127 , 247, 135), // #1161
+ INST(Vpcomud , VexRvmi , V(XOP_M8,EE,_,0,0,_,_,_ ), 0 , 188, 0 , 7135 , 247, 135), // #1162
+ INST(Vpcomuq , VexRvmi , V(XOP_M8,EF,_,0,0,_,_,_ ), 0 , 188, 0 , 7143 , 247, 135), // #1163
+ INST(Vpcomuw , VexRvmi , V(XOP_M8,ED,_,0,0,_,_,_ ), 0 , 188, 0 , 7151 , 247, 135), // #1164
+ INST(Vpcomw , VexRvmi , V(XOP_M8,CD,_,0,0,_,_,_ ), 0 , 188, 0 , 7159 , 247, 135), // #1165
+ INST(Vpconflictd , VexRm_Lx , E(660F38,C4,_,x,_,0,4,FV ), 0 , 106, 0 , 7166 , 335, 144), // #1166
+ INST(Vpconflictq , VexRm_Lx , E(660F38,C4,_,x,_,1,4,FV ), 0 , 107, 0 , 7178 , 335, 144), // #1167
+ INST(Vpdpbusd , VexRvm_Lx , E(660F38,50,_,x,_,0,4,FV ), 0 , 106, 0 , 7190 , 199, 148), // #1168
+ INST(Vpdpbusds , VexRvm_Lx , E(660F38,51,_,x,_,0,4,FV ), 0 , 106, 0 , 7199 , 199, 148), // #1169
+ INST(Vpdpwssd , VexRvm_Lx , E(660F38,52,_,x,_,0,4,FV ), 0 , 106, 0 , 7209 , 199, 148), // #1170
+ INST(Vpdpwssds , VexRvm_Lx , E(660F38,53,_,x,_,0,4,FV ), 0 , 106, 0 , 7218 , 199, 148), // #1171
+ INST(Vperm2f128 , VexRvmi , V(660F3A,06,_,1,0,_,_,_ ), 0 , 149, 0 , 7228 , 336, 119), // #1172
+ INST(Vperm2i128 , VexRvmi , V(660F3A,46,_,1,0,_,_,_ ), 0 , 149, 0 , 7239 , 336, 126), // #1173
+ INST(Vpermb , VexRvm_Lx , E(660F38,8D,_,x,_,0,4,FVM), 0 , 105, 0 , 7250 , 198, 149), // #1174
+ INST(Vpermd , VexRvm_Lx , V(660F38,36,_,x,0,0,4,FV ), 0 , 158, 0 , 7257 , 337, 136), // #1175
+ INST(Vpermi2b , VexRvm_Lx , E(660F38,75,_,x,_,0,4,FVM), 0 , 105, 0 , 7264 , 198, 149), // #1176
+ INST(Vpermi2d , VexRvm_Lx , E(660F38,76,_,x,_,0,4,FV ), 0 , 106, 0 , 7273 , 199, 122), // #1177
+ INST(Vpermi2pd , VexRvm_Lx , E(660F38,77,_,x,_,1,4,FV ), 0 , 107, 0 , 7282 , 200, 122), // #1178
+ INST(Vpermi2ps , VexRvm_Lx , E(660F38,77,_,x,_,0,4,FV ), 0 , 106, 0 , 7292 , 199, 122), // #1179
+ INST(Vpermi2q , VexRvm_Lx , E(660F38,76,_,x,_,1,4,FV ), 0 , 107, 0 , 7302 , 200, 122), // #1180
+ INST(Vpermi2w , VexRvm_Lx , E(660F38,75,_,x,_,1,4,FVM), 0 , 108, 0 , 7311 , 198, 124), // #1181
+ INST(Vpermil2pd , VexRvrmiRvmri_Lx , V(660F3A,49,_,x,x,_,_,_ ), 0 , 67 , 0 , 7320 , 338, 135), // #1182
+ INST(Vpermil2ps , VexRvrmiRvmri_Lx , V(660F3A,48,_,x,x,_,_,_ ), 0 , 67 , 0 , 7331 , 338, 135), // #1183
+ INST(Vpermilpd , VexRvmRmi_Lx , V(660F38,0D,_,x,0,1,4,FV ), V(660F3A,05,_,x,0,1,4,FV ), 193, 109, 7342 , 339, 117), // #1184
+ INST(Vpermilps , VexRvmRmi_Lx , V(660F38,0C,_,x,0,0,4,FV ), V(660F3A,04,_,x,0,0,4,FV ), 158, 110, 7352 , 339, 117), // #1185
+ INST(Vpermpd , VexRvmRmi_Lx , E(660F38,16,_,x,1,1,4,FV ), V(660F3A,01,_,x,1,1,4,FV ), 194, 111, 7362 , 340, 136), // #1186
+ INST(Vpermps , VexRvm_Lx , V(660F38,16,_,x,0,0,4,FV ), 0 , 158, 0 , 7370 , 337, 136), // #1187
+ INST(Vpermq , VexRvmRmi_Lx , V(660F38,36,_,x,_,1,4,FV ), V(660F3A,00,_,x,1,1,4,FV ), 193, 112, 7378 , 340, 136), // #1188
+ INST(Vpermt2b , VexRvm_Lx , E(660F38,7D,_,x,_,0,4,FVM), 0 , 105, 0 , 7385 , 198, 149), // #1189
+ INST(Vpermt2d , VexRvm_Lx , E(660F38,7E,_,x,_,0,4,FV ), 0 , 106, 0 , 7394 , 199, 122), // #1190
+ INST(Vpermt2pd , VexRvm_Lx , E(660F38,7F,_,x,_,1,4,FV ), 0 , 107, 0 , 7403 , 200, 122), // #1191
+ INST(Vpermt2ps , VexRvm_Lx , E(660F38,7F,_,x,_,0,4,FV ), 0 , 106, 0 , 7413 , 199, 122), // #1192
+ INST(Vpermt2q , VexRvm_Lx , E(660F38,7E,_,x,_,1,4,FV ), 0 , 107, 0 , 7423 , 200, 122), // #1193
+ INST(Vpermt2w , VexRvm_Lx , E(660F38,7D,_,x,_,1,4,FVM), 0 , 108, 0 , 7432 , 198, 124), // #1194
+ INST(Vpermw , VexRvm_Lx , E(660F38,8D,_,x,_,1,4,FVM), 0 , 108, 0 , 7441 , 198, 124), // #1195
+ INST(Vpexpandb , VexRm_Lx , E(660F38,62,_,x,_,0,0,T1S), 0 , 191, 0 , 7448 , 250, 147), // #1196
+ INST(Vpexpandd , VexRm_Lx , E(660F38,89,_,x,_,0,2,T1S), 0 , 120, 0 , 7458 , 250, 122), // #1197
+ INST(Vpexpandq , VexRm_Lx , E(660F38,89,_,x,_,1,3,T1S), 0 , 119, 0 , 7468 , 250, 122), // #1198
+ INST(Vpexpandw , VexRm_Lx , E(660F38,62,_,x,_,1,1,T1S), 0 , 192, 0 , 7478 , 250, 147), // #1199
+ INST(Vpextrb , VexMri , V(660F3A,14,_,0,0,I,0,T1S), 0 , 195, 0 , 7488 , 341, 150), // #1200
+ INST(Vpextrd , VexMri , V(660F3A,16,_,0,0,0,2,T1S), 0 , 154, 0 , 7496 , 254, 151), // #1201
+ INST(Vpextrq , VexMri , V(660F3A,16,_,0,1,1,3,T1S), 0 , 196, 0 , 7504 , 342, 151), // #1202
+ INST(Vpextrw , VexMri , V(660F3A,15,_,0,0,I,1,T1S), 0 , 197, 0 , 7512 , 343, 150), // #1203
+ INST(Vpgatherdd , VexRmvRm_VM , V(660F38,90,_,x,0,_,_,_ ), V(660F38,90,_,x,_,0,2,T1S), 90 , 113, 7520 , 270, 136), // #1204
+ INST(Vpgatherdq , VexRmvRm_VM , V(660F38,90,_,x,1,_,_,_ ), V(660F38,90,_,x,_,1,3,T1S), 160, 114, 7531 , 269, 136), // #1205
+ INST(Vpgatherqd , VexRmvRm_VM , V(660F38,91,_,x,0,_,_,_ ), V(660F38,91,_,x,_,0,2,T1S), 90 , 115, 7542 , 275, 136), // #1206
+ INST(Vpgatherqq , VexRmvRm_VM , V(660F38,91,_,x,1,_,_,_ ), V(660F38,91,_,x,_,1,3,T1S), 160, 116, 7553 , 274, 136), // #1207
+ INST(Vphaddbd , VexRm , V(XOP_M9,C2,_,0,0,_,_,_ ), 0 , 72 , 0 , 7564 , 190, 135), // #1208
+ INST(Vphaddbq , VexRm , V(XOP_M9,C3,_,0,0,_,_,_ ), 0 , 72 , 0 , 7573 , 190, 135), // #1209
+ INST(Vphaddbw , VexRm , V(XOP_M9,C1,_,0,0,_,_,_ ), 0 , 72 , 0 , 7582 , 190, 135), // #1210
+ INST(Vphaddd , VexRvm_Lx , V(660F38,02,_,x,I,_,_,_ ), 0 , 90 , 0 , 7591 , 188, 139), // #1211
+ INST(Vphadddq , VexRm , V(XOP_M9,CB,_,0,0,_,_,_ ), 0 , 72 , 0 , 7599 , 190, 135), // #1212
+ INST(Vphaddsw , VexRvm_Lx , V(660F38,03,_,x,I,_,_,_ ), 0 , 90 , 0 , 7608 , 188, 139), // #1213
+ INST(Vphaddubd , VexRm , V(XOP_M9,D2,_,0,0,_,_,_ ), 0 , 72 , 0 , 7617 , 190, 135), // #1214
+ INST(Vphaddubq , VexRm , V(XOP_M9,D3,_,0,0,_,_,_ ), 0 , 72 , 0 , 7627 , 190, 135), // #1215
+ INST(Vphaddubw , VexRm , V(XOP_M9,D1,_,0,0,_,_,_ ), 0 , 72 , 0 , 7637 , 190, 135), // #1216
+ INST(Vphaddudq , VexRm , V(XOP_M9,DB,_,0,0,_,_,_ ), 0 , 72 , 0 , 7647 , 190, 135), // #1217
+ INST(Vphadduwd , VexRm , V(XOP_M9,D6,_,0,0,_,_,_ ), 0 , 72 , 0 , 7657 , 190, 135), // #1218
+ INST(Vphadduwq , VexRm , V(XOP_M9,D7,_,0,0,_,_,_ ), 0 , 72 , 0 , 7667 , 190, 135), // #1219
+ INST(Vphaddw , VexRvm_Lx , V(660F38,01,_,x,I,_,_,_ ), 0 , 90 , 0 , 7677 , 188, 139), // #1220
+ INST(Vphaddwd , VexRm , V(XOP_M9,C6,_,0,0,_,_,_ ), 0 , 72 , 0 , 7685 , 190, 135), // #1221
+ INST(Vphaddwq , VexRm , V(XOP_M9,C7,_,0,0,_,_,_ ), 0 , 72 , 0 , 7694 , 190, 135), // #1222
+ INST(Vphminposuw , VexRm , V(660F38,41,_,0,I,_,_,_ ), 0 , 90 , 0 , 7703 , 190, 119), // #1223
+ INST(Vphsubbw , VexRm , V(XOP_M9,E1,_,0,0,_,_,_ ), 0 , 72 , 0 , 7715 , 190, 135), // #1224
+ INST(Vphsubd , VexRvm_Lx , V(660F38,06,_,x,I,_,_,_ ), 0 , 90 , 0 , 7724 , 188, 139), // #1225
+ INST(Vphsubdq , VexRm , V(XOP_M9,E3,_,0,0,_,_,_ ), 0 , 72 , 0 , 7732 , 190, 135), // #1226
+ INST(Vphsubsw , VexRvm_Lx , V(660F38,07,_,x,I,_,_,_ ), 0 , 90 , 0 , 7741 , 188, 139), // #1227
+ INST(Vphsubw , VexRvm_Lx , V(660F38,05,_,x,I,_,_,_ ), 0 , 90 , 0 , 7750 , 188, 139), // #1228
+ INST(Vphsubwd , VexRm , V(XOP_M9,E2,_,0,0,_,_,_ ), 0 , 72 , 0 , 7758 , 190, 135), // #1229
+ INST(Vpinsrb , VexRvmi , V(660F3A,20,_,0,0,I,0,T1S), 0 , 195, 0 , 7767 , 344, 150), // #1230
+ INST(Vpinsrd , VexRvmi , V(660F3A,22,_,0,0,0,2,T1S), 0 , 154, 0 , 7775 , 345, 151), // #1231
+ INST(Vpinsrq , VexRvmi , V(660F3A,22,_,0,1,1,3,T1S), 0 , 196, 0 , 7783 , 346, 151), // #1232
+ INST(Vpinsrw , VexRvmi , V(660F00,C4,_,0,0,I,1,T1S), 0 , 198, 0 , 7791 , 347, 150), // #1233
+ INST(Vplzcntd , VexRm_Lx , E(660F38,44,_,x,_,0,4,FV ), 0 , 106, 0 , 7799 , 335, 144), // #1234
+ INST(Vplzcntq , VexRm_Lx , E(660F38,44,_,x,_,1,4,FV ), 0 , 107, 0 , 7808 , 348, 144), // #1235
+ INST(Vpmacsdd , VexRvmr , V(XOP_M8,9E,_,0,0,_,_,_ ), 0 , 188, 0 , 7817 , 349, 135), // #1236
+ INST(Vpmacsdqh , VexRvmr , V(XOP_M8,9F,_,0,0,_,_,_ ), 0 , 188, 0 , 7826 , 349, 135), // #1237
+ INST(Vpmacsdql , VexRvmr , V(XOP_M8,97,_,0,0,_,_,_ ), 0 , 188, 0 , 7836 , 349, 135), // #1238
+ INST(Vpmacssdd , VexRvmr , V(XOP_M8,8E,_,0,0,_,_,_ ), 0 , 188, 0 , 7846 , 349, 135), // #1239
+ INST(Vpmacssdqh , VexRvmr , V(XOP_M8,8F,_,0,0,_,_,_ ), 0 , 188, 0 , 7856 , 349, 135), // #1240
+ INST(Vpmacssdql , VexRvmr , V(XOP_M8,87,_,0,0,_,_,_ ), 0 , 188, 0 , 7867 , 349, 135), // #1241
+ INST(Vpmacsswd , VexRvmr , V(XOP_M8,86,_,0,0,_,_,_ ), 0 , 188, 0 , 7878 , 349, 135), // #1242
+ INST(Vpmacssww , VexRvmr , V(XOP_M8,85,_,0,0,_,_,_ ), 0 , 188, 0 , 7888 , 349, 135), // #1243
+ INST(Vpmacswd , VexRvmr , V(XOP_M8,96,_,0,0,_,_,_ ), 0 , 188, 0 , 7898 , 349, 135), // #1244
+ INST(Vpmacsww , VexRvmr , V(XOP_M8,95,_,0,0,_,_,_ ), 0 , 188, 0 , 7907 , 349, 135), // #1245
+ INST(Vpmadcsswd , VexRvmr , V(XOP_M8,A6,_,0,0,_,_,_ ), 0 , 188, 0 , 7916 , 349, 135), // #1246
+ INST(Vpmadcswd , VexRvmr , V(XOP_M8,B6,_,0,0,_,_,_ ), 0 , 188, 0 , 7927 , 349, 135), // #1247
+ INST(Vpmadd52huq , VexRvm_Lx , E(660F38,B5,_,x,_,1,4,FV ), 0 , 107, 0 , 7937 , 200, 152), // #1248
+ INST(Vpmadd52luq , VexRvm_Lx , E(660F38,B4,_,x,_,1,4,FV ), 0 , 107, 0 , 7949 , 200, 152), // #1249
+ INST(Vpmaddubsw , VexRvm_Lx , V(660F38,04,_,x,I,I,4,FVM), 0 , 102, 0 , 7961 , 281, 142), // #1250
+ INST(Vpmaddwd , VexRvm_Lx , V(660F00,F5,_,x,I,I,4,FVM), 0 , 179, 0 , 7972 , 281, 142), // #1251
+ INST(Vpmaskmovd , VexRvmMvr_Lx , V(660F38,8C,_,x,0,_,_,_ ), V(660F38,8E,_,x,0,_,_,_ ), 90 , 117, 7981 , 289, 126), // #1252
+ INST(Vpmaskmovq , VexRvmMvr_Lx , V(660F38,8C,_,x,1,_,_,_ ), V(660F38,8E,_,x,1,_,_,_ ), 160, 118, 7992 , 289, 126), // #1253
+ INST(Vpmaxsb , VexRvm_Lx , V(660F38,3C,_,x,I,I,4,FVM), 0 , 102, 0 , 8003 , 350, 142), // #1254
+ INST(Vpmaxsd , VexRvm_Lx , V(660F38,3D,_,x,I,0,4,FV ), 0 , 158, 0 , 8011 , 197, 127), // #1255
+ INST(Vpmaxsq , VexRvm_Lx , E(660F38,3D,_,x,_,1,4,FV ), 0 , 107, 0 , 8019 , 200, 122), // #1256
+ INST(Vpmaxsw , VexRvm_Lx , V(660F00,EE,_,x,I,I,4,FVM), 0 , 179, 0 , 8027 , 350, 142), // #1257
+ INST(Vpmaxub , VexRvm_Lx , V(660F00,DE,_,x,I,I,4,FVM), 0 , 179, 0 , 8035 , 350, 142), // #1258
+ INST(Vpmaxud , VexRvm_Lx , V(660F38,3F,_,x,I,0,4,FV ), 0 , 158, 0 , 8043 , 197, 127), // #1259
+ INST(Vpmaxuq , VexRvm_Lx , E(660F38,3F,_,x,_,1,4,FV ), 0 , 107, 0 , 8051 , 200, 122), // #1260
+ INST(Vpmaxuw , VexRvm_Lx , V(660F38,3E,_,x,I,I,4,FVM), 0 , 102, 0 , 8059 , 350, 142), // #1261
+ INST(Vpminsb , VexRvm_Lx , V(660F38,38,_,x,I,I,4,FVM), 0 , 102, 0 , 8067 , 350, 142), // #1262
+ INST(Vpminsd , VexRvm_Lx , V(660F38,39,_,x,I,0,4,FV ), 0 , 158, 0 , 8075 , 197, 127), // #1263
+ INST(Vpminsq , VexRvm_Lx , E(660F38,39,_,x,_,1,4,FV ), 0 , 107, 0 , 8083 , 200, 122), // #1264
+ INST(Vpminsw , VexRvm_Lx , V(660F00,EA,_,x,I,I,4,FVM), 0 , 179, 0 , 8091 , 350, 142), // #1265
+ INST(Vpminub , VexRvm_Lx , V(660F00,DA,_,x,I,_,4,FVM), 0 , 179, 0 , 8099 , 350, 142), // #1266
+ INST(Vpminud , VexRvm_Lx , V(660F38,3B,_,x,I,0,4,FV ), 0 , 158, 0 , 8107 , 197, 127), // #1267
+ INST(Vpminuq , VexRvm_Lx , E(660F38,3B,_,x,_,1,4,FV ), 0 , 107, 0 , 8115 , 200, 122), // #1268
+ INST(Vpminuw , VexRvm_Lx , V(660F38,3A,_,x,I,_,4,FVM), 0 , 102, 0 , 8123 , 350, 142), // #1269
+ INST(Vpmovb2m , VexRm_Lx , E(F30F38,29,_,x,_,0,_,_ ), 0 , 123, 0 , 8131 , 351, 124), // #1270
+ INST(Vpmovd2m , VexRm_Lx , E(F30F38,39,_,x,_,0,_,_ ), 0 , 123, 0 , 8140 , 351, 125), // #1271
+ INST(Vpmovdb , VexMr_Lx , E(F30F38,31,_,x,_,0,2,QVM), 0 , 199, 0 , 8149 , 352, 122), // #1272
+ INST(Vpmovdw , VexMr_Lx , E(F30F38,33,_,x,_,0,3,HVM), 0 , 200, 0 , 8157 , 353, 122), // #1273
+ INST(Vpmovm2b , VexRm_Lx , E(F30F38,28,_,x,_,0,_,_ ), 0 , 123, 0 , 8165 , 321, 124), // #1274
+ INST(Vpmovm2d , VexRm_Lx , E(F30F38,38,_,x,_,0,_,_ ), 0 , 123, 0 , 8174 , 321, 125), // #1275
+ INST(Vpmovm2q , VexRm_Lx , E(F30F38,38,_,x,_,1,_,_ ), 0 , 186, 0 , 8183 , 321, 125), // #1276
+ INST(Vpmovm2w , VexRm_Lx , E(F30F38,28,_,x,_,1,_,_ ), 0 , 186, 0 , 8192 , 321, 124), // #1277
+ INST(Vpmovmskb , VexRm_Lx , V(660F00,D7,_,x,I,_,_,_ ), 0 , 63 , 0 , 8201 , 302, 139), // #1278
+ INST(Vpmovq2m , VexRm_Lx , E(F30F38,39,_,x,_,1,_,_ ), 0 , 186, 0 , 8211 , 351, 125), // #1279
+ INST(Vpmovqb , VexMr_Lx , E(F30F38,32,_,x,_,0,1,OVM), 0 , 201, 0 , 8220 , 354, 122), // #1280
+ INST(Vpmovqd , VexMr_Lx , E(F30F38,35,_,x,_,0,3,HVM), 0 , 200, 0 , 8228 , 353, 122), // #1281
+ INST(Vpmovqw , VexMr_Lx , E(F30F38,34,_,x,_,0,2,QVM), 0 , 199, 0 , 8236 , 352, 122), // #1282
+ INST(Vpmovsdb , VexMr_Lx , E(F30F38,21,_,x,_,0,2,QVM), 0 , 199, 0 , 8244 , 352, 122), // #1283
+ INST(Vpmovsdw , VexMr_Lx , E(F30F38,23,_,x,_,0,3,HVM), 0 , 200, 0 , 8253 , 353, 122), // #1284
+ INST(Vpmovsqb , VexMr_Lx , E(F30F38,22,_,x,_,0,1,OVM), 0 , 201, 0 , 8262 , 354, 122), // #1285
+ INST(Vpmovsqd , VexMr_Lx , E(F30F38,25,_,x,_,0,3,HVM), 0 , 200, 0 , 8271 , 353, 122), // #1286
+ INST(Vpmovsqw , VexMr_Lx , E(F30F38,24,_,x,_,0,2,QVM), 0 , 199, 0 , 8280 , 352, 122), // #1287
+ INST(Vpmovswb , VexMr_Lx , E(F30F38,20,_,x,_,0,3,HVM), 0 , 200, 0 , 8289 , 353, 124), // #1288
+ INST(Vpmovsxbd , VexRm_Lx , V(660F38,21,_,x,I,I,2,QVM), 0 , 202, 0 , 8298 , 355, 127), // #1289
+ INST(Vpmovsxbq , VexRm_Lx , V(660F38,22,_,x,I,I,1,OVM), 0 , 203, 0 , 8308 , 356, 127), // #1290
+ INST(Vpmovsxbw , VexRm_Lx , V(660F38,20,_,x,I,I,3,HVM), 0 , 127, 0 , 8318 , 357, 142), // #1291
+ INST(Vpmovsxdq , VexRm_Lx , V(660F38,25,_,x,I,0,3,HVM), 0 , 127, 0 , 8328 , 357, 127), // #1292
+ INST(Vpmovsxwd , VexRm_Lx , V(660F38,23,_,x,I,I,3,HVM), 0 , 127, 0 , 8338 , 357, 127), // #1293
+ INST(Vpmovsxwq , VexRm_Lx , V(660F38,24,_,x,I,I,2,QVM), 0 , 202, 0 , 8348 , 355, 127), // #1294
+ INST(Vpmovusdb , VexMr_Lx , E(F30F38,11,_,x,_,0,2,QVM), 0 , 199, 0 , 8358 , 352, 122), // #1295
+ INST(Vpmovusdw , VexMr_Lx , E(F30F38,13,_,x,_,0,3,HVM), 0 , 200, 0 , 8368 , 353, 122), // #1296
+ INST(Vpmovusqb , VexMr_Lx , E(F30F38,12,_,x,_,0,1,OVM), 0 , 201, 0 , 8378 , 354, 122), // #1297
+ INST(Vpmovusqd , VexMr_Lx , E(F30F38,15,_,x,_,0,3,HVM), 0 , 200, 0 , 8388 , 353, 122), // #1298
+ INST(Vpmovusqw , VexMr_Lx , E(F30F38,14,_,x,_,0,2,QVM), 0 , 199, 0 , 8398 , 352, 122), // #1299
+ INST(Vpmovuswb , VexMr_Lx , E(F30F38,10,_,x,_,0,3,HVM), 0 , 200, 0 , 8408 , 353, 124), // #1300
+ INST(Vpmovw2m , VexRm_Lx , E(F30F38,29,_,x,_,1,_,_ ), 0 , 186, 0 , 8418 , 351, 124), // #1301
+ INST(Vpmovwb , VexMr_Lx , E(F30F38,30,_,x,_,0,3,HVM), 0 , 200, 0 , 8427 , 353, 124), // #1302
+ INST(Vpmovzxbd , VexRm_Lx , V(660F38,31,_,x,I,I,2,QVM), 0 , 202, 0 , 8435 , 355, 127), // #1303
+ INST(Vpmovzxbq , VexRm_Lx , V(660F38,32,_,x,I,I,1,OVM), 0 , 203, 0 , 8445 , 356, 127), // #1304
+ INST(Vpmovzxbw , VexRm_Lx , V(660F38,30,_,x,I,I,3,HVM), 0 , 127, 0 , 8455 , 357, 142), // #1305
+ INST(Vpmovzxdq , VexRm_Lx , V(660F38,35,_,x,I,0,3,HVM), 0 , 127, 0 , 8465 , 357, 127), // #1306
+ INST(Vpmovzxwd , VexRm_Lx , V(660F38,33,_,x,I,I,3,HVM), 0 , 127, 0 , 8475 , 357, 127), // #1307
+ INST(Vpmovzxwq , VexRm_Lx , V(660F38,34,_,x,I,I,2,QVM), 0 , 202, 0 , 8485 , 355, 127), // #1308
+ INST(Vpmuldq , VexRvm_Lx , V(660F38,28,_,x,I,1,4,FV ), 0 , 193, 0 , 8495 , 194, 127), // #1309
+ INST(Vpmulhrsw , VexRvm_Lx , V(660F38,0B,_,x,I,I,4,FVM), 0 , 102, 0 , 8503 , 281, 142), // #1310
+ INST(Vpmulhuw , VexRvm_Lx , V(660F00,E4,_,x,I,I,4,FVM), 0 , 179, 0 , 8513 , 281, 142), // #1311
+ INST(Vpmulhw , VexRvm_Lx , V(660F00,E5,_,x,I,I,4,FVM), 0 , 179, 0 , 8522 , 281, 142), // #1312
+ INST(Vpmulld , VexRvm_Lx , V(660F38,40,_,x,I,0,4,FV ), 0 , 158, 0 , 8530 , 195, 127), // #1313
+ INST(Vpmullq , VexRvm_Lx , E(660F38,40,_,x,_,1,4,FV ), 0 , 107, 0 , 8538 , 200, 125), // #1314
+ INST(Vpmullw , VexRvm_Lx , V(660F00,D5,_,x,I,I,4,FVM), 0 , 179, 0 , 8546 , 281, 142), // #1315
+ INST(Vpmultishiftqb , VexRvm_Lx , E(660F38,83,_,x,_,1,4,FV ), 0 , 107, 0 , 8554 , 200, 149), // #1316
+ INST(Vpmuludq , VexRvm_Lx , V(660F00,F4,_,x,I,1,4,FV ), 0 , 97 , 0 , 8569 , 194, 127), // #1317
+ INST(Vpopcntb , VexRm_Lx , E(660F38,54,_,x,_,0,4,FV ), 0 , 106, 0 , 8578 , 250, 153), // #1318
+ INST(Vpopcntd , VexRm_Lx , E(660F38,55,_,x,_,0,4,FVM), 0 , 105, 0 , 8587 , 335, 154), // #1319
+ INST(Vpopcntq , VexRm_Lx , E(660F38,55,_,x,_,1,4,FVM), 0 , 108, 0 , 8596 , 348, 154), // #1320
+ INST(Vpopcntw , VexRm_Lx , E(660F38,54,_,x,_,1,4,FV ), 0 , 107, 0 , 8605 , 250, 153), // #1321
+ INST(Vpor , VexRvm_Lx , V(660F00,EB,_,x,I,_,_,_ ), 0 , 63 , 0 , 8614 , 313, 139), // #1322
+ INST(Vpord , VexRvm_Lx , E(660F00,EB,_,x,_,0,4,FV ), 0 , 184, 0 , 8619 , 314, 122), // #1323
+ INST(Vporq , VexRvm_Lx , E(660F00,EB,_,x,_,1,4,FV ), 0 , 125, 0 , 8625 , 318, 122), // #1324
+ INST(Vpperm , VexRvrmRvmr , V(XOP_M8,A3,_,0,x,_,_,_ ), 0 , 188, 0 , 8631 , 358, 135), // #1325
+ INST(Vprold , VexVmi_Lx , E(660F00,72,1,x,_,0,4,FV ), 0 , 204, 0 , 8638 , 359, 122), // #1326
+ INST(Vprolq , VexVmi_Lx , E(660F00,72,1,x,_,1,4,FV ), 0 , 205, 0 , 8645 , 360, 122), // #1327
+ INST(Vprolvd , VexRvm_Lx , E(660F38,15,_,x,_,0,4,FV ), 0 , 106, 0 , 8652 , 199, 122), // #1328
+ INST(Vprolvq , VexRvm_Lx , E(660F38,15,_,x,_,1,4,FV ), 0 , 107, 0 , 8660 , 200, 122), // #1329
+ INST(Vprord , VexVmi_Lx , E(660F00,72,0,x,_,0,4,FV ), 0 , 184, 0 , 8668 , 359, 122), // #1330
+ INST(Vprorq , VexVmi_Lx , E(660F00,72,0,x,_,1,4,FV ), 0 , 125, 0 , 8675 , 360, 122), // #1331
+ INST(Vprorvd , VexRvm_Lx , E(660F38,14,_,x,_,0,4,FV ), 0 , 106, 0 , 8682 , 199, 122), // #1332
+ INST(Vprorvq , VexRvm_Lx , E(660F38,14,_,x,_,1,4,FV ), 0 , 107, 0 , 8690 , 200, 122), // #1333
+ INST(Vprotb , VexRvmRmvRmi , V(XOP_M9,90,_,0,x,_,_,_ ), V(XOP_M8,C0,_,0,x,_,_,_ ), 72 , 119, 8698 , 361, 135), // #1334
+ INST(Vprotd , VexRvmRmvRmi , V(XOP_M9,92,_,0,x,_,_,_ ), V(XOP_M8,C2,_,0,x,_,_,_ ), 72 , 120, 8705 , 361, 135), // #1335
+ INST(Vprotq , VexRvmRmvRmi , V(XOP_M9,93,_,0,x,_,_,_ ), V(XOP_M8,C3,_,0,x,_,_,_ ), 72 , 121, 8712 , 361, 135), // #1336
+ INST(Vprotw , VexRvmRmvRmi , V(XOP_M9,91,_,0,x,_,_,_ ), V(XOP_M8,C1,_,0,x,_,_,_ ), 72 , 122, 8719 , 361, 135), // #1337
+ INST(Vpsadbw , VexRvm_Lx , V(660F00,F6,_,x,I,I,4,FVM), 0 , 179, 0 , 8726 , 189, 142), // #1338
+ INST(Vpscatterdd , VexMr_VM , E(660F38,A0,_,x,_,0,2,T1S), 0 , 120, 0 , 8734 , 362, 122), // #1339
+ INST(Vpscatterdq , VexMr_VM , E(660F38,A0,_,x,_,1,3,T1S), 0 , 119, 0 , 8746 , 362, 122), // #1340
+ INST(Vpscatterqd , VexMr_VM , E(660F38,A1,_,x,_,0,2,T1S), 0 , 120, 0 , 8758 , 363, 122), // #1341
+ INST(Vpscatterqq , VexMr_VM , E(660F38,A1,_,x,_,1,3,T1S), 0 , 119, 0 , 8770 , 364, 122), // #1342
+ INST(Vpshab , VexRvmRmv , V(XOP_M9,98,_,0,x,_,_,_ ), 0 , 72 , 0 , 8782 , 365, 135), // #1343
+ INST(Vpshad , VexRvmRmv , V(XOP_M9,9A,_,0,x,_,_,_ ), 0 , 72 , 0 , 8789 , 365, 135), // #1344
+ INST(Vpshaq , VexRvmRmv , V(XOP_M9,9B,_,0,x,_,_,_ ), 0 , 72 , 0 , 8796 , 365, 135), // #1345
+ INST(Vpshaw , VexRvmRmv , V(XOP_M9,99,_,0,x,_,_,_ ), 0 , 72 , 0 , 8803 , 365, 135), // #1346
+ INST(Vpshlb , VexRvmRmv , V(XOP_M9,94,_,0,x,_,_,_ ), 0 , 72 , 0 , 8810 , 365, 135), // #1347
+ INST(Vpshld , VexRvmRmv , V(XOP_M9,96,_,0,x,_,_,_ ), 0 , 72 , 0 , 8817 , 365, 135), // #1348
+ INST(Vpshldd , VexRvmi_Lx , E(660F3A,71,_,x,_,0,4,FV ), 0 , 103, 0 , 8824 , 192, 147), // #1349
+ INST(Vpshldq , VexRvmi_Lx , E(660F3A,71,_,x,_,1,4,FV ), 0 , 104, 0 , 8832 , 193, 147), // #1350
+ INST(Vpshldvd , VexRvm_Lx , E(660F38,71,_,x,_,0,4,FV ), 0 , 106, 0 , 8840 , 199, 147), // #1351
+ INST(Vpshldvq , VexRvm_Lx , E(660F38,71,_,x,_,1,4,FV ), 0 , 107, 0 , 8849 , 200, 147), // #1352
+ INST(Vpshldvw , VexRvm_Lx , E(660F38,70,_,x,_,0,4,FVM), 0 , 105, 0 , 8858 , 198, 147), // #1353
+ INST(Vpshldw , VexRvmi_Lx , E(660F3A,70,_,x,_,0,4,FVM), 0 , 146, 0 , 8867 , 246, 147), // #1354
+ INST(Vpshlq , VexRvmRmv , V(XOP_M9,97,_,0,x,_,_,_ ), 0 , 72 , 0 , 8875 , 365, 135), // #1355
+ INST(Vpshlw , VexRvmRmv , V(XOP_M9,95,_,0,x,_,_,_ ), 0 , 72 , 0 , 8882 , 365, 135), // #1356
+ INST(Vpshrdd , VexRvmi_Lx , E(660F3A,73,_,x,_,0,4,FV ), 0 , 103, 0 , 8889 , 192, 147), // #1357
+ INST(Vpshrdq , VexRvmi_Lx , E(660F3A,73,_,x,_,1,4,FV ), 0 , 104, 0 , 8897 , 193, 147), // #1358
+ INST(Vpshrdvd , VexRvm_Lx , E(660F38,73,_,x,_,0,4,FV ), 0 , 106, 0 , 8905 , 199, 147), // #1359
+ INST(Vpshrdvq , VexRvm_Lx , E(660F38,73,_,x,_,1,4,FV ), 0 , 107, 0 , 8914 , 200, 147), // #1360
+ INST(Vpshrdvw , VexRvm_Lx , E(660F38,72,_,x,_,0,4,FVM), 0 , 105, 0 , 8923 , 198, 147), // #1361
+ INST(Vpshrdw , VexRvmi_Lx , E(660F3A,72,_,x,_,0,4,FVM), 0 , 146, 0 , 8932 , 246, 147), // #1362
+ INST(Vpshufb , VexRvm_Lx , V(660F38,00,_,x,I,I,4,FVM), 0 , 102, 0 , 8940 , 281, 142), // #1363
+ INST(Vpshufbitqmb , VexRvm_Lx , E(660F38,8F,_,x,0,0,4,FVM), 0 , 105, 0 , 8948 , 366, 153), // #1364
+ INST(Vpshufd , VexRmi_Lx , V(660F00,70,_,x,I,0,4,FV ), 0 , 128, 0 , 8961 , 367, 127), // #1365
+ INST(Vpshufhw , VexRmi_Lx , V(F30F00,70,_,x,I,I,4,FVM), 0 , 180, 0 , 8969 , 368, 142), // #1366
+ INST(Vpshuflw , VexRmi_Lx , V(F20F00,70,_,x,I,I,4,FVM), 0 , 206, 0 , 8978 , 368, 142), // #1367
+ INST(Vpsignb , VexRvm_Lx , V(660F38,08,_,x,I,_,_,_ ), 0 , 90 , 0 , 8987 , 188, 139), // #1368
+ INST(Vpsignd , VexRvm_Lx , V(660F38,0A,_,x,I,_,_,_ ), 0 , 90 , 0 , 8995 , 188, 139), // #1369
+ INST(Vpsignw , VexRvm_Lx , V(660F38,09,_,x,I,_,_,_ ), 0 , 90 , 0 , 9003 , 188, 139), // #1370
+ INST(Vpslld , VexRvmVmi_Lx , V(660F00,F2,_,x,I,0,4,128), V(660F00,72,6,x,I,0,4,FV ), 207, 123, 9011 , 369, 127), // #1371
+ INST(Vpslldq , VexEvexVmi_Lx , V(660F00,73,7,x,I,I,4,FVM), 0 , 208, 0 , 9018 , 370, 142), // #1372
+ INST(Vpsllq , VexRvmVmi_Lx , V(660F00,F3,_,x,I,1,4,128), V(660F00,73,6,x,I,1,4,FV ), 209, 124, 9026 , 371, 127), // #1373
+ INST(Vpsllvd , VexRvm_Lx , V(660F38,47,_,x,0,0,4,FV ), 0 , 158, 0 , 9033 , 195, 136), // #1374
+ INST(Vpsllvq , VexRvm_Lx , V(660F38,47,_,x,1,1,4,FV ), 0 , 157, 0 , 9041 , 194, 136), // #1375
+ INST(Vpsllvw , VexRvm_Lx , E(660F38,12,_,x,_,1,4,FVM), 0 , 108, 0 , 9049 , 198, 124), // #1376
+ INST(Vpsllw , VexRvmVmi_Lx , V(660F00,F1,_,x,I,I,4,FVM), V(660F00,71,6,x,I,I,4,FVM), 179, 125, 9057 , 372, 142), // #1377
+ INST(Vpsrad , VexRvmVmi_Lx , V(660F00,E2,_,x,I,0,4,128), V(660F00,72,4,x,I,0,4,FV ), 207, 126, 9064 , 369, 127), // #1378
+ INST(Vpsraq , VexRvmVmi_Lx , E(660F00,E2,_,x,_,1,4,128), E(660F00,72,4,x,_,1,4,FV ), 210, 127, 9071 , 373, 122), // #1379
+ INST(Vpsravd , VexRvm_Lx , V(660F38,46,_,x,0,0,4,FV ), 0 , 158, 0 , 9078 , 195, 136), // #1380
+ INST(Vpsravq , VexRvm_Lx , E(660F38,46,_,x,_,1,4,FV ), 0 , 107, 0 , 9086 , 200, 122), // #1381
+ INST(Vpsravw , VexRvm_Lx , E(660F38,11,_,x,_,1,4,FVM), 0 , 108, 0 , 9094 , 198, 124), // #1382
+ INST(Vpsraw , VexRvmVmi_Lx , V(660F00,E1,_,x,I,I,4,128), V(660F00,71,4,x,I,I,4,FVM), 207, 128, 9102 , 372, 142), // #1383
+ INST(Vpsrld , VexRvmVmi_Lx , V(660F00,D2,_,x,I,0,4,128), V(660F00,72,2,x,I,0,4,FV ), 207, 129, 9109 , 369, 127), // #1384
+ INST(Vpsrldq , VexEvexVmi_Lx , V(660F00,73,3,x,I,I,4,FVM), 0 , 211, 0 , 9116 , 370, 142), // #1385
+ INST(Vpsrlq , VexRvmVmi_Lx , V(660F00,D3,_,x,I,1,4,128), V(660F00,73,2,x,I,1,4,FV ), 209, 130, 9124 , 371, 127), // #1386
+ INST(Vpsrlvd , VexRvm_Lx , V(660F38,45,_,x,0,0,4,FV ), 0 , 158, 0 , 9131 , 195, 136), // #1387
+ INST(Vpsrlvq , VexRvm_Lx , V(660F38,45,_,x,1,1,4,FV ), 0 , 157, 0 , 9139 , 194, 136), // #1388
+ INST(Vpsrlvw , VexRvm_Lx , E(660F38,10,_,x,_,1,4,FVM), 0 , 108, 0 , 9147 , 198, 124), // #1389
+ INST(Vpsrlw , VexRvmVmi_Lx , V(660F00,D1,_,x,I,I,4,128), V(660F00,71,2,x,I,I,4,FVM), 207, 131, 9155 , 372, 142), // #1390
+ INST(Vpsubb , VexRvm_Lx , V(660F00,F8,_,x,I,I,4,FVM), 0 , 179, 0 , 9162 , 374, 142), // #1391
+ INST(Vpsubd , VexRvm_Lx , V(660F00,FA,_,x,I,0,4,FV ), 0 , 128, 0 , 9169 , 375, 127), // #1392
+ INST(Vpsubq , VexRvm_Lx , V(660F00,FB,_,x,I,1,4,FV ), 0 , 97 , 0 , 9176 , 376, 127), // #1393
+ INST(Vpsubsb , VexRvm_Lx , V(660F00,E8,_,x,I,I,4,FVM), 0 , 179, 0 , 9183 , 374, 142), // #1394
+ INST(Vpsubsw , VexRvm_Lx , V(660F00,E9,_,x,I,I,4,FVM), 0 , 179, 0 , 9191 , 374, 142), // #1395
+ INST(Vpsubusb , VexRvm_Lx , V(660F00,D8,_,x,I,I,4,FVM), 0 , 179, 0 , 9199 , 374, 142), // #1396
+ INST(Vpsubusw , VexRvm_Lx , V(660F00,D9,_,x,I,I,4,FVM), 0 , 179, 0 , 9208 , 374, 142), // #1397
+ INST(Vpsubw , VexRvm_Lx , V(660F00,F9,_,x,I,I,4,FVM), 0 , 179, 0 , 9217 , 374, 142), // #1398
+ INST(Vpternlogd , VexRvmi_Lx , E(660F3A,25,_,x,_,0,4,FV ), 0 , 103, 0 , 9224 , 192, 122), // #1399
+ INST(Vpternlogq , VexRvmi_Lx , E(660F3A,25,_,x,_,1,4,FV ), 0 , 104, 0 , 9235 , 193, 122), // #1400
+ INST(Vptest , VexRm_Lx , V(660F38,17,_,x,I,_,_,_ ), 0 , 90 , 0 , 9246 , 266, 146), // #1401
+ INST(Vptestmb , VexRvm_Lx , E(660F38,26,_,x,_,0,4,FVM), 0 , 105, 0 , 9253 , 366, 124), // #1402
+ INST(Vptestmd , VexRvm_Lx , E(660F38,27,_,x,_,0,4,FV ), 0 , 106, 0 , 9262 , 377, 122), // #1403
+ INST(Vptestmq , VexRvm_Lx , E(660F38,27,_,x,_,1,4,FV ), 0 , 107, 0 , 9271 , 378, 122), // #1404
+ INST(Vptestmw , VexRvm_Lx , E(660F38,26,_,x,_,1,4,FVM), 0 , 108, 0 , 9280 , 366, 124), // #1405
+ INST(Vptestnmb , VexRvm_Lx , E(F30F38,26,_,x,_,0,4,FVM), 0 , 212, 0 , 9289 , 366, 124), // #1406
+ INST(Vptestnmd , VexRvm_Lx , E(F30F38,27,_,x,_,0,4,FV ), 0 , 213, 0 , 9299 , 377, 122), // #1407
+ INST(Vptestnmq , VexRvm_Lx , E(F30F38,27,_,x,_,1,4,FV ), 0 , 214, 0 , 9309 , 378, 122), // #1408
+ INST(Vptestnmw , VexRvm_Lx , E(F30F38,26,_,x,_,1,4,FVM), 0 , 215, 0 , 9319 , 366, 124), // #1409
+ INST(Vpunpckhbw , VexRvm_Lx , V(660F00,68,_,x,I,I,4,FVM), 0 , 179, 0 , 9329 , 281, 142), // #1410
+ INST(Vpunpckhdq , VexRvm_Lx , V(660F00,6A,_,x,I,0,4,FV ), 0 , 128, 0 , 9340 , 195, 127), // #1411
+ INST(Vpunpckhqdq , VexRvm_Lx , V(660F00,6D,_,x,I,1,4,FV ), 0 , 97 , 0 , 9351 , 194, 127), // #1412
+ INST(Vpunpckhwd , VexRvm_Lx , V(660F00,69,_,x,I,I,4,FVM), 0 , 179, 0 , 9363 , 281, 142), // #1413
+ INST(Vpunpcklbw , VexRvm_Lx , V(660F00,60,_,x,I,I,4,FVM), 0 , 179, 0 , 9374 , 281, 142), // #1414
+ INST(Vpunpckldq , VexRvm_Lx , V(660F00,62,_,x,I,0,4,FV ), 0 , 128, 0 , 9385 , 195, 127), // #1415
+ INST(Vpunpcklqdq , VexRvm_Lx , V(660F00,6C,_,x,I,1,4,FV ), 0 , 97 , 0 , 9396 , 194, 127), // #1416
+ INST(Vpunpcklwd , VexRvm_Lx , V(660F00,61,_,x,I,I,4,FVM), 0 , 179, 0 , 9408 , 281, 142), // #1417
+ INST(Vpxor , VexRvm_Lx , V(660F00,EF,_,x,I,_,_,_ ), 0 , 63 , 0 , 9419 , 315, 139), // #1418
+ INST(Vpxord , VexRvm_Lx , E(660F00,EF,_,x,_,0,4,FV ), 0 , 184, 0 , 9425 , 316, 122), // #1419
+ INST(Vpxorq , VexRvm_Lx , E(660F00,EF,_,x,_,1,4,FV ), 0 , 125, 0 , 9432 , 317, 122), // #1420
+ INST(Vrangepd , VexRvmi_Lx , E(660F3A,50,_,x,_,1,4,FV ), 0 , 104, 0 , 9439 , 255, 125), // #1421
+ INST(Vrangeps , VexRvmi_Lx , E(660F3A,50,_,x,_,0,4,FV ), 0 , 103, 0 , 9448 , 256, 125), // #1422
+ INST(Vrangesd , VexRvmi , E(660F3A,51,_,I,_,1,3,T1S), 0 , 155, 0 , 9457 , 257, 61 ), // #1423
+ INST(Vrangess , VexRvmi , E(660F3A,51,_,I,_,0,2,T1S), 0 , 156, 0 , 9466 , 258, 61 ), // #1424
+ INST(Vrcp14pd , VexRm_Lx , E(660F38,4C,_,x,_,1,4,FV ), 0 , 107, 0 , 9475 , 348, 122), // #1425
+ INST(Vrcp14ps , VexRm_Lx , E(660F38,4C,_,x,_,0,4,FV ), 0 , 106, 0 , 9484 , 335, 122), // #1426
+ INST(Vrcp14sd , VexRvm , E(660F38,4D,_,I,_,1,3,T1S), 0 , 119, 0 , 9493 , 379, 63 ), // #1427
+ INST(Vrcp14ss , VexRvm , E(660F38,4D,_,I,_,0,2,T1S), 0 , 120, 0 , 9502 , 380, 63 ), // #1428
+ INST(Vrcp28pd , VexRm , E(660F38,CA,_,2,_,1,4,FV ), 0 , 147, 0 , 9511 , 248, 131), // #1429
+ INST(Vrcp28ps , VexRm , E(660F38,CA,_,2,_,0,4,FV ), 0 , 148, 0 , 9520 , 249, 131), // #1430
+ INST(Vrcp28sd , VexRvm , E(660F38,CB,_,I,_,1,3,T1S), 0 , 119, 0 , 9529 , 276, 131), // #1431
+ INST(Vrcp28ss , VexRvm , E(660F38,CB,_,I,_,0,2,T1S), 0 , 120, 0 , 9538 , 277, 131), // #1432
+ INST(Vrcpps , VexRm_Lx , V(000F00,53,_,x,I,_,_,_ ), 0 , 66 , 0 , 9547 , 266, 119), // #1433
+ INST(Vrcpss , VexRvm , V(F30F00,53,_,I,I,_,_,_ ), 0 , 173, 0 , 9554 , 381, 119), // #1434
+ INST(Vreducepd , VexRmi_Lx , E(660F3A,56,_,x,_,1,4,FV ), 0 , 104, 0 , 9561 , 360, 125), // #1435
+ INST(Vreduceps , VexRmi_Lx , E(660F3A,56,_,x,_,0,4,FV ), 0 , 103, 0 , 9571 , 359, 125), // #1436
+ INST(Vreducesd , VexRvmi , E(660F3A,57,_,I,_,1,3,T1S), 0 , 155, 0 , 9581 , 382, 61 ), // #1437
+ INST(Vreducess , VexRvmi , E(660F3A,57,_,I,_,0,2,T1S), 0 , 156, 0 , 9591 , 383, 61 ), // #1438
+ INST(Vrndscalepd , VexRmi_Lx , E(660F3A,09,_,x,_,1,4,FV ), 0 , 104, 0 , 9601 , 278, 122), // #1439
+ INST(Vrndscaleps , VexRmi_Lx , E(660F3A,08,_,x,_,0,4,FV ), 0 , 103, 0 , 9613 , 279, 122), // #1440
+ INST(Vrndscalesd , VexRvmi , E(660F3A,0B,_,I,_,1,3,T1S), 0 , 155, 0 , 9625 , 257, 63 ), // #1441
+ INST(Vrndscaless , VexRvmi , E(660F3A,0A,_,I,_,0,2,T1S), 0 , 156, 0 , 9637 , 258, 63 ), // #1442
+ INST(Vroundpd , VexRmi_Lx , V(660F3A,09,_,x,I,_,_,_ ), 0 , 67 , 0 , 9649 , 384, 119), // #1443
+ INST(Vroundps , VexRmi_Lx , V(660F3A,08,_,x,I,_,_,_ ), 0 , 67 , 0 , 9658 , 384, 119), // #1444
+ INST(Vroundsd , VexRvmi , V(660F3A,0B,_,I,I,_,_,_ ), 0 , 67 , 0 , 9667 , 385, 119), // #1445
+ INST(Vroundss , VexRvmi , V(660F3A,0A,_,I,I,_,_,_ ), 0 , 67 , 0 , 9676 , 386, 119), // #1446
+ INST(Vrsqrt14pd , VexRm_Lx , E(660F38,4E,_,x,_,1,4,FV ), 0 , 107, 0 , 9685 , 348, 122), // #1447
+ INST(Vrsqrt14ps , VexRm_Lx , E(660F38,4E,_,x,_,0,4,FV ), 0 , 106, 0 , 9696 , 335, 122), // #1448
+ INST(Vrsqrt14sd , VexRvm , E(660F38,4F,_,I,_,1,3,T1S), 0 , 119, 0 , 9707 , 379, 63 ), // #1449
+ INST(Vrsqrt14ss , VexRvm , E(660F38,4F,_,I,_,0,2,T1S), 0 , 120, 0 , 9718 , 380, 63 ), // #1450
+ INST(Vrsqrt28pd , VexRm , E(660F38,CC,_,2,_,1,4,FV ), 0 , 147, 0 , 9729 , 248, 131), // #1451
+ INST(Vrsqrt28ps , VexRm , E(660F38,CC,_,2,_,0,4,FV ), 0 , 148, 0 , 9740 , 249, 131), // #1452
+ INST(Vrsqrt28sd , VexRvm , E(660F38,CD,_,I,_,1,3,T1S), 0 , 119, 0 , 9751 , 276, 131), // #1453
+ INST(Vrsqrt28ss , VexRvm , E(660F38,CD,_,I,_,0,2,T1S), 0 , 120, 0 , 9762 , 277, 131), // #1454
+ INST(Vrsqrtps , VexRm_Lx , V(000F00,52,_,x,I,_,_,_ ), 0 , 66 , 0 , 9773 , 266, 119), // #1455
+ INST(Vrsqrtss , VexRvm , V(F30F00,52,_,I,I,_,_,_ ), 0 , 173, 0 , 9782 , 381, 119), // #1456
+ INST(Vscalefpd , VexRvm_Lx , E(660F38,2C,_,x,_,1,4,FV ), 0 , 107, 0 , 9791 , 387, 122), // #1457
+ INST(Vscalefps , VexRvm_Lx , E(660F38,2C,_,x,_,0,4,FV ), 0 , 106, 0 , 9801 , 388, 122), // #1458
+ INST(Vscalefsd , VexRvm , E(660F38,2D,_,I,_,1,3,T1S), 0 , 119, 0 , 9811 , 389, 63 ), // #1459
+ INST(Vscalefss , VexRvm , E(660F38,2D,_,I,_,0,2,T1S), 0 , 120, 0 , 9821 , 390, 63 ), // #1460
+ INST(Vscatterdpd , VexMr_Lx , E(660F38,A2,_,x,_,1,3,T1S), 0 , 119, 0 , 9831 , 391, 122), // #1461
+ INST(Vscatterdps , VexMr_Lx , E(660F38,A2,_,x,_,0,2,T1S), 0 , 120, 0 , 9843 , 362, 122), // #1462
+ INST(Vscatterpf0dpd , VexM_VM , E(660F38,C6,5,2,_,1,3,T1S), 0 , 216, 0 , 9855 , 271, 137), // #1463
+ INST(Vscatterpf0dps , VexM_VM , E(660F38,C6,5,2,_,0,2,T1S), 0 , 217, 0 , 9870 , 272, 137), // #1464
+ INST(Vscatterpf0qpd , VexM_VM , E(660F38,C7,5,2,_,1,3,T1S), 0 , 216, 0 , 9885 , 273, 137), // #1465
+ INST(Vscatterpf0qps , VexM_VM , E(660F38,C7,5,2,_,0,2,T1S), 0 , 217, 0 , 9900 , 273, 137), // #1466
+ INST(Vscatterpf1dpd , VexM_VM , E(660F38,C6,6,2,_,1,3,T1S), 0 , 218, 0 , 9915 , 271, 137), // #1467
+ INST(Vscatterpf1dps , VexM_VM , E(660F38,C6,6,2,_,0,2,T1S), 0 , 219, 0 , 9930 , 272, 137), // #1468
+ INST(Vscatterpf1qpd , VexM_VM , E(660F38,C7,6,2,_,1,3,T1S), 0 , 218, 0 , 9945 , 273, 137), // #1469
+ INST(Vscatterpf1qps , VexM_VM , E(660F38,C7,6,2,_,0,2,T1S), 0 , 219, 0 , 9960 , 273, 137), // #1470
+ INST(Vscatterqpd , VexMr_Lx , E(660F38,A3,_,x,_,1,3,T1S), 0 , 119, 0 , 9975 , 364, 122), // #1471
+ INST(Vscatterqps , VexMr_Lx , E(660F38,A3,_,x,_,0,2,T1S), 0 , 120, 0 , 9987 , 363, 122), // #1472
+ INST(Vshuff32x4 , VexRvmi_Lx , E(660F3A,23,_,x,_,0,4,FV ), 0 , 103, 0 , 9999 , 392, 122), // #1473
+ INST(Vshuff64x2 , VexRvmi_Lx , E(660F3A,23,_,x,_,1,4,FV ), 0 , 104, 0 , 10010, 393, 122), // #1474
+ INST(Vshufi32x4 , VexRvmi_Lx , E(660F3A,43,_,x,_,0,4,FV ), 0 , 103, 0 , 10021, 392, 122), // #1475
+ INST(Vshufi64x2 , VexRvmi_Lx , E(660F3A,43,_,x,_,1,4,FV ), 0 , 104, 0 , 10032, 393, 122), // #1476
+ INST(Vshufpd , VexRvmi_Lx , V(660F00,C6,_,x,I,1,4,FV ), 0 , 97 , 0 , 10043, 394, 117), // #1477
+ INST(Vshufps , VexRvmi_Lx , V(000F00,C6,_,x,I,0,4,FV ), 0 , 98 , 0 , 10051, 395, 117), // #1478
+ INST(Vsqrtpd , VexRm_Lx , V(660F00,51,_,x,I,1,4,FV ), 0 , 97 , 0 , 10059, 396, 117), // #1479
+ INST(Vsqrtps , VexRm_Lx , V(000F00,51,_,x,I,0,4,FV ), 0 , 98 , 0 , 10067, 218, 117), // #1480
+ INST(Vsqrtsd , VexRvm , V(F20F00,51,_,I,I,1,3,T1S), 0 , 99 , 0 , 10075, 186, 118), // #1481
+ INST(Vsqrtss , VexRvm , V(F30F00,51,_,I,I,0,2,T1S), 0 , 100, 0 , 10083, 187, 118), // #1482
+ INST(Vstmxcsr , VexM , V(000F00,AE,3,0,I,_,_,_ ), 0 , 220, 0 , 10091, 287, 119), // #1483
+ INST(Vsubpd , VexRvm_Lx , V(660F00,5C,_,x,I,1,4,FV ), 0 , 97 , 0 , 10100, 184, 117), // #1484
+ INST(Vsubps , VexRvm_Lx , V(000F00,5C,_,x,I,0,4,FV ), 0 , 98 , 0 , 10107, 185, 117), // #1485
+ INST(Vsubsd , VexRvm , V(F20F00,5C,_,I,I,1,3,T1S), 0 , 99 , 0 , 10114, 186, 118), // #1486
+ INST(Vsubss , VexRvm , V(F30F00,5C,_,I,I,0,2,T1S), 0 , 100, 0 , 10121, 187, 118), // #1487
+ INST(Vtestpd , VexRm_Lx , V(660F38,0F,_,x,0,_,_,_ ), 0 , 90 , 0 , 10128, 266, 146), // #1488
+ INST(Vtestps , VexRm_Lx , V(660F38,0E,_,x,0,_,_,_ ), 0 , 90 , 0 , 10136, 266, 146), // #1489
+ INST(Vucomisd , VexRm , V(660F00,2E,_,I,I,1,3,T1S), 0 , 117, 0 , 10144, 214, 128), // #1490
+ INST(Vucomiss , VexRm , V(000F00,2E,_,I,I,0,2,T1S), 0 , 118, 0 , 10153, 215, 128), // #1491
+ INST(Vunpckhpd , VexRvm_Lx , V(660F00,15,_,x,I,1,4,FV ), 0 , 97 , 0 , 10162, 194, 117), // #1492
+ INST(Vunpckhps , VexRvm_Lx , V(000F00,15,_,x,I,0,4,FV ), 0 , 98 , 0 , 10172, 195, 117), // #1493
+ INST(Vunpcklpd , VexRvm_Lx , V(660F00,14,_,x,I,1,4,FV ), 0 , 97 , 0 , 10182, 194, 117), // #1494
+ INST(Vunpcklps , VexRvm_Lx , V(000F00,14,_,x,I,0,4,FV ), 0 , 98 , 0 , 10192, 195, 117), // #1495
+ INST(Vxorpd , VexRvm_Lx , V(660F00,57,_,x,I,1,4,FV ), 0 , 97 , 0 , 10202, 376, 123), // #1496
+ INST(Vxorps , VexRvm_Lx , V(000F00,57,_,x,I,0,4,FV ), 0 , 98 , 0 , 10209, 375, 123), // #1497
+ INST(Vzeroall , VexOp , V(000F00,77,_,1,I,_,_,_ ), 0 , 62 , 0 , 10216, 397, 119), // #1498
+ INST(Vzeroupper , VexOp , V(000F00,77,_,0,I,_,_,_ ), 0 , 66 , 0 , 10225, 397, 119), // #1499
+ INST(Wbinvd , X86Op , O(000F00,09,_,_,_,_,_,_ ), 0 , 4 , 0 , 10236, 30 , 0 ), // #1500
+ INST(Wbnoinvd , X86Op , O(F30F00,09,_,_,_,_,_,_ ), 0 , 6 , 0 , 10243, 30 , 155), // #1501
+ INST(Wrfsbase , X86M , O(F30F00,AE,2,_,x,_,_,_ ), 0 , 221, 0 , 10252, 162, 99 ), // #1502
+ INST(Wrgsbase , X86M , O(F30F00,AE,3,_,x,_,_,_ ), 0 , 222, 0 , 10261, 162, 99 ), // #1503
+ INST(Wrmsr , X86Op , O(000F00,30,_,_,_,_,_,_ ), 0 , 4 , 0 , 10270, 163, 100), // #1504
+ INST(Xabort , X86Op_O_I8 , O(000000,C6,7,_,_,_,_,_ ), 0 , 25 , 0 , 10276, 74 , 156), // #1505
+ INST(Xadd , X86Xadd , O(000F00,C0,_,_,x,_,_,_ ), 0 , 4 , 0 , 10283, 398, 36 ), // #1506
+ INST(Xbegin , X86JmpRel , O(000000,C7,7,_,_,_,_,_ ), 0 , 25 , 0 , 10288, 399, 156), // #1507
+ INST(Xchg , X86Xchg , O(000000,86,_,_,x,_,_,_ ), 0 , 0 , 0 , 448 , 400, 0 ), // #1508
+ INST(Xend , X86Op , O(000F01,D5,_,_,_,_,_,_ ), 0 , 21 , 0 , 10295, 30 , 156), // #1509
+ INST(Xgetbv , X86Op , O(000F01,D0,_,_,_,_,_,_ ), 0 , 21 , 0 , 10300, 163, 157), // #1510
+ INST(Xlatb , X86Op , O(000000,D7,_,_,_,_,_,_ ), 0 , 0 , 0 , 10307, 30 , 0 ), // #1511
+ INST(Xor , X86Arith , O(000000,30,6,_,x,_,_,_ ), 0 , 30 , 0 , 9421 , 168, 1 ), // #1512
+ INST(Xorpd , ExtRm , O(660F00,57,_,_,_,_,_,_ ), 0 , 3 , 0 , 10203, 141, 4 ), // #1513
+ INST(Xorps , ExtRm , O(000F00,57,_,_,_,_,_,_ ), 0 , 4 , 0 , 10210, 141, 5 ), // #1514
+ INST(Xresldtrk , X86Op , O(F20F01,E9,_,_,_,_,_,_ ), 0 , 86 , 0 , 10313, 30 , 158), // #1515
+ INST(Xrstor , X86M_Only , O(000F00,AE,5,_,_,_,_,_ ), 0 , 70 , 0 , 1134 , 401, 157), // #1516
+ INST(Xrstor64 , X86M_Only , O(000F00,AE,5,_,1,_,_,_ ), 0 , 223, 0 , 1142 , 402, 157), // #1517
+ INST(Xrstors , X86M_Only , O(000F00,C7,3,_,_,_,_,_ ), 0 , 71 , 0 , 10323, 401, 159), // #1518
+ INST(Xrstors64 , X86M_Only , O(000F00,C7,3,_,1,_,_,_ ), 0 , 224, 0 , 10331, 402, 159), // #1519
+ INST(Xsave , X86M_Only , O(000F00,AE,4,_,_,_,_,_ ), 0 , 91 , 0 , 1152 , 401, 157), // #1520
+ INST(Xsave64 , X86M_Only , O(000F00,AE,4,_,1,_,_,_ ), 0 , 225, 0 , 1159 , 402, 157), // #1521
+ INST(Xsavec , X86M_Only , O(000F00,C7,4,_,_,_,_,_ ), 0 , 91 , 0 , 10341, 401, 160), // #1522
+ INST(Xsavec64 , X86M_Only , O(000F00,C7,4,_,1,_,_,_ ), 0 , 225, 0 , 10348, 402, 160), // #1523
+ INST(Xsaveopt , X86M_Only , O(000F00,AE,6,_,_,_,_,_ ), 0 , 73 , 0 , 10357, 401, 161), // #1524
+ INST(Xsaveopt64 , X86M_Only , O(000F00,AE,6,_,1,_,_,_ ), 0 , 226, 0 , 10366, 402, 161), // #1525
+ INST(Xsaves , X86M_Only , O(000F00,C7,5,_,_,_,_,_ ), 0 , 70 , 0 , 10377, 401, 159), // #1526
+ INST(Xsaves64 , X86M_Only , O(000F00,C7,5,_,1,_,_,_ ), 0 , 223, 0 , 10384, 402, 159), // #1527
+ INST(Xsetbv , X86Op , O(000F01,D1,_,_,_,_,_,_ ), 0 , 21 , 0 , 10393, 163, 157), // #1528
+ INST(Xsusldtrk , X86Op , O(F20F01,E8,_,_,_,_,_,_ ), 0 , 86 , 0 , 10400, 30 , 158), // #1529
+ INST(Xtest , X86Op , O(000F01,D6,_,_,_,_,_,_ ), 0 , 21 , 0 , 10410, 30 , 162) // #1530
// ${InstInfo:End}
};
#undef NAME_DATA_INDEX
@@ -1620,7 +1647,7 @@ const uint32_t InstDB::_mainOpcodeTable[] = {
O(F30F38,00,0,0,0,0,0,_ ), // #7 [ref=2x]
O(660F3A,00,0,0,0,0,0,_ ), // #8 [ref=22x]
O(000000,00,4,0,0,0,0,_ ), // #9 [ref=5x]
- V(000F38,00,0,0,0,0,0,_ ), // #10 [ref=3x]
+ V(000F38,00,0,0,0,0,0,_ ), // #10 [ref=6x]
V(XOP_M9,00,1,0,0,0,0,_ ), // #11 [ref=3x]
V(XOP_M9,00,6,0,0,0,0,_ ), // #12 [ref=2x]
V(XOP_M9,00,5,0,0,0,0,_ ), // #13 [ref=1x]
@@ -1631,10 +1658,10 @@ const uint32_t InstDB::_mainOpcodeTable[] = {
V(000F38,00,1,0,0,0,0,_ ), // #18 [ref=1x]
O(660000,00,0,0,0,0,0,_ ), // #19 [ref=7x]
O(000000,00,0,0,1,0,0,_ ), // #20 [ref=3x]
- O(000F01,00,0,0,0,0,0,_ ), // #21 [ref=25x]
+ O(000F01,00,0,0,0,0,0,_ ), // #21 [ref=28x]
O(000F00,00,7,0,0,0,0,_ ), // #22 [ref=5x]
O(660F00,00,7,0,0,0,0,_ ), // #23 [ref=2x]
- O(660F00,00,6,0,0,0,0,_ ), // #24 [ref=2x]
+ O(660F00,00,6,0,0,0,0,_ ), // #24 [ref=3x]
O(000000,00,7,0,0,0,0,_ ), // #25 [ref=5x]
O(000F00,00,1,0,1,0,0,_ ), // #26 [ref=2x]
O(000F00,00,1,0,0,0,0,_ ), // #27 [ref=6x]
@@ -1686,152 +1713,157 @@ const uint32_t InstDB::_mainOpcodeTable[] = {
O(000F00,00,6,0,0,0,0,_ ), // #73 [ref=5x]
V(XOP_MA,00,0,0,0,0,0,_ ), // #74 [ref=1x]
V(XOP_MA,00,1,0,0,0,0,_ ), // #75 [ref=1x]
- O(000F38,00,0,0,0,0,0,_ ), // #76 [ref=23x]
- V(F20F38,00,0,0,0,0,0,_ ), // #77 [ref=3x]
- O(000000,00,3,0,0,0,0,_ ), // #78 [ref=3x]
- O(000F3A,00,0,0,0,0,0,_ ), // #79 [ref=4x]
- O(F30000,00,0,0,0,0,0,_ ), // #80 [ref=1x]
- O(000F0F,00,0,0,0,0,0,_ ), // #81 [ref=26x]
- V(F30F38,00,0,0,0,0,0,_ ), // #82 [ref=2x]
- O(000F3A,00,0,0,1,0,0,_ ), // #83 [ref=1x]
- O(660F3A,00,0,0,1,0,0,_ ), // #84 [ref=1x]
- O(F30F00,00,1,0,0,0,0,_ ), // #85 [ref=1x]
- O(F30F00,00,7,0,0,0,0,_ ), // #86 [ref=1x]
- V(F20F3A,00,0,0,0,0,0,_ ), // #87 [ref=1x]
- V(660F38,00,0,0,0,0,0,_ ), // #88 [ref=22x]
- O(000F00,00,4,0,0,0,0,_ ), // #89 [ref=4x]
- V(XOP_M9,00,7,0,0,0,0,_ ), // #90 [ref=1x]
- V(XOP_M9,00,4,0,0,0,0,_ ), // #91 [ref=1x]
- E(F20F38,00,0,2,0,0,2,T4X), // #92 [ref=6x]
- V(660F00,00,0,0,0,1,4,FV ), // #93 [ref=22x]
- V(000F00,00,0,0,0,0,4,FV ), // #94 [ref=16x]
- V(F20F00,00,0,0,0,1,3,T1S), // #95 [ref=10x]
- V(F30F00,00,0,0,0,0,2,T1S), // #96 [ref=10x]
- V(F20F00,00,0,0,0,0,0,_ ), // #97 [ref=4x]
- V(660F38,00,0,0,0,0,4,FVM), // #98 [ref=14x]
- E(660F3A,00,0,0,0,0,4,FV ), // #99 [ref=14x]
- E(660F3A,00,0,0,0,1,4,FV ), // #100 [ref=14x]
- E(660F38,00,0,0,0,0,4,FVM), // #101 [ref=9x]
- E(660F38,00,0,0,0,0,4,FV ), // #102 [ref=22x]
- E(660F38,00,0,0,0,1,4,FV ), // #103 [ref=28x]
- E(660F38,00,0,0,0,1,4,FVM), // #104 [ref=9x]
- V(660F38,00,0,1,0,0,0,_ ), // #105 [ref=2x]
- E(660F38,00,0,0,0,0,3,T2 ), // #106 [ref=2x]
- E(660F38,00,0,0,0,0,4,T4 ), // #107 [ref=2x]
- E(660F38,00,0,2,0,0,5,T8 ), // #108 [ref=2x]
- E(660F38,00,0,0,0,1,4,T2 ), // #109 [ref=2x]
- E(660F38,00,0,2,0,1,5,T4 ), // #110 [ref=2x]
- V(660F38,00,0,0,0,1,3,T1S), // #111 [ref=2x]
- V(660F38,00,0,0,0,0,2,T1S), // #112 [ref=14x]
- V(660F00,00,0,0,0,1,3,T1S), // #113 [ref=5x]
- V(000F00,00,0,0,0,0,2,T1S), // #114 [ref=2x]
- E(660F38,00,0,0,0,1,3,T1S), // #115 [ref=14x]
- E(660F38,00,0,0,0,0,2,T1S), // #116 [ref=14x]
- V(F30F00,00,0,0,0,0,3,HV ), // #117 [ref=1x]
- E(F20F38,00,0,0,0,0,0,_ ), // #118 [ref=1x]
- E(F30F38,00,0,0,0,0,0,_ ), // #119 [ref=7x]
- V(F20F00,00,0,0,0,1,4,FV ), // #120 [ref=1x]
- E(660F00,00,0,0,0,1,4,FV ), // #121 [ref=9x]
- E(000F00,00,0,0,0,1,4,FV ), // #122 [ref=3x]
- V(660F38,00,0,0,0,0,3,HVM), // #123 [ref=7x]
- V(660F00,00,0,0,0,0,4,FV ), // #124 [ref=11x]
- V(000F00,00,0,0,0,0,4,HV ), // #125 [ref=1x]
- V(660F3A,00,0,0,0,0,3,HVM), // #126 [ref=1x]
- E(660F00,00,0,0,0,0,3,HV ), // #127 [ref=4x]
- E(000F00,00,0,0,0,0,4,FV ), // #128 [ref=2x]
- E(F30F00,00,0,0,0,1,4,FV ), // #129 [ref=2x]
- V(F20F00,00,0,0,0,0,3,T1F), // #130 [ref=2x]
- E(F20F00,00,0,0,0,0,3,T1F), // #131 [ref=2x]
- V(F20F00,00,0,0,0,0,2,T1W), // #132 [ref=1x]
- V(F30F00,00,0,0,0,0,2,T1W), // #133 [ref=1x]
- V(F30F00,00,0,0,0,0,2,T1F), // #134 [ref=2x]
- E(F30F00,00,0,0,0,0,2,T1F), // #135 [ref=2x]
- V(F30F00,00,0,0,0,0,4,FV ), // #136 [ref=1x]
- E(F30F00,00,0,0,0,0,3,HV ), // #137 [ref=1x]
- E(F20F00,00,0,0,0,0,4,FV ), // #138 [ref=1x]
- E(F20F00,00,0,0,0,1,4,FV ), // #139 [ref=1x]
- E(F20F00,00,0,0,0,0,2,T1W), // #140 [ref=1x]
- E(F30F00,00,0,0,0,0,2,T1W), // #141 [ref=1x]
- E(660F3A,00,0,0,0,0,4,FVM), // #142 [ref=5x]
- E(660F38,00,0,2,0,1,4,FV ), // #143 [ref=3x]
- E(660F38,00,0,2,0,0,4,FV ), // #144 [ref=3x]
- V(660F3A,00,0,1,0,0,0,_ ), // #145 [ref=6x]
- E(660F3A,00,0,0,0,0,4,T4 ), // #146 [ref=4x]
- E(660F3A,00,0,2,0,0,5,T8 ), // #147 [ref=4x]
- E(660F3A,00,0,0,0,1,4,T2 ), // #148 [ref=4x]
- E(660F3A,00,0,2,0,1,5,T4 ), // #149 [ref=4x]
- V(660F3A,00,0,0,0,0,2,T1S), // #150 [ref=4x]
- E(660F3A,00,0,0,0,1,3,T1S), // #151 [ref=6x]
- E(660F3A,00,0,0,0,0,2,T1S), // #152 [ref=6x]
- V(660F38,00,0,0,1,1,4,FV ), // #153 [ref=20x]
- V(660F38,00,0,0,0,0,4,FV ), // #154 [ref=32x]
- V(660F38,00,0,0,1,1,3,T1S), // #155 [ref=12x]
- V(660F38,00,0,0,1,0,0,_ ), // #156 [ref=5x]
- E(660F38,00,1,2,0,1,3,T1S), // #157 [ref=2x]
- E(660F38,00,1,2,0,0,2,T1S), // #158 [ref=2x]
- E(660F38,00,2,2,0,1,3,T1S), // #159 [ref=2x]
- E(660F38,00,2,2,0,0,2,T1S), // #160 [ref=2x]
- V(660F3A,00,0,0,1,1,4,FV ), // #161 [ref=2x]
- V(000F00,00,2,0,0,0,0,_ ), // #162 [ref=1x]
- V(660F00,00,0,0,0,1,4,FVM), // #163 [ref=3x]
- V(000F00,00,0,0,0,0,4,FVM), // #164 [ref=3x]
- V(660F00,00,0,0,0,0,2,T1S), // #165 [ref=1x]
- V(F20F00,00,0,0,0,1,3,DUP), // #166 [ref=1x]
- E(660F00,00,0,0,0,0,4,FVM), // #167 [ref=1x]
- E(660F00,00,0,0,0,1,4,FVM), // #168 [ref=1x]
- V(F30F00,00,0,0,0,0,0,_ ), // #169 [ref=3x]
- E(F20F00,00,0,0,0,1,4,FVM), // #170 [ref=1x]
- E(F30F00,00,0,0,0,0,4,FVM), // #171 [ref=1x]
- E(F30F00,00,0,0,0,1,4,FVM), // #172 [ref=1x]
- E(F20F00,00,0,0,0,0,4,FVM), // #173 [ref=1x]
- V(000F00,00,0,0,0,0,3,T2 ), // #174 [ref=2x]
- V(660F00,00,0,0,0,0,4,FVM), // #175 [ref=33x]
- V(F30F00,00,0,0,0,0,4,FVM), // #176 [ref=3x]
- O(F30F00,00,6,0,0,0,0,_ ), // #177 [ref=1x]
- V(660F3A,00,0,0,0,0,4,FVM), // #178 [ref=2x]
- E(660F00,00,0,0,0,0,4,FV ), // #179 [ref=5x]
- V(660F38,00,0,0,0,0,0,T1S), // #180 [ref=1x]
- E(F30F38,00,0,0,0,1,0,_ ), // #181 [ref=5x]
- V(660F38,00,0,0,0,0,1,T1S), // #182 [ref=1x]
- V(XOP_M8,00,0,0,0,0,0,_ ), // #183 [ref=22x]
- V(660F38,00,0,0,0,1,4,FVM), // #184 [ref=2x]
- E(660F3A,00,0,0,0,1,4,FVM), // #185 [ref=2x]
- E(660F38,00,0,0,0,0,0,T1S), // #186 [ref=2x]
- E(660F38,00,0,0,0,1,1,T1S), // #187 [ref=2x]
- V(660F38,00,0,0,0,1,4,FV ), // #188 [ref=3x]
- E(660F38,00,0,0,1,1,4,FV ), // #189 [ref=1x]
- V(660F3A,00,0,0,0,0,0,T1S), // #190 [ref=2x]
- V(660F3A,00,0,0,1,1,3,T1S), // #191 [ref=2x]
- V(660F3A,00,0,0,0,0,1,T1S), // #192 [ref=1x]
- V(660F00,00,0,0,0,0,1,T1S), // #193 [ref=1x]
- E(F30F38,00,0,0,0,0,2,QVM), // #194 [ref=6x]
- E(F30F38,00,0,0,0,0,3,HVM), // #195 [ref=9x]
- E(F30F38,00,0,0,0,0,1,OVM), // #196 [ref=3x]
- V(660F38,00,0,0,0,0,2,QVM), // #197 [ref=4x]
- V(660F38,00,0,0,0,0,1,OVM), // #198 [ref=2x]
- E(660F00,00,1,0,0,0,4,FV ), // #199 [ref=1x]
- E(660F00,00,1,0,0,1,4,FV ), // #200 [ref=1x]
- V(F20F00,00,0,0,0,0,4,FVM), // #201 [ref=1x]
- V(660F00,00,0,0,0,0,4,128), // #202 [ref=5x]
- V(660F00,00,7,0,0,0,4,FVM), // #203 [ref=1x]
- V(660F00,00,0,0,0,1,4,128), // #204 [ref=2x]
- E(660F00,00,0,0,0,1,4,128), // #205 [ref=1x]
- V(660F00,00,3,0,0,0,4,FVM), // #206 [ref=1x]
- E(F30F38,00,0,0,0,0,4,FVM), // #207 [ref=1x]
- E(F30F38,00,0,0,0,0,4,FV ), // #208 [ref=1x]
- E(F30F38,00,0,0,0,1,4,FV ), // #209 [ref=1x]
- E(F30F38,00,0,0,0,1,4,FVM), // #210 [ref=1x]
- E(660F38,00,5,2,0,1,3,T1S), // #211 [ref=2x]
- E(660F38,00,5,2,0,0,2,T1S), // #212 [ref=2x]
- E(660F38,00,6,2,0,1,3,T1S), // #213 [ref=2x]
- E(660F38,00,6,2,0,0,2,T1S), // #214 [ref=2x]
- V(000F00,00,3,0,0,0,0,_ ), // #215 [ref=1x]
- O(F30F00,00,2,0,0,0,0,_ ), // #216 [ref=1x]
- O(F30F00,00,3,0,0,0,0,_ ), // #217 [ref=1x]
- O(000F00,00,5,0,1,0,0,_ ), // #218 [ref=2x]
- O(000F00,00,3,0,1,0,0,_ ), // #219 [ref=1x]
- O(000F00,00,4,0,1,0,0,_ ), // #220 [ref=2x]
- O(000F00,00,6,0,1,0,0,_ ) // #221 [ref=1x]
+ O(F30F01,00,0,0,0,0,0,_ ), // #76 [ref=3x]
+ O(000F38,00,0,0,0,0,0,_ ), // #77 [ref=23x]
+ V(F20F38,00,0,0,0,0,0,_ ), // #78 [ref=6x]
+ O(000000,00,3,0,0,0,0,_ ), // #79 [ref=3x]
+ O(000F3A,00,0,0,0,0,0,_ ), // #80 [ref=4x]
+ O(F30000,00,0,0,0,0,0,_ ), // #81 [ref=1x]
+ O(000F0F,00,0,0,0,0,0,_ ), // #82 [ref=26x]
+ V(F30F38,00,0,0,0,0,0,_ ), // #83 [ref=5x]
+ O(000F3A,00,0,0,1,0,0,_ ), // #84 [ref=1x]
+ O(660F3A,00,0,0,1,0,0,_ ), // #85 [ref=1x]
+ O(F20F01,00,0,0,0,0,0,_ ), // #86 [ref=4x]
+ O(F30F00,00,1,0,0,0,0,_ ), // #87 [ref=1x]
+ O(F30F00,00,7,0,0,0,0,_ ), // #88 [ref=1x]
+ V(F20F3A,00,0,0,0,0,0,_ ), // #89 [ref=1x]
+ V(660F38,00,0,0,0,0,0,_ ), // #90 [ref=25x]
+ O(000F00,00,4,0,0,0,0,_ ), // #91 [ref=4x]
+ V(XOP_M9,00,7,0,0,0,0,_ ), // #92 [ref=1x]
+ V(XOP_M9,00,4,0,0,0,0,_ ), // #93 [ref=1x]
+ O(F30F00,00,6,0,0,0,0,_ ), // #94 [ref=2x]
+ O(F20F00,00,6,0,0,0,0,_ ), // #95 [ref=1x]
+ E(F20F38,00,0,2,0,0,2,T4X), // #96 [ref=6x]
+ V(660F00,00,0,0,0,1,4,FV ), // #97 [ref=22x]
+ V(000F00,00,0,0,0,0,4,FV ), // #98 [ref=16x]
+ V(F20F00,00,0,0,0,1,3,T1S), // #99 [ref=10x]
+ V(F30F00,00,0,0,0,0,2,T1S), // #100 [ref=10x]
+ V(F20F00,00,0,0,0,0,0,_ ), // #101 [ref=4x]
+ V(660F38,00,0,0,0,0,4,FVM), // #102 [ref=14x]
+ E(660F3A,00,0,0,0,0,4,FV ), // #103 [ref=14x]
+ E(660F3A,00,0,0,0,1,4,FV ), // #104 [ref=14x]
+ E(660F38,00,0,0,0,0,4,FVM), // #105 [ref=9x]
+ E(660F38,00,0,0,0,0,4,FV ), // #106 [ref=22x]
+ E(660F38,00,0,0,0,1,4,FV ), // #107 [ref=28x]
+ E(660F38,00,0,0,0,1,4,FVM), // #108 [ref=9x]
+ V(660F38,00,0,1,0,0,0,_ ), // #109 [ref=2x]
+ E(660F38,00,0,0,0,0,3,T2 ), // #110 [ref=2x]
+ E(660F38,00,0,0,0,0,4,T4 ), // #111 [ref=2x]
+ E(660F38,00,0,2,0,0,5,T8 ), // #112 [ref=2x]
+ E(660F38,00,0,0,0,1,4,T2 ), // #113 [ref=2x]
+ E(660F38,00,0,2,0,1,5,T4 ), // #114 [ref=2x]
+ V(660F38,00,0,0,0,1,3,T1S), // #115 [ref=2x]
+ V(660F38,00,0,0,0,0,2,T1S), // #116 [ref=14x]
+ V(660F00,00,0,0,0,1,3,T1S), // #117 [ref=5x]
+ V(000F00,00,0,0,0,0,2,T1S), // #118 [ref=2x]
+ E(660F38,00,0,0,0,1,3,T1S), // #119 [ref=14x]
+ E(660F38,00,0,0,0,0,2,T1S), // #120 [ref=14x]
+ V(F30F00,00,0,0,0,0,3,HV ), // #121 [ref=1x]
+ E(F20F38,00,0,0,0,0,0,_ ), // #122 [ref=1x]
+ E(F30F38,00,0,0,0,0,0,_ ), // #123 [ref=7x]
+ V(F20F00,00,0,0,0,1,4,FV ), // #124 [ref=1x]
+ E(660F00,00,0,0,0,1,4,FV ), // #125 [ref=9x]
+ E(000F00,00,0,0,0,1,4,FV ), // #126 [ref=3x]
+ V(660F38,00,0,0,0,0,3,HVM), // #127 [ref=7x]
+ V(660F00,00,0,0,0,0,4,FV ), // #128 [ref=11x]
+ V(000F00,00,0,0,0,0,4,HV ), // #129 [ref=1x]
+ V(660F3A,00,0,0,0,0,3,HVM), // #130 [ref=1x]
+ E(660F00,00,0,0,0,0,3,HV ), // #131 [ref=4x]
+ E(000F00,00,0,0,0,0,4,FV ), // #132 [ref=2x]
+ E(F30F00,00,0,0,0,1,4,FV ), // #133 [ref=2x]
+ V(F20F00,00,0,0,0,0,3,T1F), // #134 [ref=2x]
+ E(F20F00,00,0,0,0,0,3,T1F), // #135 [ref=2x]
+ V(F20F00,00,0,0,0,0,2,T1W), // #136 [ref=1x]
+ V(F30F00,00,0,0,0,0,2,T1W), // #137 [ref=1x]
+ V(F30F00,00,0,0,0,0,2,T1F), // #138 [ref=2x]
+ E(F30F00,00,0,0,0,0,2,T1F), // #139 [ref=2x]
+ V(F30F00,00,0,0,0,0,4,FV ), // #140 [ref=1x]
+ E(F30F00,00,0,0,0,0,3,HV ), // #141 [ref=1x]
+ E(F20F00,00,0,0,0,0,4,FV ), // #142 [ref=1x]
+ E(F20F00,00,0,0,0,1,4,FV ), // #143 [ref=1x]
+ E(F20F00,00,0,0,0,0,2,T1W), // #144 [ref=1x]
+ E(F30F00,00,0,0,0,0,2,T1W), // #145 [ref=1x]
+ E(660F3A,00,0,0,0,0,4,FVM), // #146 [ref=5x]
+ E(660F38,00,0,2,0,1,4,FV ), // #147 [ref=3x]
+ E(660F38,00,0,2,0,0,4,FV ), // #148 [ref=3x]
+ V(660F3A,00,0,1,0,0,0,_ ), // #149 [ref=6x]
+ E(660F3A,00,0,0,0,0,4,T4 ), // #150 [ref=4x]
+ E(660F3A,00,0,2,0,0,5,T8 ), // #151 [ref=4x]
+ E(660F3A,00,0,0,0,1,4,T2 ), // #152 [ref=4x]
+ E(660F3A,00,0,2,0,1,5,T4 ), // #153 [ref=4x]
+ V(660F3A,00,0,0,0,0,2,T1S), // #154 [ref=4x]
+ E(660F3A,00,0,0,0,1,3,T1S), // #155 [ref=6x]
+ E(660F3A,00,0,0,0,0,2,T1S), // #156 [ref=6x]
+ V(660F38,00,0,0,1,1,4,FV ), // #157 [ref=20x]
+ V(660F38,00,0,0,0,0,4,FV ), // #158 [ref=32x]
+ V(660F38,00,0,0,1,1,3,T1S), // #159 [ref=12x]
+ V(660F38,00,0,0,1,0,0,_ ), // #160 [ref=5x]
+ E(660F38,00,1,2,0,1,3,T1S), // #161 [ref=2x]
+ E(660F38,00,1,2,0,0,2,T1S), // #162 [ref=2x]
+ E(660F38,00,2,2,0,1,3,T1S), // #163 [ref=2x]
+ E(660F38,00,2,2,0,0,2,T1S), // #164 [ref=2x]
+ V(660F3A,00,0,0,1,1,4,FV ), // #165 [ref=2x]
+ V(000F00,00,2,0,0,0,0,_ ), // #166 [ref=1x]
+ V(660F00,00,0,0,0,1,4,FVM), // #167 [ref=3x]
+ V(000F00,00,0,0,0,0,4,FVM), // #168 [ref=3x]
+ V(660F00,00,0,0,0,0,2,T1S), // #169 [ref=1x]
+ V(F20F00,00,0,0,0,1,3,DUP), // #170 [ref=1x]
+ E(660F00,00,0,0,0,0,4,FVM), // #171 [ref=1x]
+ E(660F00,00,0,0,0,1,4,FVM), // #172 [ref=1x]
+ V(F30F00,00,0,0,0,0,0,_ ), // #173 [ref=3x]
+ E(F20F00,00,0,0,0,1,4,FVM), // #174 [ref=1x]
+ E(F30F00,00,0,0,0,0,4,FVM), // #175 [ref=1x]
+ E(F30F00,00,0,0,0,1,4,FVM), // #176 [ref=1x]
+ E(F20F00,00,0,0,0,0,4,FVM), // #177 [ref=1x]
+ V(000F00,00,0,0,0,0,3,T2 ), // #178 [ref=2x]
+ V(660F00,00,0,0,0,0,4,FVM), // #179 [ref=33x]
+ V(F30F00,00,0,0,0,0,4,FVM), // #180 [ref=3x]
+ E(F20F38,00,0,0,0,0,4,FV ), // #181 [ref=1x]
+ E(F20F38,00,0,0,0,1,4,FV ), // #182 [ref=1x]
+ V(660F3A,00,0,0,0,0,4,FVM), // #183 [ref=2x]
+ E(660F00,00,0,0,0,0,4,FV ), // #184 [ref=5x]
+ V(660F38,00,0,0,0,0,0,T1S), // #185 [ref=1x]
+ E(F30F38,00,0,0,0,1,0,_ ), // #186 [ref=5x]
+ V(660F38,00,0,0,0,0,1,T1S), // #187 [ref=1x]
+ V(XOP_M8,00,0,0,0,0,0,_ ), // #188 [ref=22x]
+ V(660F38,00,0,0,0,1,4,FVM), // #189 [ref=2x]
+ E(660F3A,00,0,0,0,1,4,FVM), // #190 [ref=2x]
+ E(660F38,00,0,0,0,0,0,T1S), // #191 [ref=2x]
+ E(660F38,00,0,0,0,1,1,T1S), // #192 [ref=2x]
+ V(660F38,00,0,0,0,1,4,FV ), // #193 [ref=3x]
+ E(660F38,00,0,0,1,1,4,FV ), // #194 [ref=1x]
+ V(660F3A,00,0,0,0,0,0,T1S), // #195 [ref=2x]
+ V(660F3A,00,0,0,1,1,3,T1S), // #196 [ref=2x]
+ V(660F3A,00,0,0,0,0,1,T1S), // #197 [ref=1x]
+ V(660F00,00,0,0,0,0,1,T1S), // #198 [ref=1x]
+ E(F30F38,00,0,0,0,0,2,QVM), // #199 [ref=6x]
+ E(F30F38,00,0,0,0,0,3,HVM), // #200 [ref=9x]
+ E(F30F38,00,0,0,0,0,1,OVM), // #201 [ref=3x]
+ V(660F38,00,0,0,0,0,2,QVM), // #202 [ref=4x]
+ V(660F38,00,0,0,0,0,1,OVM), // #203 [ref=2x]
+ E(660F00,00,1,0,0,0,4,FV ), // #204 [ref=1x]
+ E(660F00,00,1,0,0,1,4,FV ), // #205 [ref=1x]
+ V(F20F00,00,0,0,0,0,4,FVM), // #206 [ref=1x]
+ V(660F00,00,0,0,0,0,4,128), // #207 [ref=5x]
+ V(660F00,00,7,0,0,0,4,FVM), // #208 [ref=1x]
+ V(660F00,00,0,0,0,1,4,128), // #209 [ref=2x]
+ E(660F00,00,0,0,0,1,4,128), // #210 [ref=1x]
+ V(660F00,00,3,0,0,0,4,FVM), // #211 [ref=1x]
+ E(F30F38,00,0,0,0,0,4,FVM), // #212 [ref=1x]
+ E(F30F38,00,0,0,0,0,4,FV ), // #213 [ref=1x]
+ E(F30F38,00,0,0,0,1,4,FV ), // #214 [ref=1x]
+ E(F30F38,00,0,0,0,1,4,FVM), // #215 [ref=1x]
+ E(660F38,00,5,2,0,1,3,T1S), // #216 [ref=2x]
+ E(660F38,00,5,2,0,0,2,T1S), // #217 [ref=2x]
+ E(660F38,00,6,2,0,1,3,T1S), // #218 [ref=2x]
+ E(660F38,00,6,2,0,0,2,T1S), // #219 [ref=2x]
+ V(000F00,00,3,0,0,0,0,_ ), // #220 [ref=1x]
+ O(F30F00,00,2,0,0,0,0,_ ), // #221 [ref=1x]
+ O(F30F00,00,3,0,0,0,0,_ ), // #222 [ref=1x]
+ O(000F00,00,5,0,1,0,0,_ ), // #223 [ref=2x]
+ O(000F00,00,3,0,1,0,0,_ ), // #224 [ref=1x]
+ O(000F00,00,4,0,1,0,0,_ ), // #225 [ref=2x]
+ O(000F00,00,6,0,1,0,0,_ ) // #226 [ref=1x]
};
// ----------------------------------------------------------------------------
// ${MainOpcodeTable:End}
@@ -1839,7 +1871,7 @@ const uint32_t InstDB::_mainOpcodeTable[] = {
// ${AltOpcodeTable:Begin}
// ------------------- Automatically generated, do not edit -------------------
const uint32_t InstDB::_altOpcodeTable[] = {
- 0 , // #0 [ref=1359x]
+ 0 , // #0 [ref=1386x]
O(660F00,1B,_,_,_,_,_,_ ), // #1 [ref=1x]
O(000F00,BA,4,_,x,_,_,_ ), // #2 [ref=1x]
O(000F00,BA,7,_,x,_,_,_ ), // #3 [ref=1x]
@@ -1991,397 +2023,408 @@ const uint32_t InstDB::_altOpcodeTable[] = {
#define SINGLE_REG(VAL) InstDB::kSingleReg##VAL
const InstDB::CommonInfo InstDB::_commonInfoTable[] = {
{ 0 , 0 , 0 , CONTROL(None) , SINGLE_REG(None), 0 }, // #0 [ref=1x]
- { 0 , 341, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #1 [ref=4x]
- { 0 , 342, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #2 [ref=2x]
+ { 0 , 344, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #1 [ref=4x]
+ { 0 , 345, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #2 [ref=2x]
{ F(Lock)|F(XAcquire)|F(XRelease) , 16 , 12, CONTROL(None) , SINGLE_REG(None), 0 }, // #3 [ref=2x]
{ 0 , 151, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #4 [ref=2x]
{ F(Vec) , 70 , 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #5 [ref=54x]
{ F(Vec) , 97 , 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #6 [ref=19x]
- { F(Vec) , 222, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #7 [ref=16x]
+ { F(Vec) , 225, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #7 [ref=16x]
{ F(Vec) , 183, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #8 [ref=20x]
{ F(Lock)|F(XAcquire)|F(XRelease) , 28 , 11, CONTROL(None) , SINGLE_REG(RO) , 0 }, // #9 [ref=1x]
- { F(Vex) , 237, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #10 [ref=3x]
+ { F(Vex) , 240, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #10 [ref=3x]
{ F(Vec) , 70 , 1 , CONTROL(None) , SINGLE_REG(RO) , 0 }, // #11 [ref=12x]
- { 0 , 343, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #12 [ref=1x]
- { F(Vex) , 239, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #13 [ref=5x]
+ { 0 , 346, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #12 [ref=1x]
+ { F(Vex) , 242, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #13 [ref=5x]
{ F(Vex) , 151, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #14 [ref=12x]
- { F(Vec) , 344, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #15 [ref=4x]
- { 0 , 241, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #16 [ref=3x]
- { F(Mib) , 345, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #17 [ref=1x]
- { 0 , 346, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #18 [ref=1x]
- { 0 , 243, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #19 [ref=1x]
- { F(Mib) , 347, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #20 [ref=1x]
- { 0 , 245, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #21 [ref=1x]
+ { F(Vec) , 347, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #15 [ref=4x]
+ { 0 , 244, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #16 [ref=3x]
+ { F(Mib) , 348, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #17 [ref=1x]
+ { 0 , 349, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #18 [ref=1x]
+ { 0 , 246, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #19 [ref=1x]
+ { F(Mib) , 350, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #20 [ref=1x]
+ { 0 , 248, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #21 [ref=1x]
{ 0 , 150, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #22 [ref=35x]
- { 0 , 348, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #23 [ref=3x]
+ { 0 , 351, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #23 [ref=3x]
{ 0 , 114, 4 , CONTROL(None) , SINGLE_REG(None), 0 }, // #24 [ref=1x]
{ F(Lock)|F(XAcquire)|F(XRelease) , 114, 4 , CONTROL(None) , SINGLE_REG(None), 0 }, // #25 [ref=3x]
- { F(Rep)|F(RepIgnored) , 247, 2 , CONTROL(Call) , SINGLE_REG(None), 0 }, // #26 [ref=1x]
- { 0 , 349, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #27 [ref=1x]
- { 0 , 350, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #28 [ref=2x]
- { 0 , 324, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #29 [ref=1x]
- { 0 , 257, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #30 [ref=74x]
- { 0 , 351, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #31 [ref=24x]
- { 0 , 352, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #32 [ref=1x]
+ { F(Rep)|F(RepIgnored) , 250, 2 , CONTROL(Call) , SINGLE_REG(None), 0 }, // #26 [ref=1x]
+ { 0 , 352, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #27 [ref=1x]
+ { 0 , 353, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #28 [ref=2x]
+ { 0 , 327, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #29 [ref=1x]
+ { 0 , 260, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #30 [ref=80x]
+ { 0 , 354, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #31 [ref=24x]
+ { 0 , 355, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #32 [ref=1x]
{ 0 , 16 , 12, CONTROL(None) , SINGLE_REG(None), 0 }, // #33 [ref=1x]
- { F(Rep) , 353, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #34 [ref=1x]
- { F(Vec) , 354, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #35 [ref=2x]
- { F(Vec) , 355, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #36 [ref=3x]
+ { F(Rep) , 356, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #34 [ref=1x]
+ { F(Vec) , 357, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #35 [ref=2x]
+ { F(Vec) , 358, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #36 [ref=3x]
{ F(Lock)|F(XAcquire)|F(XRelease) , 118, 4 , CONTROL(None) , SINGLE_REG(None), 0 }, // #37 [ref=1x]
- { F(Lock)|F(XAcquire)|F(XRelease) , 356, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #38 [ref=1x]
- { F(Lock)|F(XAcquire)|F(XRelease) , 357, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #39 [ref=1x]
- { 0 , 358, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #40 [ref=1x]
- { 0 , 359, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #41 [ref=1x]
- { 0 , 249, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #42 [ref=1x]
- { F(Mmx)|F(Vec) , 360, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #43 [ref=2x]
- { F(Mmx)|F(Vec) , 361, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #44 [ref=2x]
- { F(Mmx)|F(Vec) , 362, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #45 [ref=2x]
- { F(Vec) , 363, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #46 [ref=2x]
- { F(Vec) , 364, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #47 [ref=2x]
- { F(Vec) , 365, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #48 [ref=2x]
- { 0 , 366, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #49 [ref=1x]
- { 0 , 367, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #50 [ref=2x]
- { F(Lock)|F(XAcquire)|F(XRelease) , 251, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #51 [ref=2x]
+ { F(Lock)|F(XAcquire)|F(XRelease) , 359, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #38 [ref=1x]
+ { F(Lock)|F(XAcquire)|F(XRelease) , 360, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #39 [ref=1x]
+ { 0 , 361, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #40 [ref=1x]
+ { 0 , 362, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #41 [ref=1x]
+ { 0 , 252, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #42 [ref=1x]
+ { F(Mmx)|F(Vec) , 363, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #43 [ref=2x]
+ { F(Mmx)|F(Vec) , 364, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #44 [ref=2x]
+ { F(Mmx)|F(Vec) , 365, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #45 [ref=2x]
+ { F(Vec) , 366, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #46 [ref=2x]
+ { F(Vec) , 367, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #47 [ref=2x]
+ { F(Vec) , 368, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #48 [ref=2x]
+ { 0 , 369, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #49 [ref=1x]
+ { 0 , 370, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #50 [ref=2x]
+ { F(Lock)|F(XAcquire)|F(XRelease) , 254, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #51 [ref=2x]
{ 0 , 39 , 4 , CONTROL(None) , SINGLE_REG(None), 0 }, // #52 [ref=3x]
- { F(Mmx) , 257, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #53 [ref=1x]
- { 0 , 253, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #54 [ref=2x]
- { 0 , 368, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #55 [ref=1x]
- { F(Vec) , 369, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #56 [ref=2x]
- { F(Vec) , 255, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #57 [ref=1x]
+ { F(Mmx) , 260, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #53 [ref=1x]
+ { 0 , 256, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #54 [ref=2x]
+ { 0 , 371, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #55 [ref=1x]
+ { F(Vec) , 372, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #56 [ref=2x]
+ { F(Vec) , 258, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #57 [ref=1x]
{ F(FpuM32)|F(FpuM64) , 153, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #58 [ref=6x]
- { 0 , 257, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #59 [ref=9x]
- { F(FpuM80) , 370, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #60 [ref=2x]
- { 0 , 258, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #61 [ref=13x]
- { F(FpuM32)|F(FpuM64) , 259, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #62 [ref=2x]
- { F(FpuM16)|F(FpuM32) , 371, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #63 [ref=9x]
- { F(FpuM16)|F(FpuM32)|F(FpuM64) , 372, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #64 [ref=3x]
- { F(FpuM32)|F(FpuM64)|F(FpuM80) , 373, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #65 [ref=2x]
- { F(FpuM16) , 374, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #66 [ref=3x]
- { F(FpuM16) , 375, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #67 [ref=2x]
- { F(FpuM32)|F(FpuM64) , 260, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #68 [ref=1x]
- { 0 , 376, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #69 [ref=2x]
+ { 0 , 260, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #59 [ref=9x]
+ { F(FpuM80) , 373, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #60 [ref=2x]
+ { 0 , 261, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #61 [ref=13x]
+ { F(FpuM32)|F(FpuM64) , 262, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #62 [ref=2x]
+ { F(FpuM16)|F(FpuM32) , 374, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #63 [ref=9x]
+ { F(FpuM16)|F(FpuM32)|F(FpuM64) , 375, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #64 [ref=3x]
+ { F(FpuM32)|F(FpuM64)|F(FpuM80) , 376, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #65 [ref=2x]
+ { F(FpuM16) , 377, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #66 [ref=3x]
+ { F(FpuM16) , 378, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #67 [ref=2x]
+ { F(FpuM32)|F(FpuM64) , 263, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #68 [ref=1x]
+ { 0 , 379, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #69 [ref=2x]
{ 0 , 39 , 10, CONTROL(None) , SINGLE_REG(None), 0 }, // #70 [ref=1x]
- { 0 , 377, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #71 [ref=1x]
- { F(Rep) , 378, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #72 [ref=1x]
- { F(Vec) , 261, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #73 [ref=1x]
- { 0 , 379, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #74 [ref=2x]
- { 0 , 380, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #75 [ref=8x]
- { 0 , 263, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #76 [ref=3x]
- { 0 , 265, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #77 [ref=1x]
- { 0 , 257, 1 , CONTROL(Return) , SINGLE_REG(None), 0 }, // #78 [ref=3x]
- { 0 , 381, 1 , CONTROL(Return) , SINGLE_REG(None), 0 }, // #79 [ref=1x]
- { F(Rep)|F(RepIgnored) , 267, 2 , CONTROL(Branch) , SINGLE_REG(None), 0 }, // #80 [ref=30x]
- { F(Rep)|F(RepIgnored) , 269, 2 , CONTROL(Branch) , SINGLE_REG(None), 0 }, // #81 [ref=1x]
- { F(Rep)|F(RepIgnored) , 271, 2 , CONTROL(Jump) , SINGLE_REG(None), 0 }, // #82 [ref=1x]
- { F(Vec)|F(Vex) , 382, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #83 [ref=27x]
- { F(Vec)|F(Vex) , 273, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #84 [ref=1x]
- { F(Vec)|F(Vex) , 275, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #85 [ref=1x]
- { F(Vec)|F(Vex) , 277, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #86 [ref=1x]
- { F(Vec)|F(Vex) , 279, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #87 [ref=1x]
- { F(Vec)|F(Vex) , 383, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #88 [ref=12x]
- { F(Vec)|F(Vex) , 384, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #89 [ref=8x]
- { 0 , 385, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #90 [ref=2x]
- { 0 , 281, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #91 [ref=1x]
+ { 0 , 380, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #71 [ref=1x]
+ { F(Rep) , 381, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #72 [ref=1x]
+ { F(Vec) , 264, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #73 [ref=1x]
+ { 0 , 382, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #74 [ref=2x]
+ { 0 , 383, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #75 [ref=8x]
+ { 0 , 266, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #76 [ref=3x]
+ { 0 , 268, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #77 [ref=1x]
+ { 0 , 260, 1 , CONTROL(Return) , SINGLE_REG(None), 0 }, // #78 [ref=3x]
+ { 0 , 384, 1 , CONTROL(Return) , SINGLE_REG(None), 0 }, // #79 [ref=1x]
+ { F(Rep)|F(RepIgnored) , 270, 2 , CONTROL(Branch) , SINGLE_REG(None), 0 }, // #80 [ref=30x]
+ { F(Rep)|F(RepIgnored) , 272, 2 , CONTROL(Branch) , SINGLE_REG(None), 0 }, // #81 [ref=1x]
+ { F(Rep)|F(RepIgnored) , 274, 2 , CONTROL(Jump) , SINGLE_REG(None), 0 }, // #82 [ref=1x]
+ { F(Vec)|F(Vex) , 385, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #83 [ref=27x]
+ { F(Vec)|F(Vex) , 276, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #84 [ref=1x]
+ { F(Vec)|F(Vex) , 278, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #85 [ref=1x]
+ { F(Vec)|F(Vex) , 280, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #86 [ref=1x]
+ { F(Vec)|F(Vex) , 282, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #87 [ref=1x]
+ { F(Vec)|F(Vex) , 386, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #88 [ref=12x]
+ { F(Vec)|F(Vex) , 387, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #89 [ref=8x]
+ { 0 , 388, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #90 [ref=2x]
+ { 0 , 284, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #91 [ref=1x]
{ F(Vec) , 192, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #92 [ref=2x]
- { 0 , 386, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #93 [ref=2x]
- { 0 , 283, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #94 [ref=2x]
- { 0 , 387, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #95 [ref=1x]
- { 0 , 156, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #96 [ref=3x]
- { 0 , 388, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #97 [ref=5x]
- { F(Vex) , 389, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #98 [ref=2x]
- { F(Rep) , 390, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #99 [ref=1x]
- { 0 , 269, 2 , CONTROL(Branch) , SINGLE_REG(None), 0 }, // #100 [ref=3x]
- { 0 , 285, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #101 [ref=1x]
- { F(Vex) , 391, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #102 [ref=2x]
- { F(Vec) , 392, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #103 [ref=1x]
- { F(Mmx) , 393, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #104 [ref=1x]
- { 0 , 394, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #105 [ref=2x]
- { F(XRelease) , 0 , 16, CONTROL(None) , SINGLE_REG(None), 0 }, // #106 [ref=1x]
- { F(Vec) , 70 , 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #107 [ref=6x]
- { 0 , 64 , 6 , CONTROL(None) , SINGLE_REG(None), 0 }, // #108 [ref=1x]
- { F(Mmx)|F(Vec) , 287, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #109 [ref=1x]
- { 0 , 395, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #110 [ref=1x]
- { 0 , 68 , 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #111 [ref=2x]
- { F(Mmx)|F(Vec) , 396, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #112 [ref=1x]
- { F(Vec) , 256, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #113 [ref=2x]
- { F(Vec) , 198, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #114 [ref=4x]
- { F(Vec) , 397, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #115 [ref=2x]
- { F(Vec) , 71 , 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #116 [ref=3x]
- { F(Mmx) , 398, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #117 [ref=1x]
- { F(Vec) , 98 , 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #118 [ref=1x]
- { F(Vec) , 201, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #119 [ref=1x]
- { F(Mmx)|F(Vec) , 94 , 5 , CONTROL(None) , SINGLE_REG(None), 0 }, // #120 [ref=1x]
- { F(Mmx)|F(Vec) , 399, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #121 [ref=1x]
- { F(Rep) , 400, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #122 [ref=1x]
- { F(Vec) , 97 , 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #123 [ref=1x]
- { F(Vec) , 289, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #124 [ref=1x]
- { 0 , 291, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #125 [ref=2x]
- { 0 , 293, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #126 [ref=1x]
- { F(Vex) , 295, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #127 [ref=1x]
- { 0 , 401, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #128 [ref=1x]
- { 0 , 402, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #129 [ref=1x]
- { F(Lock)|F(XAcquire)|F(XRelease) , 252, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #130 [ref=2x]
- { 0 , 297, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #131 [ref=1x]
- { F(Lock)|F(XAcquire)|F(XRelease) , 16 , 12, CONTROL(None) , SINGLE_REG(RO) , 0 }, // #132 [ref=1x]
- { 0 , 403, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #133 [ref=1x]
- { F(Rep) , 404, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #134 [ref=1x]
- { F(Mmx)|F(Vec) , 299, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #135 [ref=40x]
- { F(Mmx)|F(Vec) , 301, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #136 [ref=1x]
- { F(Mmx)|F(Vec) , 299, 2 , CONTROL(None) , SINGLE_REG(RO) , 0 }, // #137 [ref=6x]
- { F(Mmx)|F(Vec) , 299, 2 , CONTROL(None) , SINGLE_REG(WO) , 0 }, // #138 [ref=16x]
- { F(Mmx) , 299, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #139 [ref=26x]
- { F(Vec) , 70 , 1 , CONTROL(None) , SINGLE_REG(WO) , 0 }, // #140 [ref=4x]
- { F(Vec) , 405, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #141 [ref=1x]
- { F(Vec) , 406, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #142 [ref=1x]
- { F(Vec) , 407, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #143 [ref=1x]
- { F(Vec) , 408, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #144 [ref=1x]
- { F(Vec) , 409, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #145 [ref=1x]
- { F(Vec) , 410, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #146 [ref=1x]
- { F(Mmx)|F(Vec) , 303, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #147 [ref=1x]
- { F(Vec) , 411, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #148 [ref=1x]
- { F(Vec) , 412, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #149 [ref=1x]
- { F(Vec) , 413, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #150 [ref=1x]
- { F(Mmx)|F(Vec) , 414, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #151 [ref=1x]
- { F(Mmx)|F(Vec) , 415, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #152 [ref=1x]
- { F(Vec) , 225, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #153 [ref=2x]
- { 0 , 122, 4 , CONTROL(None) , SINGLE_REG(None), 0 }, // #154 [ref=1x]
- { 0 , 381, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #155 [ref=6x]
- { F(Mmx) , 301, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #156 [ref=1x]
- { F(Mmx)|F(Vec) , 305, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #157 [ref=8x]
- { F(Vec) , 416, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #158 [ref=2x]
- { 0 , 126, 4 , CONTROL(None) , SINGLE_REG(None), 0 }, // #159 [ref=1x]
- { 0 , 417, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #160 [ref=8x]
- { 0 , 418, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #161 [ref=4x]
- { 0 , 419, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #162 [ref=6x]
- { 0 , 307, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #163 [ref=1x]
- { F(Rep)|F(RepIgnored) , 309, 2 , CONTROL(Return) , SINGLE_REG(None), 0 }, // #164 [ref=1x]
- { F(Vex) , 311, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #165 [ref=1x]
- { F(Lock)|F(XAcquire)|F(XRelease) , 16 , 12, CONTROL(None) , SINGLE_REG(WO) , 0 }, // #166 [ref=3x]
- { F(Rep) , 420, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #167 [ref=1x]
- { 0 , 421, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #168 [ref=30x]
- { 0 , 159, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #169 [ref=2x]
- { 0 , 422, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #170 [ref=3x]
- { F(Rep) , 423, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #171 [ref=1x]
- { 0 , 57 , 7 , CONTROL(None) , SINGLE_REG(None), 0 }, // #172 [ref=1x]
- { F(Vec)|F(Evex)|F(Avx512T4X)|F(Avx512KZ) , 424, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #173 [ref=4x]
- { F(Vec)|F(Evex)|F(Avx512T4X)|F(Avx512KZ) , 425, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #174 [ref=2x]
- { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_ER_SAE_B64) , 162, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #175 [ref=22x]
- { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_ER_SAE_B32) , 162, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #176 [ref=22x]
- { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_ER_SAE) , 426, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #177 [ref=18x]
- { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_ER_SAE) , 427, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #178 [ref=17x]
- { F(Vec)|F(Vex) , 162, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #179 [ref=15x]
- { F(Vec)|F(Vex)|F(Evex) , 162, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #180 [ref=5x]
- { F(Vec)|F(Vex) , 70 , 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #181 [ref=17x]
- { F(Vec)|F(Vex) , 183, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #182 [ref=1x]
- { F(Vec)|F(Evex)|F(Avx512KZ_B32) , 165, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #183 [ref=4x]
- { F(Vec)|F(Evex)|F(Avx512KZ_B64) , 165, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #184 [ref=4x]
- { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_B64) , 162, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #185 [ref=10x]
- { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_B32) , 162, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #186 [ref=12x]
- { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_B64) , 162, 3 , CONTROL(None) , SINGLE_REG(RO) , 0 }, // #187 [ref=2x]
- { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_B32) , 162, 3 , CONTROL(None) , SINGLE_REG(RO) , 0 }, // #188 [ref=6x]
- { F(Vec)|F(Evex)|F(Avx512KZ) , 162, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #189 [ref=13x]
- { F(Vec)|F(Evex)|F(Avx512KZ_B32) , 162, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #190 [ref=16x]
- { F(Vec)|F(Evex)|F(Avx512KZ_B64) , 162, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #191 [ref=19x]
- { F(Vec)|F(Vex) , 165, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #192 [ref=6x]
- { F(Vec)|F(Vex) , 313, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #193 [ref=3x]
- { F(Vec)|F(Vex) , 428, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #194 [ref=2x]
- { F(Vec)|F(Evex)|F(Avx512KZ) , 429, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #195 [ref=1x]
- { F(Vec)|F(Evex)|F(Avx512KZ) , 430, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #196 [ref=4x]
- { F(Vec)|F(Evex)|F(Avx512KZ) , 431, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #197 [ref=4x]
- { F(Vec)|F(Evex)|F(Avx512KZ) , 432, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #198 [ref=1x]
- { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 429, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #199 [ref=1x]
- { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 433, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #200 [ref=1x]
- { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_SAE_B64) , 168, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #201 [ref=1x]
- { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_SAE_B32) , 168, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #202 [ref=1x]
- { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_SAE) , 434, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #203 [ref=1x]
- { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_SAE) , 435, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #204 [ref=1x]
- { F(Vec)|F(Vex)|F(Evex)|F(Avx512SAE) , 97 , 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #205 [ref=2x]
- { F(Vec)|F(Vex)|F(Evex)|F(Avx512SAE) , 222, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #206 [ref=2x]
- { F(Vec)|F(Evex)|F(Avx512KZ) , 171, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #207 [ref=6x]
- { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_B32) , 174, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #208 [ref=1x]
- { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_ER_SAE_B32) , 177, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #209 [ref=3x]
- { F(Vec)|F(Evex)|F(Avx512KZ_B32) , 315, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #210 [ref=1x]
- { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_ER_SAE_B64) , 315, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #211 [ref=2x]
- { F(Vec)|F(Evex)|F(Avx512KZ_ER_SAE_B64) , 177, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #212 [ref=4x]
- { F(Vec)|F(Evex)|F(Avx512KZ_ER_SAE_B64) , 315, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #213 [ref=3x]
- { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_SAE) , 174, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #214 [ref=1x]
- { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_ER_SAE_B32) , 174, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #215 [ref=1x]
- { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_SAE) , 180, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #216 [ref=1x]
- { F(Vec)|F(Evex)|F(Avx512KZ_ER_SAE_B32) , 174, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #217 [ref=2x]
- { F(Vec)|F(Evex)|F(Avx512KZ_ER_SAE_B32) , 177, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #218 [ref=2x]
- { F(Vec)|F(Vex)|F(Evex)|F(Avx512ER_SAE) , 363, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #219 [ref=1x]
- { F(Vec)|F(Evex)|F(Avx512ER_SAE) , 363, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #220 [ref=1x]
- { F(Vec)|F(Vex)|F(Evex)|F(Avx512ER_SAE) , 436, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #221 [ref=2x]
- { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_SAE) , 427, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #222 [ref=3x]
- { F(Vec)|F(Vex)|F(Evex)|F(Avx512ER_SAE) , 365, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #223 [ref=1x]
- { F(Vec)|F(Evex)|F(Avx512ER_SAE) , 365, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #224 [ref=1x]
- { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_SAE_B64) , 315, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #225 [ref=1x]
- { F(Vec)|F(Evex)|F(Avx512KZ_SAE_B64) , 177, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #226 [ref=3x]
- { F(Vec)|F(Evex)|F(Avx512KZ_SAE_B64) , 315, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #227 [ref=1x]
- { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_SAE_B32) , 177, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #228 [ref=1x]
- { F(Vec)|F(Evex)|F(Avx512KZ_SAE_B32) , 174, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #229 [ref=2x]
- { F(Vec)|F(Evex)|F(Avx512KZ_SAE_B32) , 177, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #230 [ref=2x]
- { F(Vec)|F(Vex)|F(Evex)|F(Avx512SAE) , 363, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #231 [ref=1x]
- { F(Vec)|F(Evex)|F(Avx512SAE) , 363, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #232 [ref=1x]
- { F(Vec)|F(Vex)|F(Evex)|F(Avx512SAE) , 365, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #233 [ref=1x]
- { F(Vec)|F(Evex)|F(Avx512SAE) , 365, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #234 [ref=1x]
- { F(Vec)|F(Evex)|F(Avx512KZ_B32) , 174, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #235 [ref=1x]
- { F(Vec)|F(Evex)|F(Avx512ER_SAE) , 436, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #236 [ref=2x]
- { F(Vec)|F(Evex)|F(Avx512KZ) , 165, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #237 [ref=3x]
- { F(Vec)|F(Vex) , 165, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #238 [ref=9x]
- { F(Vec)|F(Evex)|F(Avx512KZ_SAE_B64) , 74 , 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #239 [ref=3x]
- { F(Vec)|F(Evex)|F(Avx512KZ_SAE_B32) , 74 , 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #240 [ref=3x]
- { F(Vec)|F(Evex)|F(Avx512KZ) , 177, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #241 [ref=9x]
- { F(Vec)|F(Vex) , 181, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #242 [ref=2x]
- { F(Vec)|F(Evex)|F(Avx512KZ) , 437, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #243 [ref=4x]
- { F(Vec)|F(Evex)|F(Avx512KZ) , 182, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #244 [ref=4x]
- { F(Vec)|F(Vex)|F(Evex) , 369, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #245 [ref=2x]
- { F(Vec)|F(Evex)|F(Avx512KZ_SAE_B64) , 165, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #246 [ref=2x]
- { F(Vec)|F(Evex)|F(Avx512KZ_SAE_B32) , 165, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #247 [ref=2x]
- { F(Vec)|F(Evex)|F(Avx512KZ_SAE) , 438, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #248 [ref=4x]
- { F(Vec)|F(Evex)|F(Avx512KZ_SAE) , 439, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #249 [ref=4x]
- { F(Vec)|F(Vex) , 130, 4 , CONTROL(None) , SINGLE_REG(None), 0 }, // #250 [ref=13x]
- { F(Vec)|F(Vex) , 317, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #251 [ref=4x]
- { F(Vec)|F(Vex) , 319, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #252 [ref=4x]
- { F(Vec)|F(Evex)|F(Avx512K_B64) , 440, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #253 [ref=1x]
- { F(Vec)|F(Evex)|F(Avx512K_B32) , 440, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #254 [ref=1x]
- { F(Vec)|F(Evex)|F(Avx512K) , 441, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #255 [ref=1x]
- { F(Vec)|F(Evex)|F(Avx512K) , 442, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #256 [ref=1x]
- { F(Vec)|F(Vex) , 177, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #257 [ref=7x]
- { F(Vec)|F(Vex) , 97 , 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #258 [ref=1x]
- { F(Vec)|F(Vex) , 222, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #259 [ref=1x]
- { F(Vec)|F(Vsib)|F(Vex)|F(Evex)|F(Avx512K) , 99 , 5 , CONTROL(None) , SINGLE_REG(None), 0 }, // #260 [ref=2x]
- { F(Vec)|F(Vsib)|F(Vex)|F(Evex)|F(Avx512K) , 104, 5 , CONTROL(None) , SINGLE_REG(None), 0 }, // #261 [ref=2x]
- { F(Vsib)|F(Evex)|F(Avx512K) , 443, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #262 [ref=4x]
- { F(Vsib)|F(Evex)|F(Avx512K) , 444, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #263 [ref=4x]
- { F(Vsib)|F(Evex)|F(Avx512K) , 445, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #264 [ref=8x]
- { F(Vec)|F(Vsib)|F(Vex)|F(Evex)|F(Avx512K) , 109, 5 , CONTROL(None) , SINGLE_REG(None), 0 }, // #265 [ref=2x]
- { F(Vec)|F(Vsib)|F(Vex)|F(Evex)|F(Avx512K) , 134, 4 , CONTROL(None) , SINGLE_REG(None), 0 }, // #266 [ref=2x]
- { F(Vec)|F(Evex)|F(Avx512KZ_SAE) , 426, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #267 [ref=3x]
- { F(Vec)|F(Evex)|F(Avx512KZ_SAE) , 427, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #268 [ref=3x]
- { F(Vec)|F(Evex)|F(Avx512KZ_SAE_B64) , 183, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #269 [ref=2x]
- { F(Vec)|F(Evex)|F(Avx512KZ_SAE_B32) , 183, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #270 [ref=2x]
- { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 165, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #271 [ref=3x]
- { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 162, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #272 [ref=22x]
- { F(Vec)|F(Vex) , 321, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #273 [ref=2x]
- { F(Vec)|F(Evex)|F(Avx512KZ) , 321, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #274 [ref=4x]
- { F(Vec)|F(Evex)|F(Avx512KZ) , 446, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #275 [ref=4x]
- { F(Vec)|F(Vex)|F(Evex) , 439, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #276 [ref=1x]
- { F(Vec)|F(Vex) , 192, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #277 [ref=1x]
- { F(Vex) , 386, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #278 [ref=2x]
- { F(Vec)|F(Vex) , 392, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #279 [ref=1x]
- { F(Vec)|F(Vex) , 138, 4 , CONTROL(None) , SINGLE_REG(None), 0 }, // #280 [ref=4x]
- { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_SAE_B64) , 162, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #281 [ref=2x]
- { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_SAE_B32) , 162, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #282 [ref=2x]
- { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_SAE) , 426, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #283 [ref=2x]
- { 0 , 447, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #284 [ref=4x]
- { 0 , 323, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #285 [ref=3x]
- { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 70 , 6 , CONTROL(None) , SINGLE_REG(None), 0 }, // #286 [ref=4x]
- { F(Vec)|F(Vex)|F(Evex) , 325, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #287 [ref=1x]
- { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 186, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #288 [ref=1x]
- { F(Vec)|F(Vex) , 70 , 4 , CONTROL(None) , SINGLE_REG(None), 0 }, // #289 [ref=2x]
- { F(Vec)|F(Evex)|F(Avx512KZ) , 70 , 6 , CONTROL(None) , SINGLE_REG(None), 0 }, // #290 [ref=6x]
- { F(Vec)|F(Vex)|F(Evex) , 200, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #291 [ref=2x]
- { F(Vec)|F(Vex)|F(Evex) , 327, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #292 [ref=4x]
- { F(Vec)|F(Vex) , 448, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #293 [ref=3x]
- { F(Vec)|F(Vex)|F(Evex) , 189, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #294 [ref=3x]
- { F(Vec)|F(Vex)|F(Evex) , 192, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #295 [ref=1x]
- { F(Vec)|F(Vex)|F(Evex) , 195, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #296 [ref=1x]
- { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 198, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #297 [ref=1x]
- { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 177, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #298 [ref=5x]
- { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 201, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #299 [ref=1x]
- { 0 , 329, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #300 [ref=1x]
- { 0 , 331, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #301 [ref=1x]
- { F(Vec)|F(Vex) , 162, 2 , CONTROL(None) , SINGLE_REG(RO) , 0 }, // #302 [ref=2x]
- { F(Vec)|F(Evex)|F(Avx512KZ_B32) , 162, 3 , CONTROL(None) , SINGLE_REG(RO) , 0 }, // #303 [ref=2x]
- { F(Vec)|F(Vex) , 162, 2 , CONTROL(None) , SINGLE_REG(WO) , 0 }, // #304 [ref=2x]
- { F(Vec)|F(Evex)|F(Avx512KZ_B32) , 162, 3 , CONTROL(None) , SINGLE_REG(WO) , 0 }, // #305 [ref=2x]
- { F(Vec)|F(Evex)|F(Avx512KZ_B64) , 162, 3 , CONTROL(None) , SINGLE_REG(WO) , 0 }, // #306 [ref=2x]
- { F(Vec)|F(Evex)|F(Avx512KZ_B64) , 162, 3 , CONTROL(None) , SINGLE_REG(RO) , 0 }, // #307 [ref=2x]
- { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 449, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #308 [ref=1x]
- { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 450, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #309 [ref=1x]
- { F(Vec)|F(Evex) , 451, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #310 [ref=6x]
- { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 204, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #311 [ref=1x]
- { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 452, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #312 [ref=1x]
- { F(Vec)|F(Vex)|F(Evex) , 165, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #313 [ref=1x]
- { F(Vec)|F(Evex)|F(Avx512K) , 207, 3 , CONTROL(None) , SINGLE_REG(WO) , 0 }, // #314 [ref=2x]
- { F(Vec)|F(Evex)|F(Avx512K_B32) , 207, 3 , CONTROL(None) , SINGLE_REG(WO) , 0 }, // #315 [ref=2x]
- { F(Vec)|F(Vex)|F(Evex)|F(Avx512K) , 210, 3 , CONTROL(None) , SINGLE_REG(WO) , 0 }, // #316 [ref=4x]
- { F(Vec)|F(Vex)|F(Evex)|F(Avx512K_B32) , 210, 3 , CONTROL(None) , SINGLE_REG(WO) , 0 }, // #317 [ref=2x]
- { F(Vec)|F(Vex)|F(Evex)|F(Avx512K_B64) , 210, 3 , CONTROL(None) , SINGLE_REG(WO) , 0 }, // #318 [ref=2x]
- { F(Vec)|F(Vex) , 405, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #319 [ref=1x]
- { F(Vec)|F(Vex) , 406, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #320 [ref=1x]
- { F(Vec)|F(Vex) , 407, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #321 [ref=1x]
- { F(Vec)|F(Vex) , 408, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #322 [ref=1x]
- { F(Vec)|F(Evex)|F(Avx512K_B64) , 207, 3 , CONTROL(None) , SINGLE_REG(WO) , 0 }, // #323 [ref=4x]
- { F(Vec)|F(Evex)|F(Avx512KZ_B32) , 177, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #324 [ref=6x]
- { F(Vec)|F(Vex) , 166, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #325 [ref=2x]
- { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_B32) , 163, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #326 [ref=2x]
- { F(Vec)|F(Vex) , 142, 4 , CONTROL(None) , SINGLE_REG(None), 0 }, // #327 [ref=2x]
- { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_B64) , 76 , 6 , CONTROL(None) , SINGLE_REG(None), 0 }, // #328 [ref=2x]
- { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_B64) , 146, 4 , CONTROL(None) , SINGLE_REG(None), 0 }, // #329 [ref=2x]
- { F(Vec)|F(Vex)|F(Evex) , 409, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #330 [ref=1x]
- { F(Vec)|F(Vex)|F(Evex) , 410, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #331 [ref=1x]
- { F(Vec)|F(Vex)|F(Evex) , 453, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #332 [ref=1x]
- { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 454, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #333 [ref=1x]
- { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 455, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #334 [ref=1x]
- { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 456, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #335 [ref=1x]
- { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 457, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #336 [ref=1x]
- { F(Vec)|F(Evex)|F(Avx512KZ_B64) , 177, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #337 [ref=4x]
- { F(Vec)|F(Vex) , 313, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #338 [ref=12x]
- { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 162, 3 , CONTROL(None) , SINGLE_REG(RO) , 0 }, // #339 [ref=8x]
- { F(Vec)|F(Evex) , 458, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #340 [ref=4x]
- { F(Vec)|F(Evex)|F(Avx512KZ) , 213, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #341 [ref=6x]
- { F(Vec)|F(Evex)|F(Avx512KZ) , 216, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #342 [ref=9x]
- { F(Vec)|F(Evex)|F(Avx512KZ) , 219, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #343 [ref=3x]
- { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 222, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #344 [ref=4x]
- { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 225, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #345 [ref=2x]
- { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 174, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #346 [ref=6x]
- { F(Vec)|F(Vex) , 130, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #347 [ref=1x]
- { F(Vec)|F(Evex)|F(Avx512KZ_B32) , 183, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #348 [ref=3x]
- { F(Vec)|F(Evex)|F(Avx512KZ_B64) , 183, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #349 [ref=3x]
- { F(Vec)|F(Vex) , 333, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #350 [ref=4x]
- { F(Vec)|F(Vsib)|F(Evex)|F(Avx512K) , 228, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #351 [ref=3x]
- { F(Vec)|F(Vsib)|F(Evex)|F(Avx512K) , 335, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #352 [ref=2x]
- { F(Vec)|F(Vsib)|F(Evex)|F(Avx512K) , 231, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #353 [ref=2x]
- { F(Vec)|F(Vex) , 337, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #354 [ref=8x]
- { F(Vec)|F(Evex)|F(Avx512K) , 234, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #355 [ref=5x]
- { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_B32) , 183, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #356 [ref=1x]
- { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 183, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #357 [ref=2x]
- { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_B32) , 82 , 6 , CONTROL(None) , SINGLE_REG(None), 0 }, // #358 [ref=3x]
- { F(Vec)|F(Vex)|F(Evex) , 183, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #359 [ref=2x]
- { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_B64) , 82 , 6 , CONTROL(None) , SINGLE_REG(None), 0 }, // #360 [ref=2x]
- { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 82 , 6 , CONTROL(None) , SINGLE_REG(None), 0 }, // #361 [ref=3x]
- { F(Vec)|F(Evex)|F(Avx512KZ_B64) , 88 , 6 , CONTROL(None) , SINGLE_REG(None), 0 }, // #362 [ref=1x]
- { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 162, 3 , CONTROL(None) , SINGLE_REG(WO) , 0 }, // #363 [ref=6x]
- { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_B32) , 162, 3 , CONTROL(None) , SINGLE_REG(WO) , 0 }, // #364 [ref=2x]
- { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_B64) , 162, 3 , CONTROL(None) , SINGLE_REG(WO) , 0 }, // #365 [ref=2x]
- { F(Vec)|F(Evex)|F(Avx512K_B32) , 234, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #366 [ref=2x]
- { F(Vec)|F(Evex)|F(Avx512K_B64) , 234, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #367 [ref=2x]
- { F(Vec)|F(Evex)|F(Avx512KZ) , 426, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #368 [ref=2x]
- { F(Vec)|F(Evex)|F(Avx512KZ) , 427, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #369 [ref=2x]
- { F(Vec)|F(Vex) , 427, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #370 [ref=2x]
- { F(Vec)|F(Evex)|F(Avx512KZ) , 438, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #371 [ref=1x]
- { F(Vec)|F(Evex)|F(Avx512KZ) , 439, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #372 [ref=1x]
- { F(Vec)|F(Vex) , 183, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #373 [ref=2x]
- { F(Vec)|F(Vex) , 438, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #374 [ref=1x]
- { F(Vec)|F(Vex) , 439, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #375 [ref=1x]
- { F(Vec)|F(Evex)|F(Avx512KZ_ER_SAE_B64) , 162, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #376 [ref=1x]
- { F(Vec)|F(Evex)|F(Avx512KZ_ER_SAE_B32) , 162, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #377 [ref=1x]
- { F(Vec)|F(Evex)|F(Avx512KZ_ER_SAE) , 426, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #378 [ref=1x]
- { F(Vec)|F(Evex)|F(Avx512KZ_ER_SAE) , 427, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #379 [ref=1x]
- { F(Vec)|F(Vsib)|F(Evex)|F(Avx512K) , 339, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #380 [ref=1x]
- { F(Vec)|F(Evex)|F(Avx512KZ_B32) , 166, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #381 [ref=2x]
- { F(Vec)|F(Evex)|F(Avx512KZ_B64) , 166, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #382 [ref=2x]
- { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_B32) , 165, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #383 [ref=1x]
- { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_B64) , 165, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #384 [ref=1x]
- { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_ER_SAE_B64) , 177, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #385 [ref=1x]
- { F(Vec)|F(Vex) , 257, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #386 [ref=2x]
- { F(Lock)|F(XAcquire)|F(XRelease) , 49 , 4 , CONTROL(None) , SINGLE_REG(None), 0 }, // #387 [ref=1x]
- { 0 , 459, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #388 [ref=1x]
- { F(Lock)|F(XAcquire) , 49 , 8 , CONTROL(None) , SINGLE_REG(RO) , 0 }, // #389 [ref=1x]
- { 0 , 460, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #390 [ref=6x]
- { 0 , 461, 1 , CONTROL(None) , SINGLE_REG(None), 0 } // #391 [ref=6x]
+ { 0 , 389, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #93 [ref=2x]
+ { 0 , 286, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #94 [ref=2x]
+ { F(Vex) , 390, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #95 [ref=2x]
+ { 0 , 391, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #96 [ref=1x]
+ { 0 , 156, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #97 [ref=3x]
+ { 0 , 392, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #98 [ref=5x]
+ { F(Vex) , 393, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #99 [ref=2x]
+ { F(Rep) , 394, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #100 [ref=1x]
+ { 0 , 272, 2 , CONTROL(Branch) , SINGLE_REG(None), 0 }, // #101 [ref=3x]
+ { 0 , 288, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #102 [ref=1x]
+ { F(Vex) , 395, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #103 [ref=2x]
+ { F(Vec) , 396, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #104 [ref=1x]
+ { F(Mmx) , 397, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #105 [ref=1x]
+ { 0 , 398, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #106 [ref=2x]
+ { F(XRelease) , 0 , 16, CONTROL(None) , SINGLE_REG(None), 0 }, // #107 [ref=1x]
+ { F(Vec) , 70 , 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #108 [ref=6x]
+ { 0 , 64 , 6 , CONTROL(None) , SINGLE_REG(None), 0 }, // #109 [ref=1x]
+ { F(Mmx)|F(Vec) , 290, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #110 [ref=1x]
+ { 0 , 399, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #111 [ref=1x]
+ { 0 , 68 , 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #112 [ref=2x]
+ { F(Mmx)|F(Vec) , 400, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #113 [ref=1x]
+ { F(Vec) , 259, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #114 [ref=2x]
+ { F(Vec) , 198, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #115 [ref=4x]
+ { F(Vec) , 401, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #116 [ref=2x]
+ { F(Vec) , 71 , 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #117 [ref=3x]
+ { F(Mmx) , 402, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #118 [ref=1x]
+ { F(Vec) , 98 , 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #119 [ref=1x]
+ { F(Vec) , 201, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #120 [ref=1x]
+ { F(Mmx)|F(Vec) , 94 , 5 , CONTROL(None) , SINGLE_REG(None), 0 }, // #121 [ref=1x]
+ { F(Mmx)|F(Vec) , 403, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #122 [ref=1x]
+ { F(Rep) , 404, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #123 [ref=1x]
+ { F(Vec) , 97 , 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #124 [ref=1x]
+ { F(Vec) , 292, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #125 [ref=1x]
+ { 0 , 294, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #126 [ref=2x]
+ { 0 , 296, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #127 [ref=1x]
+ { F(Vex) , 298, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #128 [ref=1x]
+ { 0 , 405, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #129 [ref=1x]
+ { 0 , 406, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #130 [ref=1x]
+ { F(Lock)|F(XAcquire)|F(XRelease) , 255, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #131 [ref=2x]
+ { 0 , 300, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #132 [ref=1x]
+ { F(Lock)|F(XAcquire)|F(XRelease) , 16 , 12, CONTROL(None) , SINGLE_REG(RO) , 0 }, // #133 [ref=1x]
+ { 0 , 407, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #134 [ref=1x]
+ { F(Rep) , 408, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #135 [ref=1x]
+ { F(Mmx)|F(Vec) , 302, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #136 [ref=40x]
+ { F(Mmx)|F(Vec) , 304, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #137 [ref=1x]
+ { F(Mmx)|F(Vec) , 302, 2 , CONTROL(None) , SINGLE_REG(RO) , 0 }, // #138 [ref=6x]
+ { F(Mmx)|F(Vec) , 302, 2 , CONTROL(None) , SINGLE_REG(WO) , 0 }, // #139 [ref=16x]
+ { F(Mmx) , 302, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #140 [ref=26x]
+ { F(Vec) , 70 , 1 , CONTROL(None) , SINGLE_REG(WO) , 0 }, // #141 [ref=4x]
+ { F(Vec) , 409, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #142 [ref=1x]
+ { F(Vec) , 410, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #143 [ref=1x]
+ { F(Vec) , 411, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #144 [ref=1x]
+ { F(Vec) , 412, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #145 [ref=1x]
+ { F(Vec) , 413, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #146 [ref=1x]
+ { F(Vec) , 414, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #147 [ref=1x]
+ { F(Mmx)|F(Vec) , 306, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #148 [ref=1x]
+ { F(Vec) , 415, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #149 [ref=1x]
+ { F(Vec) , 416, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #150 [ref=1x]
+ { F(Vec) , 417, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #151 [ref=1x]
+ { F(Mmx)|F(Vec) , 418, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #152 [ref=1x]
+ { F(Mmx)|F(Vec) , 419, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #153 [ref=1x]
+ { F(Vec) , 228, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #154 [ref=2x]
+ { 0 , 122, 4 , CONTROL(None) , SINGLE_REG(None), 0 }, // #155 [ref=1x]
+ { 0 , 384, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #156 [ref=9x]
+ { F(Mmx) , 304, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #157 [ref=1x]
+ { F(Mmx)|F(Vec) , 308, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #158 [ref=8x]
+ { F(Vec) , 420, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #159 [ref=2x]
+ { 0 , 126, 4 , CONTROL(None) , SINGLE_REG(None), 0 }, // #160 [ref=1x]
+ { 0 , 421, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #161 [ref=8x]
+ { 0 , 422, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #162 [ref=4x]
+ { 0 , 423, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #163 [ref=6x]
+ { 0 , 310, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #164 [ref=1x]
+ { 0 , 424, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #165 [ref=1x]
+ { F(Rep)|F(RepIgnored) , 312, 2 , CONTROL(Return) , SINGLE_REG(None), 0 }, // #166 [ref=1x]
+ { F(Vex) , 314, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #167 [ref=1x]
+ { F(Lock)|F(XAcquire)|F(XRelease) , 16 , 12, CONTROL(None) , SINGLE_REG(WO) , 0 }, // #168 [ref=3x]
+ { F(Rep) , 425, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #169 [ref=1x]
+ { 0 , 426, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #170 [ref=30x]
+ { 0 , 159, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #171 [ref=2x]
+ { 0 , 427, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #172 [ref=3x]
+ { F(Rep) , 428, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #173 [ref=1x]
+ { F(Vex) , 429, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #174 [ref=5x]
+ { 0 , 57 , 7 , CONTROL(None) , SINGLE_REG(None), 0 }, // #175 [ref=1x]
+ { F(Tsib)|F(Vex) , 430, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #176 [ref=2x]
+ { F(Vex) , 384, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #177 [ref=1x]
+ { F(Tsib)|F(Vex) , 431, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #178 [ref=1x]
+ { F(Vex) , 432, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #179 [ref=1x]
+ { 0 , 433, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #180 [ref=2x]
+ { 0 , 434, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #181 [ref=1x]
+ { F(Vec)|F(Evex)|F(Avx512T4X)|F(Avx512KZ) , 435, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #182 [ref=4x]
+ { F(Vec)|F(Evex)|F(Avx512T4X)|F(Avx512KZ) , 436, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #183 [ref=2x]
+ { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_ER_SAE_B64) , 162, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #184 [ref=22x]
+ { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_ER_SAE_B32) , 162, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #185 [ref=22x]
+ { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_ER_SAE) , 437, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #186 [ref=18x]
+ { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_ER_SAE) , 438, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #187 [ref=17x]
+ { F(Vec)|F(Vex) , 162, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #188 [ref=15x]
+ { F(Vec)|F(Vex)|F(Evex) , 162, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #189 [ref=5x]
+ { F(Vec)|F(Vex) , 70 , 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #190 [ref=17x]
+ { F(Vec)|F(Vex) , 183, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #191 [ref=1x]
+ { F(Vec)|F(Evex)|F(Avx512KZ_B32) , 165, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #192 [ref=4x]
+ { F(Vec)|F(Evex)|F(Avx512KZ_B64) , 165, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #193 [ref=4x]
+ { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_B64) , 162, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #194 [ref=10x]
+ { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_B32) , 162, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #195 [ref=12x]
+ { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_B64) , 162, 3 , CONTROL(None) , SINGLE_REG(RO) , 0 }, // #196 [ref=2x]
+ { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_B32) , 162, 3 , CONTROL(None) , SINGLE_REG(RO) , 0 }, // #197 [ref=6x]
+ { F(Vec)|F(Evex)|F(Avx512KZ) , 162, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #198 [ref=13x]
+ { F(Vec)|F(Evex)|F(Avx512KZ_B32) , 162, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #199 [ref=16x]
+ { F(Vec)|F(Evex)|F(Avx512KZ_B64) , 162, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #200 [ref=19x]
+ { F(Vec)|F(Vex) , 165, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #201 [ref=6x]
+ { F(Vec)|F(Vex) , 316, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #202 [ref=3x]
+ { F(Vec)|F(Vex) , 439, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #203 [ref=2x]
+ { F(Vec)|F(Evex)|F(Avx512KZ) , 440, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #204 [ref=1x]
+ { F(Vec)|F(Evex)|F(Avx512KZ) , 441, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #205 [ref=4x]
+ { F(Vec)|F(Evex)|F(Avx512KZ) , 442, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #206 [ref=4x]
+ { F(Vec)|F(Evex)|F(Avx512KZ) , 443, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #207 [ref=1x]
+ { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 440, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #208 [ref=1x]
+ { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 444, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #209 [ref=1x]
+ { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_SAE_B64) , 168, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #210 [ref=1x]
+ { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_SAE_B32) , 168, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #211 [ref=1x]
+ { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_SAE) , 445, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #212 [ref=1x]
+ { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_SAE) , 446, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #213 [ref=1x]
+ { F(Vec)|F(Vex)|F(Evex)|F(Avx512SAE) , 97 , 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #214 [ref=2x]
+ { F(Vec)|F(Vex)|F(Evex)|F(Avx512SAE) , 225, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #215 [ref=2x]
+ { F(Vec)|F(Evex)|F(Avx512KZ) , 171, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #216 [ref=6x]
+ { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_B32) , 174, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #217 [ref=1x]
+ { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_ER_SAE_B32) , 177, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #218 [ref=3x]
+ { F(Vec)|F(Evex)|F(Avx512KZ_B32) , 318, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #219 [ref=1x]
+ { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_ER_SAE_B64) , 318, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #220 [ref=2x]
+ { F(Vec)|F(Evex)|F(Avx512KZ_ER_SAE_B64) , 177, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #221 [ref=4x]
+ { F(Vec)|F(Evex)|F(Avx512KZ_ER_SAE_B64) , 318, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #222 [ref=3x]
+ { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_SAE) , 174, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #223 [ref=1x]
+ { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_ER_SAE_B32) , 174, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #224 [ref=1x]
+ { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_SAE) , 180, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #225 [ref=1x]
+ { F(Vec)|F(Evex)|F(Avx512KZ_ER_SAE_B32) , 174, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #226 [ref=2x]
+ { F(Vec)|F(Evex)|F(Avx512KZ_ER_SAE_B32) , 177, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #227 [ref=2x]
+ { F(Vec)|F(Vex)|F(Evex)|F(Avx512ER_SAE) , 366, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #228 [ref=1x]
+ { F(Vec)|F(Evex)|F(Avx512ER_SAE) , 366, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #229 [ref=1x]
+ { F(Vec)|F(Vex)|F(Evex)|F(Avx512ER_SAE) , 447, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #230 [ref=2x]
+ { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_SAE) , 438, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #231 [ref=3x]
+ { F(Vec)|F(Vex)|F(Evex)|F(Avx512ER_SAE) , 368, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #232 [ref=1x]
+ { F(Vec)|F(Evex)|F(Avx512ER_SAE) , 368, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #233 [ref=1x]
+ { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_SAE_B64) , 318, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #234 [ref=1x]
+ { F(Vec)|F(Evex)|F(Avx512KZ_SAE_B64) , 177, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #235 [ref=3x]
+ { F(Vec)|F(Evex)|F(Avx512KZ_SAE_B64) , 318, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #236 [ref=1x]
+ { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_SAE_B32) , 177, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #237 [ref=1x]
+ { F(Vec)|F(Evex)|F(Avx512KZ_SAE_B32) , 174, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #238 [ref=2x]
+ { F(Vec)|F(Evex)|F(Avx512KZ_SAE_B32) , 177, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #239 [ref=2x]
+ { F(Vec)|F(Vex)|F(Evex)|F(Avx512SAE) , 366, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #240 [ref=1x]
+ { F(Vec)|F(Evex)|F(Avx512SAE) , 366, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #241 [ref=1x]
+ { F(Vec)|F(Vex)|F(Evex)|F(Avx512SAE) , 368, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #242 [ref=1x]
+ { F(Vec)|F(Evex)|F(Avx512SAE) , 368, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #243 [ref=1x]
+ { F(Vec)|F(Evex)|F(Avx512KZ_B32) , 174, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #244 [ref=1x]
+ { F(Vec)|F(Evex)|F(Avx512ER_SAE) , 447, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #245 [ref=2x]
+ { F(Vec)|F(Evex)|F(Avx512KZ) , 165, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #246 [ref=3x]
+ { F(Vec)|F(Vex) , 165, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #247 [ref=9x]
+ { F(Vec)|F(Evex)|F(Avx512KZ_SAE_B64) , 74 , 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #248 [ref=3x]
+ { F(Vec)|F(Evex)|F(Avx512KZ_SAE_B32) , 74 , 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #249 [ref=3x]
+ { F(Vec)|F(Evex)|F(Avx512KZ) , 177, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #250 [ref=9x]
+ { F(Vec)|F(Vex) , 181, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #251 [ref=2x]
+ { F(Vec)|F(Evex)|F(Avx512KZ) , 448, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #252 [ref=4x]
+ { F(Vec)|F(Evex)|F(Avx512KZ) , 182, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #253 [ref=4x]
+ { F(Vec)|F(Vex)|F(Evex) , 372, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #254 [ref=2x]
+ { F(Vec)|F(Evex)|F(Avx512KZ_SAE_B64) , 165, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #255 [ref=2x]
+ { F(Vec)|F(Evex)|F(Avx512KZ_SAE_B32) , 165, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #256 [ref=2x]
+ { F(Vec)|F(Evex)|F(Avx512KZ_SAE) , 449, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #257 [ref=4x]
+ { F(Vec)|F(Evex)|F(Avx512KZ_SAE) , 450, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #258 [ref=4x]
+ { F(Vec)|F(Vex) , 130, 4 , CONTROL(None) , SINGLE_REG(None), 0 }, // #259 [ref=13x]
+ { F(Vec)|F(Vex) , 320, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #260 [ref=4x]
+ { F(Vec)|F(Vex) , 322, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #261 [ref=4x]
+ { F(Vec)|F(Evex)|F(Avx512K_B64) , 451, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #262 [ref=1x]
+ { F(Vec)|F(Evex)|F(Avx512K_B32) , 451, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #263 [ref=1x]
+ { F(Vec)|F(Evex)|F(Avx512K) , 452, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #264 [ref=1x]
+ { F(Vec)|F(Evex)|F(Avx512K) , 453, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #265 [ref=1x]
+ { F(Vec)|F(Vex) , 177, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #266 [ref=7x]
+ { F(Vec)|F(Vex) , 97 , 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #267 [ref=1x]
+ { F(Vec)|F(Vex) , 225, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #268 [ref=1x]
+ { F(Vec)|F(Vsib)|F(Vex)|F(Evex)|F(Avx512K) , 99 , 5 , CONTROL(None) , SINGLE_REG(None), 0 }, // #269 [ref=2x]
+ { F(Vec)|F(Vsib)|F(Vex)|F(Evex)|F(Avx512K) , 104, 5 , CONTROL(None) , SINGLE_REG(None), 0 }, // #270 [ref=2x]
+ { F(Vsib)|F(Evex)|F(Avx512K) , 454, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #271 [ref=4x]
+ { F(Vsib)|F(Evex)|F(Avx512K) , 455, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #272 [ref=4x]
+ { F(Vsib)|F(Evex)|F(Avx512K) , 456, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #273 [ref=8x]
+ { F(Vec)|F(Vsib)|F(Vex)|F(Evex)|F(Avx512K) , 109, 5 , CONTROL(None) , SINGLE_REG(None), 0 }, // #274 [ref=2x]
+ { F(Vec)|F(Vsib)|F(Vex)|F(Evex)|F(Avx512K) , 134, 4 , CONTROL(None) , SINGLE_REG(None), 0 }, // #275 [ref=2x]
+ { F(Vec)|F(Evex)|F(Avx512KZ_SAE) , 437, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #276 [ref=3x]
+ { F(Vec)|F(Evex)|F(Avx512KZ_SAE) , 438, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #277 [ref=3x]
+ { F(Vec)|F(Evex)|F(Avx512KZ_SAE_B64) , 183, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #278 [ref=2x]
+ { F(Vec)|F(Evex)|F(Avx512KZ_SAE_B32) , 183, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #279 [ref=2x]
+ { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 165, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #280 [ref=3x]
+ { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 162, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #281 [ref=22x]
+ { F(Vec)|F(Vex) , 324, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #282 [ref=2x]
+ { F(Vec)|F(Evex)|F(Avx512KZ) , 324, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #283 [ref=4x]
+ { F(Vec)|F(Evex)|F(Avx512KZ) , 457, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #284 [ref=4x]
+ { F(Vec)|F(Vex)|F(Evex) , 450, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #285 [ref=1x]
+ { F(Vec)|F(Vex) , 192, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #286 [ref=1x]
+ { F(Vex) , 389, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #287 [ref=2x]
+ { F(Vec)|F(Vex) , 396, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #288 [ref=1x]
+ { F(Vec)|F(Vex) , 138, 4 , CONTROL(None) , SINGLE_REG(None), 0 }, // #289 [ref=4x]
+ { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_SAE_B64) , 162, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #290 [ref=2x]
+ { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_SAE_B32) , 162, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #291 [ref=2x]
+ { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_SAE) , 437, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #292 [ref=2x]
+ { 0 , 458, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #293 [ref=4x]
+ { 0 , 326, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #294 [ref=3x]
+ { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 70 , 6 , CONTROL(None) , SINGLE_REG(None), 0 }, // #295 [ref=4x]
+ { F(Vec)|F(Vex)|F(Evex) , 328, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #296 [ref=1x]
+ { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 186, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #297 [ref=1x]
+ { F(Vec)|F(Vex) , 70 , 4 , CONTROL(None) , SINGLE_REG(None), 0 }, // #298 [ref=2x]
+ { F(Vec)|F(Evex)|F(Avx512KZ) , 70 , 6 , CONTROL(None) , SINGLE_REG(None), 0 }, // #299 [ref=6x]
+ { F(Vec)|F(Vex)|F(Evex) , 200, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #300 [ref=2x]
+ { F(Vec)|F(Vex)|F(Evex) , 330, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #301 [ref=4x]
+ { F(Vec)|F(Vex) , 459, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #302 [ref=3x]
+ { F(Vec)|F(Vex)|F(Evex) , 189, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #303 [ref=3x]
+ { F(Vec)|F(Vex)|F(Evex) , 192, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #304 [ref=1x]
+ { F(Vec)|F(Vex)|F(Evex) , 195, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #305 [ref=1x]
+ { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 198, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #306 [ref=1x]
+ { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 177, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #307 [ref=5x]
+ { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 201, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #308 [ref=1x]
+ { 0 , 332, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #309 [ref=1x]
+ { 0 , 334, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #310 [ref=1x]
+ { F(Vec)|F(Evex)|F(Avx512B32) , 204, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #311 [ref=1x]
+ { F(Vec)|F(Evex)|F(Avx512B64) , 204, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #312 [ref=1x]
+ { F(Vec)|F(Vex) , 162, 2 , CONTROL(None) , SINGLE_REG(RO) , 0 }, // #313 [ref=2x]
+ { F(Vec)|F(Evex)|F(Avx512KZ_B32) , 162, 3 , CONTROL(None) , SINGLE_REG(RO) , 0 }, // #314 [ref=2x]
+ { F(Vec)|F(Vex) , 162, 2 , CONTROL(None) , SINGLE_REG(WO) , 0 }, // #315 [ref=2x]
+ { F(Vec)|F(Evex)|F(Avx512KZ_B32) , 162, 3 , CONTROL(None) , SINGLE_REG(WO) , 0 }, // #316 [ref=2x]
+ { F(Vec)|F(Evex)|F(Avx512KZ_B64) , 162, 3 , CONTROL(None) , SINGLE_REG(WO) , 0 }, // #317 [ref=2x]
+ { F(Vec)|F(Evex)|F(Avx512KZ_B64) , 162, 3 , CONTROL(None) , SINGLE_REG(RO) , 0 }, // #318 [ref=2x]
+ { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 460, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #319 [ref=1x]
+ { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 461, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #320 [ref=1x]
+ { F(Vec)|F(Evex) , 462, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #321 [ref=6x]
+ { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 207, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #322 [ref=1x]
+ { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 463, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #323 [ref=1x]
+ { F(Vec)|F(Vex)|F(Evex) , 165, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #324 [ref=1x]
+ { F(Vec)|F(Evex)|F(Avx512K) , 210, 3 , CONTROL(None) , SINGLE_REG(WO) , 0 }, // #325 [ref=2x]
+ { F(Vec)|F(Evex)|F(Avx512K_B32) , 210, 3 , CONTROL(None) , SINGLE_REG(WO) , 0 }, // #326 [ref=2x]
+ { F(Vec)|F(Vex)|F(Evex)|F(Avx512K) , 213, 3 , CONTROL(None) , SINGLE_REG(WO) , 0 }, // #327 [ref=4x]
+ { F(Vec)|F(Vex)|F(Evex)|F(Avx512K_B32) , 213, 3 , CONTROL(None) , SINGLE_REG(WO) , 0 }, // #328 [ref=2x]
+ { F(Vec)|F(Vex)|F(Evex)|F(Avx512K_B64) , 213, 3 , CONTROL(None) , SINGLE_REG(WO) , 0 }, // #329 [ref=2x]
+ { F(Vec)|F(Vex) , 409, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #330 [ref=1x]
+ { F(Vec)|F(Vex) , 410, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #331 [ref=1x]
+ { F(Vec)|F(Vex) , 411, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #332 [ref=1x]
+ { F(Vec)|F(Vex) , 412, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #333 [ref=1x]
+ { F(Vec)|F(Evex)|F(Avx512K_B64) , 210, 3 , CONTROL(None) , SINGLE_REG(WO) , 0 }, // #334 [ref=4x]
+ { F(Vec)|F(Evex)|F(Avx512KZ_B32) , 177, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #335 [ref=6x]
+ { F(Vec)|F(Vex) , 166, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #336 [ref=2x]
+ { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_B32) , 163, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #337 [ref=2x]
+ { F(Vec)|F(Vex) , 142, 4 , CONTROL(None) , SINGLE_REG(None), 0 }, // #338 [ref=2x]
+ { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_B64) , 76 , 6 , CONTROL(None) , SINGLE_REG(None), 0 }, // #339 [ref=2x]
+ { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_B64) , 146, 4 , CONTROL(None) , SINGLE_REG(None), 0 }, // #340 [ref=2x]
+ { F(Vec)|F(Vex)|F(Evex) , 413, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #341 [ref=1x]
+ { F(Vec)|F(Vex)|F(Evex) , 414, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #342 [ref=1x]
+ { F(Vec)|F(Vex)|F(Evex) , 464, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #343 [ref=1x]
+ { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 465, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #344 [ref=1x]
+ { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 466, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #345 [ref=1x]
+ { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 467, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #346 [ref=1x]
+ { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 468, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #347 [ref=1x]
+ { F(Vec)|F(Evex)|F(Avx512KZ_B64) , 177, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #348 [ref=4x]
+ { F(Vec)|F(Vex) , 316, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #349 [ref=12x]
+ { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 162, 3 , CONTROL(None) , SINGLE_REG(RO) , 0 }, // #350 [ref=8x]
+ { F(Vec)|F(Evex) , 469, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #351 [ref=4x]
+ { F(Vec)|F(Evex)|F(Avx512KZ) , 216, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #352 [ref=6x]
+ { F(Vec)|F(Evex)|F(Avx512KZ) , 219, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #353 [ref=9x]
+ { F(Vec)|F(Evex)|F(Avx512KZ) , 222, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #354 [ref=3x]
+ { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 225, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #355 [ref=4x]
+ { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 228, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #356 [ref=2x]
+ { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 174, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #357 [ref=6x]
+ { F(Vec)|F(Vex) , 130, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #358 [ref=1x]
+ { F(Vec)|F(Evex)|F(Avx512KZ_B32) , 183, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #359 [ref=3x]
+ { F(Vec)|F(Evex)|F(Avx512KZ_B64) , 183, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #360 [ref=3x]
+ { F(Vec)|F(Vex) , 336, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #361 [ref=4x]
+ { F(Vec)|F(Vsib)|F(Evex)|F(Avx512K) , 231, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #362 [ref=3x]
+ { F(Vec)|F(Vsib)|F(Evex)|F(Avx512K) , 338, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #363 [ref=2x]
+ { F(Vec)|F(Vsib)|F(Evex)|F(Avx512K) , 234, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #364 [ref=2x]
+ { F(Vec)|F(Vex) , 340, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #365 [ref=8x]
+ { F(Vec)|F(Evex)|F(Avx512K) , 237, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #366 [ref=5x]
+ { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_B32) , 183, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #367 [ref=1x]
+ { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 183, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #368 [ref=2x]
+ { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_B32) , 82 , 6 , CONTROL(None) , SINGLE_REG(None), 0 }, // #369 [ref=3x]
+ { F(Vec)|F(Vex)|F(Evex) , 183, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #370 [ref=2x]
+ { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_B64) , 82 , 6 , CONTROL(None) , SINGLE_REG(None), 0 }, // #371 [ref=2x]
+ { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 82 , 6 , CONTROL(None) , SINGLE_REG(None), 0 }, // #372 [ref=3x]
+ { F(Vec)|F(Evex)|F(Avx512KZ_B64) , 88 , 6 , CONTROL(None) , SINGLE_REG(None), 0 }, // #373 [ref=1x]
+ { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 162, 3 , CONTROL(None) , SINGLE_REG(WO) , 0 }, // #374 [ref=6x]
+ { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_B32) , 162, 3 , CONTROL(None) , SINGLE_REG(WO) , 0 }, // #375 [ref=2x]
+ { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_B64) , 162, 3 , CONTROL(None) , SINGLE_REG(WO) , 0 }, // #376 [ref=2x]
+ { F(Vec)|F(Evex)|F(Avx512K_B32) , 237, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #377 [ref=2x]
+ { F(Vec)|F(Evex)|F(Avx512K_B64) , 237, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #378 [ref=2x]
+ { F(Vec)|F(Evex)|F(Avx512KZ) , 437, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #379 [ref=2x]
+ { F(Vec)|F(Evex)|F(Avx512KZ) , 438, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #380 [ref=2x]
+ { F(Vec)|F(Vex) , 438, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #381 [ref=2x]
+ { F(Vec)|F(Evex)|F(Avx512KZ) , 449, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #382 [ref=1x]
+ { F(Vec)|F(Evex)|F(Avx512KZ) , 450, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #383 [ref=1x]
+ { F(Vec)|F(Vex) , 183, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #384 [ref=2x]
+ { F(Vec)|F(Vex) , 449, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #385 [ref=1x]
+ { F(Vec)|F(Vex) , 450, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #386 [ref=1x]
+ { F(Vec)|F(Evex)|F(Avx512KZ_ER_SAE_B64) , 162, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #387 [ref=1x]
+ { F(Vec)|F(Evex)|F(Avx512KZ_ER_SAE_B32) , 162, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #388 [ref=1x]
+ { F(Vec)|F(Evex)|F(Avx512KZ_ER_SAE) , 437, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #389 [ref=1x]
+ { F(Vec)|F(Evex)|F(Avx512KZ_ER_SAE) , 438, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #390 [ref=1x]
+ { F(Vec)|F(Vsib)|F(Evex)|F(Avx512K) , 342, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #391 [ref=1x]
+ { F(Vec)|F(Evex)|F(Avx512KZ_B32) , 166, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #392 [ref=2x]
+ { F(Vec)|F(Evex)|F(Avx512KZ_B64) , 166, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #393 [ref=2x]
+ { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_B32) , 165, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #394 [ref=1x]
+ { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_B64) , 165, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #395 [ref=1x]
+ { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_ER_SAE_B64) , 177, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #396 [ref=1x]
+ { F(Vec)|F(Vex) , 260, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #397 [ref=2x]
+ { F(Lock)|F(XAcquire)|F(XRelease) , 49 , 4 , CONTROL(None) , SINGLE_REG(None), 0 }, // #398 [ref=1x]
+ { 0 , 470, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #399 [ref=1x]
+ { F(Lock)|F(XAcquire) , 49 , 8 , CONTROL(None) , SINGLE_REG(RO) , 0 }, // #400 [ref=1x]
+ { 0 , 471, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #401 [ref=6x]
+ { 0 , 472, 1 , CONTROL(None) , SINGLE_REG(None), 0 } // #402 [ref=6x]
};
#undef SINGLE_REG
#undef CONTROL
@@ -2465,95 +2508,108 @@ const InstDB::CommonInfoTableB InstDB::_commonInfoTableB[] = {
{ { EXT(AVX512_BW) }, 1, 0 }, // #65 [ref=4x]
{ { EXT(AVX512_F) }, 1, 0 }, // #66 [ref=1x]
{ { EXT(LAHFSAHF) }, 22, 0 }, // #67 [ref=1x]
- { { EXT(LWP) }, 0, 0 }, // #68 [ref=4x]
- { { 0 }, 23, 0 }, // #69 [ref=3x]
- { { EXT(LZCNT) }, 1, 0 }, // #70 [ref=1x]
- { { EXT(MMX2) }, 0, 0 }, // #71 [ref=8x]
- { { EXT(MONITOR) }, 0, 0 }, // #72 [ref=2x]
- { { EXT(MONITORX) }, 0, 0 }, // #73 [ref=2x]
- { { EXT(MOVBE) }, 0, 0 }, // #74 [ref=1x]
- { { EXT(MMX), EXT(SSE2) }, 0, 0 }, // #75 [ref=46x]
- { { EXT(MOVDIR64B) }, 0, 0 }, // #76 [ref=1x]
- { { EXT(MOVDIRI) }, 0, 0 }, // #77 [ref=1x]
- { { EXT(BMI2) }, 0, 0 }, // #78 [ref=7x]
- { { EXT(SSSE3) }, 0, 0 }, // #79 [ref=15x]
- { { EXT(MMX2), EXT(SSE2) }, 0, 0 }, // #80 [ref=10x]
- { { EXT(PCLMULQDQ) }, 0, 0 }, // #81 [ref=1x]
- { { EXT(SSE4_2) }, 1, 0 }, // #82 [ref=4x]
- { { EXT(PCOMMIT) }, 0, 0 }, // #83 [ref=1x]
- { { EXT(MMX2), EXT(SSE2), EXT(SSE4_1) }, 0, 0 }, // #84 [ref=1x]
- { { EXT(3DNOW2) }, 0, 0 }, // #85 [ref=5x]
- { { EXT(GEODE) }, 0, 0 }, // #86 [ref=2x]
- { { EXT(POPCNT) }, 1, 0 }, // #87 [ref=1x]
- { { 0 }, 24, 0 }, // #88 [ref=3x]
- { { EXT(PREFETCHW) }, 1, 0 }, // #89 [ref=1x]
- { { EXT(PREFETCHWT1) }, 1, 0 }, // #90 [ref=1x]
- { { EXT(SSE4_1) }, 1, 0 }, // #91 [ref=1x]
- { { 0 }, 25, 0 }, // #92 [ref=3x]
- { { 0 }, 26, 0 }, // #93 [ref=2x]
- { { EXT(FSGSBASE) }, 0, 0 }, // #94 [ref=4x]
- { { EXT(MSR) }, 0, 0 }, // #95 [ref=2x]
- { { EXT(RDPID) }, 0, 0 }, // #96 [ref=1x]
- { { EXT(RDRAND) }, 1, 0 }, // #97 [ref=1x]
- { { EXT(RDSEED) }, 1, 0 }, // #98 [ref=1x]
- { { EXT(RDTSC) }, 0, 0 }, // #99 [ref=1x]
- { { EXT(RDTSCP) }, 0, 0 }, // #100 [ref=1x]
- { { 0 }, 27, 0 }, // #101 [ref=2x]
- { { EXT(LAHFSAHF) }, 28, 0 }, // #102 [ref=1x]
- { { EXT(SHA) }, 0, 0 }, // #103 [ref=7x]
- { { EXT(SKINIT) }, 0, 0 }, // #104 [ref=2x]
- { { EXT(AVX512_4FMAPS) }, 0, 0 }, // #105 [ref=4x]
- { { EXT(AVX), EXT(AVX512_F), EXT(AVX512_VL) }, 0, 0 }, // #106 [ref=46x]
- { { EXT(AVX), EXT(AVX512_F) }, 0, 0 }, // #107 [ref=32x]
- { { EXT(AVX) }, 0, 0 }, // #108 [ref=37x]
- { { EXT(AESNI), EXT(AVX), EXT(AVX512_F), EXT(AVX512_VL), EXT(VAES) }, 0, 0 }, // #109 [ref=4x]
- { { EXT(AESNI), EXT(AVX) }, 0, 0 }, // #110 [ref=2x]
- { { EXT(AVX512_F), EXT(AVX512_VL) }, 0, 0 }, // #111 [ref=112x]
- { { EXT(AVX), EXT(AVX512_DQ), EXT(AVX512_VL) }, 0, 0 }, // #112 [ref=8x]
- { { EXT(AVX512_BW), EXT(AVX512_VL) }, 0, 0 }, // #113 [ref=26x]
- { { EXT(AVX512_DQ), EXT(AVX512_VL) }, 0, 0 }, // #114 [ref=30x]
- { { EXT(AVX2) }, 0, 0 }, // #115 [ref=7x]
- { { EXT(AVX), EXT(AVX2), EXT(AVX512_F), EXT(AVX512_VL) }, 0, 0 }, // #116 [ref=39x]
- { { EXT(AVX), EXT(AVX512_F) }, 1, 0 }, // #117 [ref=4x]
- { { EXT(AVX512_BF16), EXT(AVX512_VL) }, 0, 0 }, // #118 [ref=3x]
- { { EXT(AVX512_F), EXT(AVX512_VL), EXT(F16C) }, 0, 0 }, // #119 [ref=2x]
- { { EXT(AVX512_ERI) }, 0, 0 }, // #120 [ref=10x]
- { { EXT(AVX512_F), EXT(AVX512_VL), EXT(FMA) }, 0, 0 }, // #121 [ref=36x]
- { { EXT(AVX512_F), EXT(FMA) }, 0, 0 }, // #122 [ref=24x]
- { { EXT(FMA4) }, 0, 0 }, // #123 [ref=20x]
- { { EXT(XOP) }, 0, 0 }, // #124 [ref=55x]
- { { EXT(AVX2), EXT(AVX512_F), EXT(AVX512_VL) }, 0, 0 }, // #125 [ref=19x]
- { { EXT(AVX512_PFI) }, 0, 0 }, // #126 [ref=16x]
- { { EXT(AVX), EXT(AVX512_F), EXT(AVX512_VL), EXT(GFNI) }, 0, 0 }, // #127 [ref=3x]
- { { EXT(AVX), EXT(AVX2) }, 0, 0 }, // #128 [ref=17x]
- { { EXT(AVX512_4VNNIW) }, 0, 0 }, // #129 [ref=2x]
- { { EXT(AVX), EXT(AVX2), EXT(AVX512_BW), EXT(AVX512_VL) }, 0, 0 }, // #130 [ref=54x]
- { { EXT(AVX2), EXT(AVX512_BW), EXT(AVX512_VL) }, 0, 0 }, // #131 [ref=2x]
- { { EXT(AVX512_CDI), EXT(AVX512_VL) }, 0, 0 }, // #132 [ref=6x]
- { { EXT(AVX), EXT(AVX512_F), EXT(AVX512_VL), EXT(PCLMULQDQ), EXT(VPCLMULQDQ) }, 0, 0 }, // #133 [ref=1x]
- { { EXT(AVX) }, 1, 0 }, // #134 [ref=7x]
- { { EXT(AVX512_VBMI2), EXT(AVX512_VL) }, 0, 0 }, // #135 [ref=16x]
- { { EXT(AVX512_VL), EXT(AVX512_VNNI) }, 0, 0 }, // #136 [ref=4x]
- { { EXT(AVX512_VBMI), EXT(AVX512_VL) }, 0, 0 }, // #137 [ref=4x]
- { { EXT(AVX), EXT(AVX512_BW) }, 0, 0 }, // #138 [ref=4x]
- { { EXT(AVX), EXT(AVX512_DQ) }, 0, 0 }, // #139 [ref=4x]
- { { EXT(AVX512_IFMA), EXT(AVX512_VL) }, 0, 0 }, // #140 [ref=2x]
- { { EXT(AVX512_BITALG), EXT(AVX512_VL) }, 0, 0 }, // #141 [ref=3x]
- { { EXT(AVX512_VL), EXT(AVX512_VPOPCNTDQ) }, 0, 0 }, // #142 [ref=2x]
- { { EXT(WBNOINVD) }, 0, 0 }, // #143 [ref=1x]
- { { EXT(RTM) }, 0, 0 }, // #144 [ref=3x]
- { { EXT(XSAVE) }, 0, 0 }, // #145 [ref=6x]
- { { EXT(XSAVES) }, 0, 0 }, // #146 [ref=4x]
- { { EXT(XSAVEC) }, 0, 0 }, // #147 [ref=2x]
- { { EXT(XSAVEOPT) }, 0, 0 }, // #148 [ref=2x]
- { { EXT(TSX) }, 1, 0 } // #149 [ref=1x]
+ { { EXT(AMX_TILE) }, 0, 0 }, // #68 [ref=7x]
+ { { EXT(LWP) }, 0, 0 }, // #69 [ref=4x]
+ { { 0 }, 23, 0 }, // #70 [ref=3x]
+ { { EXT(LZCNT) }, 1, 0 }, // #71 [ref=1x]
+ { { EXT(MMX2) }, 0, 0 }, // #72 [ref=8x]
+ { { EXT(MCOMMIT) }, 1, 0 }, // #73 [ref=1x]
+ { { EXT(MONITOR) }, 0, 0 }, // #74 [ref=2x]
+ { { EXT(MONITORX) }, 0, 0 }, // #75 [ref=2x]
+ { { EXT(MOVBE) }, 0, 0 }, // #76 [ref=1x]
+ { { EXT(MMX), EXT(SSE2) }, 0, 0 }, // #77 [ref=46x]
+ { { EXT(MOVDIR64B) }, 0, 0 }, // #78 [ref=1x]
+ { { EXT(MOVDIRI) }, 0, 0 }, // #79 [ref=1x]
+ { { EXT(BMI2) }, 0, 0 }, // #80 [ref=7x]
+ { { EXT(SSSE3) }, 0, 0 }, // #81 [ref=15x]
+ { { EXT(MMX2), EXT(SSE2) }, 0, 0 }, // #82 [ref=10x]
+ { { EXT(PCLMULQDQ) }, 0, 0 }, // #83 [ref=1x]
+ { { EXT(SSE4_2) }, 1, 0 }, // #84 [ref=4x]
+ { { EXT(PCOMMIT) }, 0, 0 }, // #85 [ref=1x]
+ { { EXT(PCONFIG) }, 0, 0 }, // #86 [ref=1x]
+ { { EXT(MMX2), EXT(SSE2), EXT(SSE4_1) }, 0, 0 }, // #87 [ref=1x]
+ { { EXT(3DNOW2) }, 0, 0 }, // #88 [ref=5x]
+ { { EXT(GEODE) }, 0, 0 }, // #89 [ref=2x]
+ { { EXT(POPCNT) }, 1, 0 }, // #90 [ref=1x]
+ { { 0 }, 24, 0 }, // #91 [ref=3x]
+ { { EXT(PREFETCHW) }, 1, 0 }, // #92 [ref=1x]
+ { { EXT(PREFETCHWT1) }, 1, 0 }, // #93 [ref=1x]
+ { { EXT(SNP) }, 20, 0 }, // #94 [ref=3x]
+ { { EXT(SSE4_1) }, 1, 0 }, // #95 [ref=1x]
+ { { 0 }, 25, 0 }, // #96 [ref=3x]
+ { { EXT(SNP) }, 1, 0 }, // #97 [ref=1x]
+ { { 0 }, 26, 0 }, // #98 [ref=2x]
+ { { EXT(FSGSBASE) }, 0, 0 }, // #99 [ref=4x]
+ { { EXT(MSR) }, 0, 0 }, // #100 [ref=2x]
+ { { EXT(RDPID) }, 0, 0 }, // #101 [ref=1x]
+ { { EXT(RDPRU) }, 0, 0 }, // #102 [ref=1x]
+ { { EXT(RDRAND) }, 1, 0 }, // #103 [ref=1x]
+ { { EXT(RDSEED) }, 1, 0 }, // #104 [ref=1x]
+ { { EXT(RDTSC) }, 0, 0 }, // #105 [ref=1x]
+ { { EXT(RDTSCP) }, 0, 0 }, // #106 [ref=1x]
+ { { 0 }, 27, 0 }, // #107 [ref=2x]
+ { { EXT(LAHFSAHF) }, 28, 0 }, // #108 [ref=1x]
+ { { EXT(SERIALIZE) }, 0, 0 }, // #109 [ref=1x]
+ { { EXT(SHA) }, 0, 0 }, // #110 [ref=7x]
+ { { EXT(SKINIT) }, 0, 0 }, // #111 [ref=2x]
+ { { EXT(AMX_BF16) }, 0, 0 }, // #112 [ref=1x]
+ { { EXT(AMX_INT8) }, 0, 0 }, // #113 [ref=4x]
+ { { EXT(WAITPKG) }, 1, 0 }, // #114 [ref=2x]
+ { { EXT(WAITPKG) }, 0, 0 }, // #115 [ref=1x]
+ { { EXT(AVX512_4FMAPS) }, 0, 0 }, // #116 [ref=4x]
+ { { EXT(AVX), EXT(AVX512_F), EXT(AVX512_VL) }, 0, 0 }, // #117 [ref=46x]
+ { { EXT(AVX), EXT(AVX512_F) }, 0, 0 }, // #118 [ref=32x]
+ { { EXT(AVX) }, 0, 0 }, // #119 [ref=37x]
+ { { EXT(AESNI), EXT(AVX), EXT(AVX512_F), EXT(AVX512_VL), EXT(VAES) }, 0, 0 }, // #120 [ref=4x]
+ { { EXT(AESNI), EXT(AVX) }, 0, 0 }, // #121 [ref=2x]
+ { { EXT(AVX512_F), EXT(AVX512_VL) }, 0, 0 }, // #122 [ref=112x]
+ { { EXT(AVX), EXT(AVX512_DQ), EXT(AVX512_VL) }, 0, 0 }, // #123 [ref=8x]
+ { { EXT(AVX512_BW), EXT(AVX512_VL) }, 0, 0 }, // #124 [ref=26x]
+ { { EXT(AVX512_DQ), EXT(AVX512_VL) }, 0, 0 }, // #125 [ref=30x]
+ { { EXT(AVX2) }, 0, 0 }, // #126 [ref=7x]
+ { { EXT(AVX), EXT(AVX2), EXT(AVX512_F), EXT(AVX512_VL) }, 0, 0 }, // #127 [ref=39x]
+ { { EXT(AVX), EXT(AVX512_F) }, 1, 0 }, // #128 [ref=4x]
+ { { EXT(AVX512_BF16), EXT(AVX512_VL) }, 0, 0 }, // #129 [ref=3x]
+ { { EXT(AVX512_F), EXT(AVX512_VL), EXT(F16C) }, 0, 0 }, // #130 [ref=2x]
+ { { EXT(AVX512_ERI) }, 0, 0 }, // #131 [ref=10x]
+ { { EXT(AVX512_F), EXT(AVX512_VL), EXT(FMA) }, 0, 0 }, // #132 [ref=36x]
+ { { EXT(AVX512_F), EXT(FMA) }, 0, 0 }, // #133 [ref=24x]
+ { { EXT(FMA4) }, 0, 0 }, // #134 [ref=20x]
+ { { EXT(XOP) }, 0, 0 }, // #135 [ref=55x]
+ { { EXT(AVX2), EXT(AVX512_F), EXT(AVX512_VL) }, 0, 0 }, // #136 [ref=19x]
+ { { EXT(AVX512_PFI) }, 0, 0 }, // #137 [ref=16x]
+ { { EXT(AVX), EXT(AVX512_F), EXT(AVX512_VL), EXT(GFNI) }, 0, 0 }, // #138 [ref=3x]
+ { { EXT(AVX), EXT(AVX2) }, 0, 0 }, // #139 [ref=17x]
+ { { EXT(AVX512_VP2INTERSECT) }, 0, 0 }, // #140 [ref=2x]
+ { { EXT(AVX512_4VNNIW) }, 0, 0 }, // #141 [ref=2x]
+ { { EXT(AVX), EXT(AVX2), EXT(AVX512_BW), EXT(AVX512_VL) }, 0, 0 }, // #142 [ref=54x]
+ { { EXT(AVX2), EXT(AVX512_BW), EXT(AVX512_VL) }, 0, 0 }, // #143 [ref=2x]
+ { { EXT(AVX512_CDI), EXT(AVX512_VL) }, 0, 0 }, // #144 [ref=6x]
+ { { EXT(AVX), EXT(AVX512_F), EXT(AVX512_VL), EXT(PCLMULQDQ), EXT(VPCLMULQDQ) }, 0, 0 }, // #145 [ref=1x]
+ { { EXT(AVX) }, 1, 0 }, // #146 [ref=7x]
+ { { EXT(AVX512_VBMI2), EXT(AVX512_VL) }, 0, 0 }, // #147 [ref=16x]
+ { { EXT(AVX512_VL), EXT(AVX512_VNNI) }, 0, 0 }, // #148 [ref=4x]
+ { { EXT(AVX512_VBMI), EXT(AVX512_VL) }, 0, 0 }, // #149 [ref=4x]
+ { { EXT(AVX), EXT(AVX512_BW) }, 0, 0 }, // #150 [ref=4x]
+ { { EXT(AVX), EXT(AVX512_DQ) }, 0, 0 }, // #151 [ref=4x]
+ { { EXT(AVX512_IFMA), EXT(AVX512_VL) }, 0, 0 }, // #152 [ref=2x]
+ { { EXT(AVX512_BITALG), EXT(AVX512_VL) }, 0, 0 }, // #153 [ref=3x]
+ { { EXT(AVX512_VL), EXT(AVX512_VPOPCNTDQ) }, 0, 0 }, // #154 [ref=2x]
+ { { EXT(WBNOINVD) }, 0, 0 }, // #155 [ref=1x]
+ { { EXT(RTM) }, 0, 0 }, // #156 [ref=3x]
+ { { EXT(XSAVE) }, 0, 0 }, // #157 [ref=6x]
+ { { EXT(TSXLDTRK) }, 0, 0 }, // #158 [ref=2x]
+ { { EXT(XSAVES) }, 0, 0 }, // #159 [ref=4x]
+ { { EXT(XSAVEC) }, 0, 0 }, // #160 [ref=2x]
+ { { EXT(XSAVEOPT) }, 0, 0 }, // #161 [ref=2x]
+ { { EXT(TSX) }, 1, 0 } // #162 [ref=1x]
};
#undef EXT
#define FLAG(VAL) uint32_t(Status::k##VAL)
const InstDB::RWFlagsInfoTable InstDB::_rwFlagsInfoTable[] = {
- { 0, 0 }, // #0 [ref=1281x]
- { 0, FLAG(AF) | FLAG(CF) | FLAG(OF) | FLAG(PF) | FLAG(SF) | FLAG(ZF) }, // #1 [ref=76x]
+ { 0, 0 }, // #0 [ref=1301x]
+ { 0, FLAG(AF) | FLAG(CF) | FLAG(OF) | FLAG(PF) | FLAG(SF) | FLAG(ZF) }, // #1 [ref=80x]
{ FLAG(CF), FLAG(AF) | FLAG(CF) | FLAG(OF) | FLAG(PF) | FLAG(SF) | FLAG(ZF) }, // #2 [ref=2x]
{ FLAG(CF), FLAG(CF) }, // #3 [ref=2x]
{ FLAG(OF), FLAG(OF) }, // #4 [ref=1x]
@@ -2572,7 +2628,7 @@ const InstDB::RWFlagsInfoTable InstDB::_rwFlagsInfoTable[] = {
{ FLAG(PF), 0 }, // #17 [ref=14x]
{ FLAG(SF), 0 }, // #18 [ref=6x]
{ FLAG(DF), FLAG(AF) | FLAG(CF) | FLAG(OF) | FLAG(PF) | FLAG(SF) | FLAG(ZF) }, // #19 [ref=2x]
- { 0, FLAG(AF) | FLAG(OF) | FLAG(PF) | FLAG(SF) | FLAG(ZF) }, // #20 [ref=2x]
+ { 0, FLAG(AF) | FLAG(OF) | FLAG(PF) | FLAG(SF) | FLAG(ZF) }, // #20 [ref=5x]
{ 0, FLAG(CF) | FLAG(PF) | FLAG(ZF) }, // #21 [ref=4x]
{ FLAG(AF) | FLAG(CF) | FLAG(PF) | FLAG(SF) | FLAG(ZF), 0 }, // #22 [ref=1x]
{ FLAG(DF), 0 }, // #23 [ref=3x]
@@ -2619,66 +2675,69 @@ const char InstDB::_nameData[] =
"knotd\0" "knotq\0" "knotw\0" "korb\0" "kord\0" "korq\0" "kortestb\0" "kortestd\0" "kortestq\0" "kortestw\0" "korw\0"
"kshiftlb\0" "kshiftld\0" "kshiftlq\0" "kshiftlw\0" "kshiftrb\0" "kshiftrd\0" "kshiftrq\0" "kshiftrw\0" "ktestb\0"
"ktestd\0" "ktestq\0" "ktestw\0" "kunpckbw\0" "kunpckdq\0" "kunpckwd\0" "kxnorb\0" "kxnord\0" "kxnorq\0" "kxnorw\0"
- "kxorb\0" "kxord\0" "kxorq\0" "kxorw\0" "lahf\0" "lar\0" "lds\0" "lea\0" "leave\0" "les\0" "lfence\0" "lfs\0"
- "lgdt\0" "lgs\0" "lidt\0" "lldt\0" "llwpcb\0" "lmsw\0" "lods\0" "loop\0" "loope\0" "loopne\0" "lsl\0" "ltr\0"
- "lwpins\0" "lwpval\0" "lzcnt\0" "mfence\0" "monitor\0" "monitorx\0" "movdir64b\0" "movdiri\0" "movdq2q\0" "movnti\0"
- "movntq\0" "movntsd\0" "movntss\0" "movq2dq\0" "movsx\0" "movsxd\0" "movzx\0" "mulx\0" "mwait\0" "mwaitx\0" "neg\0"
- "not\0" "out\0" "outs\0" "pause\0" "pavgusb\0" "pcommit\0" "pdep\0" "pext\0" "pf2id\0" "pf2iw\0" "pfacc\0" "pfadd\0"
+ "kxorb\0" "kxord\0" "kxorq\0" "kxorw\0" "lahf\0" "lar\0" "lds\0" "ldtilecfg\0" "lea\0" "leave\0" "les\0" "lfence\0"
+ "lfs\0" "lgdt\0" "lgs\0" "lidt\0" "lldt\0" "llwpcb\0" "lmsw\0" "lods\0" "loop\0" "loope\0" "loopne\0" "lsl\0" "ltr\0"
+ "lwpins\0" "lwpval\0" "lzcnt\0" "mcommit\0" "mfence\0" "monitorx\0" "movdir64b\0" "movdiri\0" "movdq2q\0" "movnti\0"
+ "movntq\0" "movntsd\0" "movntss\0" "movq2dq\0" "movsx\0" "movsxd\0" "movzx\0" "mulx\0" "mwaitx\0" "neg\0" "not\0"
+ "out\0" "outs\0" "pavgusb\0" "pcommit\0" "pconfig\0" "pdep\0" "pext\0" "pf2id\0" "pf2iw\0" "pfacc\0" "pfadd\0"
"pfcmpeq\0" "pfcmpge\0" "pfcmpgt\0" "pfmax\0" "pfmin\0" "pfmul\0" "pfnacc\0" "pfpnacc\0" "pfrcp\0" "pfrcpit1\0"
"pfrcpit2\0" "pfrcpv\0" "pfrsqit1\0" "pfrsqrt\0" "pfrsqrtv\0" "pfsub\0" "pfsubr\0" "pi2fd\0" "pi2fw\0" "pmulhrw\0"
"pop\0" "popa\0" "popad\0" "popcnt\0" "popf\0" "popfd\0" "popfq\0" "prefetch\0" "prefetchnta\0" "prefetcht0\0"
- "prefetcht1\0" "prefetcht2\0" "prefetchw\0" "prefetchwt1\0" "pshufw\0" "pswapd\0" "push\0" "pusha\0" "pushad\0"
- "pushf\0" "pushfd\0" "pushfq\0" "rcl\0" "rcr\0" "rdfsbase\0" "rdgsbase\0" "rdmsr\0" "rdpid\0" "rdpmc\0" "rdrand\0"
- "rdseed\0" "rdtsc\0" "rdtscp\0" "rol\0" "ror\0" "rorx\0" "rsm\0" "sahf\0" "sal\0" "sar\0" "sarx\0" "sbb\0" "scas\0"
- "seta\0" "setae\0" "setb\0" "setbe\0" "setc\0" "sete\0" "setg\0" "setge\0" "setl\0" "setle\0" "setna\0" "setnae\0"
- "setnb\0" "setnbe\0" "setnc\0" "setne\0" "setng\0" "setnge\0" "setnl\0" "setnle\0" "setno\0" "setnp\0" "setns\0"
- "setnz\0" "seto\0" "setp\0" "setpe\0" "setpo\0" "sets\0" "setz\0" "sfence\0" "sgdt\0" "sha1msg1\0" "sha1msg2\0"
- "sha1nexte\0" "sha1rnds4\0" "sha256msg1\0" "sha256msg2\0" "sha256rnds2\0" "shl\0" "shlx\0" "shr\0" "shrd\0" "shrx\0"
- "sidt\0" "skinit\0" "sldt\0" "slwpcb\0" "smsw\0" "stac\0" "stc\0" "stgi\0" "sti\0" "stos\0" "str\0" "swapgs\0"
- "syscall\0" "sysenter\0" "sysexit\0" "sysexit64\0" "sysret\0" "sysret64\0" "t1mskc\0" "tzcnt\0" "tzmsk\0" "ud2\0"
- "v4fmaddps\0" "v4fmaddss\0" "v4fnmaddps\0" "v4fnmaddss\0" "vaddpd\0" "vaddps\0" "vaddsd\0" "vaddss\0" "vaddsubpd\0"
- "vaddsubps\0" "vaesdec\0" "vaesdeclast\0" "vaesenc\0" "vaesenclast\0" "vaesimc\0" "vaeskeygenassist\0" "valignd\0"
- "valignq\0" "vandnpd\0" "vandnps\0" "vandpd\0" "vandps\0" "vblendmb\0" "vblendmd\0" "vblendmpd\0" "vblendmps\0"
- "vblendmq\0" "vblendmw\0" "vblendpd\0" "vblendps\0" "vblendvpd\0" "vblendvps\0" "vbroadcastf128\0"
- "vbroadcastf32x2\0" "vbroadcastf32x4\0" "vbroadcastf32x8\0" "vbroadcastf64x2\0" "vbroadcastf64x4\0"
- "vbroadcasti128\0" "vbroadcasti32x2\0" "vbroadcasti32x4\0" "vbroadcasti32x8\0" "vbroadcasti64x2\0"
- "vbroadcasti64x4\0" "vbroadcastsd\0" "vbroadcastss\0" "vcmppd\0" "vcmpps\0" "vcmpsd\0" "vcmpss\0" "vcomisd\0"
- "vcomiss\0" "vcompresspd\0" "vcompressps\0" "vcvtdq2pd\0" "vcvtdq2ps\0" "vcvtne2ps2bf16\0" "vcvtneps2bf16\0"
- "vcvtpd2dq\0" "vcvtpd2ps\0" "vcvtpd2qq\0" "vcvtpd2udq\0" "vcvtpd2uqq\0" "vcvtph2ps\0" "vcvtps2dq\0" "vcvtps2pd\0"
- "vcvtps2ph\0" "vcvtps2qq\0" "vcvtps2udq\0" "vcvtps2uqq\0" "vcvtqq2pd\0" "vcvtqq2ps\0" "vcvtsd2si\0" "vcvtsd2ss\0"
- "vcvtsd2usi\0" "vcvtsi2sd\0" "vcvtsi2ss\0" "vcvtss2sd\0" "vcvtss2si\0" "vcvtss2usi\0" "vcvttpd2dq\0" "vcvttpd2qq\0"
- "vcvttpd2udq\0" "vcvttpd2uqq\0" "vcvttps2dq\0" "vcvttps2qq\0" "vcvttps2udq\0" "vcvttps2uqq\0" "vcvttsd2si\0"
- "vcvttsd2usi\0" "vcvttss2si\0" "vcvttss2usi\0" "vcvtudq2pd\0" "vcvtudq2ps\0" "vcvtuqq2pd\0" "vcvtuqq2ps\0"
- "vcvtusi2sd\0" "vcvtusi2ss\0" "vdbpsadbw\0" "vdivpd\0" "vdivps\0" "vdivsd\0" "vdivss\0" "vdpbf16ps\0" "vdppd\0"
- "vdpps\0" "verr\0" "verw\0" "vexp2pd\0" "vexp2ps\0" "vexpandpd\0" "vexpandps\0" "vextractf128\0" "vextractf32x4\0"
- "vextractf32x8\0" "vextractf64x2\0" "vextractf64x4\0" "vextracti128\0" "vextracti32x4\0" "vextracti32x8\0"
- "vextracti64x2\0" "vextracti64x4\0" "vextractps\0" "vfixupimmpd\0" "vfixupimmps\0" "vfixupimmsd\0" "vfixupimmss\0"
- "vfmadd132pd\0" "vfmadd132ps\0" "vfmadd132sd\0" "vfmadd132ss\0" "vfmadd213pd\0" "vfmadd213ps\0" "vfmadd213sd\0"
- "vfmadd213ss\0" "vfmadd231pd\0" "vfmadd231ps\0" "vfmadd231sd\0" "vfmadd231ss\0" "vfmaddpd\0" "vfmaddps\0"
- "vfmaddsd\0" "vfmaddss\0" "vfmaddsub132pd\0" "vfmaddsub132ps\0" "vfmaddsub213pd\0" "vfmaddsub213ps\0"
- "vfmaddsub231pd\0" "vfmaddsub231ps\0" "vfmaddsubpd\0" "vfmaddsubps\0" "vfmsub132pd\0" "vfmsub132ps\0" "vfmsub132sd\0"
- "vfmsub132ss\0" "vfmsub213pd\0" "vfmsub213ps\0" "vfmsub213sd\0" "vfmsub213ss\0" "vfmsub231pd\0" "vfmsub231ps\0"
- "vfmsub231sd\0" "vfmsub231ss\0" "vfmsubadd132pd\0" "vfmsubadd132ps\0" "vfmsubadd213pd\0" "vfmsubadd213ps\0"
- "vfmsubadd231pd\0" "vfmsubadd231ps\0" "vfmsubaddpd\0" "vfmsubaddps\0" "vfmsubpd\0" "vfmsubps\0" "vfmsubsd\0"
- "vfmsubss\0" "vfnmadd132pd\0" "vfnmadd132ps\0" "vfnmadd132sd\0" "vfnmadd132ss\0" "vfnmadd213pd\0" "vfnmadd213ps\0"
- "vfnmadd213sd\0" "vfnmadd213ss\0" "vfnmadd231pd\0" "vfnmadd231ps\0" "vfnmadd231sd\0" "vfnmadd231ss\0" "vfnmaddpd\0"
- "vfnmaddps\0" "vfnmaddsd\0" "vfnmaddss\0" "vfnmsub132pd\0" "vfnmsub132ps\0" "vfnmsub132sd\0" "vfnmsub132ss\0"
- "vfnmsub213pd\0" "vfnmsub213ps\0" "vfnmsub213sd\0" "vfnmsub213ss\0" "vfnmsub231pd\0" "vfnmsub231ps\0"
- "vfnmsub231sd\0" "vfnmsub231ss\0" "vfnmsubpd\0" "vfnmsubps\0" "vfnmsubsd\0" "vfnmsubss\0" "vfpclasspd\0"
- "vfpclassps\0" "vfpclasssd\0" "vfpclassss\0" "vfrczpd\0" "vfrczps\0" "vfrczsd\0" "vfrczss\0" "vgatherdpd\0"
- "vgatherdps\0" "vgatherpf0dpd\0" "vgatherpf0dps\0" "vgatherpf0qpd\0" "vgatherpf0qps\0" "vgatherpf1dpd\0"
- "vgatherpf1dps\0" "vgatherpf1qpd\0" "vgatherpf1qps\0" "vgatherqpd\0" "vgatherqps\0" "vgetexppd\0" "vgetexpps\0"
- "vgetexpsd\0" "vgetexpss\0" "vgetmantpd\0" "vgetmantps\0" "vgetmantsd\0" "vgetmantss\0" "vgf2p8affineinvqb\0"
- "vgf2p8affineqb\0" "vgf2p8mulb\0" "vhaddpd\0" "vhaddps\0" "vhsubpd\0" "vhsubps\0" "vinsertf128\0" "vinsertf32x4\0"
- "vinsertf32x8\0" "vinsertf64x2\0" "vinsertf64x4\0" "vinserti128\0" "vinserti32x4\0" "vinserti32x8\0" "vinserti64x2\0"
- "vinserti64x4\0" "vinsertps\0" "vlddqu\0" "vldmxcsr\0" "vmaskmovdqu\0" "vmaskmovpd\0" "vmaskmovps\0" "vmaxpd\0"
- "vmaxps\0" "vmaxsd\0" "vmaxss\0" "vmcall\0" "vmclear\0" "vmfunc\0" "vminpd\0" "vminps\0" "vminsd\0" "vminss\0"
- "vmlaunch\0" "vmload\0" "vmmcall\0" "vmovapd\0" "vmovaps\0" "vmovd\0" "vmovddup\0" "vmovdqa\0" "vmovdqa32\0"
- "vmovdqa64\0" "vmovdqu\0" "vmovdqu16\0" "vmovdqu32\0" "vmovdqu64\0" "vmovdqu8\0" "vmovhlps\0" "vmovhpd\0" "vmovhps\0"
- "vmovlhps\0" "vmovlpd\0" "vmovlps\0" "vmovmskpd\0" "vmovmskps\0" "vmovntdq\0" "vmovntdqa\0" "vmovntpd\0" "vmovntps\0"
- "vmovq\0" "vmovsd\0" "vmovshdup\0" "vmovsldup\0" "vmovss\0" "vmovupd\0" "vmovups\0" "vmpsadbw\0" "vmptrld\0"
- "vmptrst\0" "vmread\0" "vmresume\0" "vmrun\0" "vmsave\0" "vmulpd\0" "vmulps\0" "vmulsd\0" "vmulss\0" "vmwrite\0"
- "vmxon\0" "vorpd\0" "vorps\0" "vp4dpwssd\0" "vp4dpwssds\0" "vpabsb\0" "vpabsd\0" "vpabsq\0" "vpabsw\0" "vpackssdw\0"
+ "prefetcht1\0" "prefetcht2\0" "prefetchw\0" "prefetchwt1\0" "pshufw\0" "psmash\0" "pswapd\0" "push\0" "pusha\0"
+ "pushad\0" "pushf\0" "pushfd\0" "pushfq\0" "pvalidate\0" "rcl\0" "rcr\0" "rdfsbase\0" "rdgsbase\0" "rdmsr\0"
+ "rdpid\0" "rdpmc\0" "rdpru\0" "rdrand\0" "rdseed\0" "rdtsc\0" "rdtscp\0" "rmpadjust\0" "rmpupdate\0" "rol\0" "ror\0"
+ "rorx\0" "rsm\0" "sahf\0" "sal\0" "sar\0" "sarx\0" "sbb\0" "scas\0" "serialize\0" "seta\0" "setae\0" "setb\0"
+ "setbe\0" "setc\0" "sete\0" "setg\0" "setge\0" "setl\0" "setle\0" "setna\0" "setnae\0" "setnb\0" "setnbe\0" "setnc\0"
+ "setne\0" "setng\0" "setnge\0" "setnl\0" "setnle\0" "setno\0" "setnp\0" "setns\0" "setnz\0" "seto\0" "setp\0"
+ "setpe\0" "setpo\0" "sets\0" "setz\0" "sfence\0" "sgdt\0" "sha1msg1\0" "sha1msg2\0" "sha1nexte\0" "sha1rnds4\0"
+ "sha256msg1\0" "sha256msg2\0" "sha256rnds2\0" "shl\0" "shlx\0" "shr\0" "shrd\0" "shrx\0" "sidt\0" "skinit\0" "sldt\0"
+ "slwpcb\0" "smsw\0" "stac\0" "stc\0" "stgi\0" "sti\0" "stos\0" "str\0" "sttilecfg\0" "swapgs\0" "syscall\0"
+ "sysenter\0" "sysexit\0" "sysexit64\0" "sysret\0" "sysret64\0" "t1mskc\0" "tdpbf16ps\0" "tdpbssd\0" "tdpbsud\0"
+ "tdpbusd\0" "tdpbuud\0" "tileloadd\0" "tileloaddt1\0" "tilerelease\0" "tilestored\0" "tilezero\0" "tpause\0"
+ "tzcnt\0" "tzmsk\0" "ud2\0" "umonitor\0" "umwait\0" "v4fmaddps\0" "v4fmaddss\0" "v4fnmaddps\0" "v4fnmaddss\0"
+ "vaddpd\0" "vaddps\0" "vaddsd\0" "vaddss\0" "vaddsubpd\0" "vaddsubps\0" "vaesdec\0" "vaesdeclast\0" "vaesenc\0"
+ "vaesenclast\0" "vaesimc\0" "vaeskeygenassist\0" "valignd\0" "valignq\0" "vandnpd\0" "vandnps\0" "vandpd\0"
+ "vandps\0" "vblendmb\0" "vblendmd\0" "vblendmpd\0" "vblendmps\0" "vblendmq\0" "vblendmw\0" "vblendpd\0" "vblendps\0"
+ "vblendvpd\0" "vblendvps\0" "vbroadcastf128\0" "vbroadcastf32x2\0" "vbroadcastf32x4\0" "vbroadcastf32x8\0"
+ "vbroadcastf64x2\0" "vbroadcastf64x4\0" "vbroadcasti128\0" "vbroadcasti32x2\0" "vbroadcasti32x4\0"
+ "vbroadcasti32x8\0" "vbroadcasti64x2\0" "vbroadcasti64x4\0" "vbroadcastsd\0" "vbroadcastss\0" "vcmppd\0" "vcmpps\0"
+ "vcmpsd\0" "vcmpss\0" "vcomisd\0" "vcomiss\0" "vcompresspd\0" "vcompressps\0" "vcvtdq2pd\0" "vcvtdq2ps\0"
+ "vcvtne2ps2bf16\0" "vcvtneps2bf16\0" "vcvtpd2dq\0" "vcvtpd2ps\0" "vcvtpd2qq\0" "vcvtpd2udq\0" "vcvtpd2uqq\0"
+ "vcvtph2ps\0" "vcvtps2dq\0" "vcvtps2pd\0" "vcvtps2ph\0" "vcvtps2qq\0" "vcvtps2udq\0" "vcvtps2uqq\0" "vcvtqq2pd\0"
+ "vcvtqq2ps\0" "vcvtsd2si\0" "vcvtsd2ss\0" "vcvtsd2usi\0" "vcvtsi2sd\0" "vcvtsi2ss\0" "vcvtss2sd\0" "vcvtss2si\0"
+ "vcvtss2usi\0" "vcvttpd2dq\0" "vcvttpd2qq\0" "vcvttpd2udq\0" "vcvttpd2uqq\0" "vcvttps2dq\0" "vcvttps2qq\0"
+ "vcvttps2udq\0" "vcvttps2uqq\0" "vcvttsd2si\0" "vcvttsd2usi\0" "vcvttss2si\0" "vcvttss2usi\0" "vcvtudq2pd\0"
+ "vcvtudq2ps\0" "vcvtuqq2pd\0" "vcvtuqq2ps\0" "vcvtusi2sd\0" "vcvtusi2ss\0" "vdbpsadbw\0" "vdivpd\0" "vdivps\0"
+ "vdivsd\0" "vdivss\0" "vdpbf16ps\0" "vdppd\0" "vdpps\0" "verr\0" "verw\0" "vexp2pd\0" "vexp2ps\0" "vexpandpd\0"
+ "vexpandps\0" "vextractf128\0" "vextractf32x4\0" "vextractf32x8\0" "vextractf64x2\0" "vextractf64x4\0"
+ "vextracti128\0" "vextracti32x4\0" "vextracti32x8\0" "vextracti64x2\0" "vextracti64x4\0" "vextractps\0"
+ "vfixupimmpd\0" "vfixupimmps\0" "vfixupimmsd\0" "vfixupimmss\0" "vfmadd132pd\0" "vfmadd132ps\0" "vfmadd132sd\0"
+ "vfmadd132ss\0" "vfmadd213pd\0" "vfmadd213ps\0" "vfmadd213sd\0" "vfmadd213ss\0" "vfmadd231pd\0" "vfmadd231ps\0"
+ "vfmadd231sd\0" "vfmadd231ss\0" "vfmaddpd\0" "vfmaddps\0" "vfmaddsd\0" "vfmaddss\0" "vfmaddsub132pd\0"
+ "vfmaddsub132ps\0" "vfmaddsub213pd\0" "vfmaddsub213ps\0" "vfmaddsub231pd\0" "vfmaddsub231ps\0" "vfmaddsubpd\0"
+ "vfmaddsubps\0" "vfmsub132pd\0" "vfmsub132ps\0" "vfmsub132sd\0" "vfmsub132ss\0" "vfmsub213pd\0" "vfmsub213ps\0"
+ "vfmsub213sd\0" "vfmsub213ss\0" "vfmsub231pd\0" "vfmsub231ps\0" "vfmsub231sd\0" "vfmsub231ss\0" "vfmsubadd132pd\0"
+ "vfmsubadd132ps\0" "vfmsubadd213pd\0" "vfmsubadd213ps\0" "vfmsubadd231pd\0" "vfmsubadd231ps\0" "vfmsubaddpd\0"
+ "vfmsubaddps\0" "vfmsubpd\0" "vfmsubps\0" "vfmsubsd\0" "vfmsubss\0" "vfnmadd132pd\0" "vfnmadd132ps\0"
+ "vfnmadd132sd\0" "vfnmadd132ss\0" "vfnmadd213pd\0" "vfnmadd213ps\0" "vfnmadd213sd\0" "vfnmadd213ss\0"
+ "vfnmadd231pd\0" "vfnmadd231ps\0" "vfnmadd231sd\0" "vfnmadd231ss\0" "vfnmaddpd\0" "vfnmaddps\0" "vfnmaddsd\0"
+ "vfnmaddss\0" "vfnmsub132pd\0" "vfnmsub132ps\0" "vfnmsub132sd\0" "vfnmsub132ss\0" "vfnmsub213pd\0" "vfnmsub213ps\0"
+ "vfnmsub213sd\0" "vfnmsub213ss\0" "vfnmsub231pd\0" "vfnmsub231ps\0" "vfnmsub231sd\0" "vfnmsub231ss\0" "vfnmsubpd\0"
+ "vfnmsubps\0" "vfnmsubsd\0" "vfnmsubss\0" "vfpclasspd\0" "vfpclassps\0" "vfpclasssd\0" "vfpclassss\0" "vfrczpd\0"
+ "vfrczps\0" "vfrczsd\0" "vfrczss\0" "vgatherdpd\0" "vgatherdps\0" "vgatherpf0dpd\0" "vgatherpf0dps\0"
+ "vgatherpf0qpd\0" "vgatherpf0qps\0" "vgatherpf1dpd\0" "vgatherpf1dps\0" "vgatherpf1qpd\0" "vgatherpf1qps\0"
+ "vgatherqpd\0" "vgatherqps\0" "vgetexppd\0" "vgetexpps\0" "vgetexpsd\0" "vgetexpss\0" "vgetmantpd\0" "vgetmantps\0"
+ "vgetmantsd\0" "vgetmantss\0" "vgf2p8affineinvqb\0" "vgf2p8affineqb\0" "vgf2p8mulb\0" "vhaddpd\0" "vhaddps\0"
+ "vhsubpd\0" "vhsubps\0" "vinsertf128\0" "vinsertf32x4\0" "vinsertf32x8\0" "vinsertf64x2\0" "vinsertf64x4\0"
+ "vinserti128\0" "vinserti32x4\0" "vinserti32x8\0" "vinserti64x2\0" "vinserti64x4\0" "vinsertps\0" "vlddqu\0"
+ "vldmxcsr\0" "vmaskmovdqu\0" "vmaskmovpd\0" "vmaskmovps\0" "vmaxpd\0" "vmaxps\0" "vmaxsd\0" "vmaxss\0" "vmcall\0"
+ "vmclear\0" "vmfunc\0" "vminpd\0" "vminps\0" "vminsd\0" "vminss\0" "vmlaunch\0" "vmload\0" "vmmcall\0" "vmovapd\0"
+ "vmovaps\0" "vmovd\0" "vmovddup\0" "vmovdqa\0" "vmovdqa32\0" "vmovdqa64\0" "vmovdqu\0" "vmovdqu16\0" "vmovdqu32\0"
+ "vmovdqu64\0" "vmovdqu8\0" "vmovhlps\0" "vmovhpd\0" "vmovhps\0" "vmovlhps\0" "vmovlpd\0" "vmovlps\0" "vmovmskpd\0"
+ "vmovmskps\0" "vmovntdq\0" "vmovntdqa\0" "vmovntpd\0" "vmovntps\0" "vmovq\0" "vmovsd\0" "vmovshdup\0" "vmovsldup\0"
+ "vmovss\0" "vmovupd\0" "vmovups\0" "vmpsadbw\0" "vmptrld\0" "vmptrst\0" "vmread\0" "vmresume\0" "vmrun\0" "vmsave\0"
+ "vmulpd\0" "vmulps\0" "vmulsd\0" "vmulss\0" "vmwrite\0" "vmxon\0" "vorpd\0" "vorps\0" "vp2intersectd\0"
+ "vp2intersectq\0" "vp4dpwssd\0" "vp4dpwssds\0" "vpabsb\0" "vpabsd\0" "vpabsq\0" "vpabsw\0" "vpackssdw\0"
"vpacksswb\0" "vpackusdw\0" "vpackuswb\0" "vpaddb\0" "vpaddd\0" "vpaddq\0" "vpaddsb\0" "vpaddsw\0" "vpaddusb\0"
"vpaddusw\0" "vpaddw\0" "vpalignr\0" "vpand\0" "vpandd\0" "vpandn\0" "vpandnd\0" "vpandnq\0" "vpandq\0" "vpavgb\0"
"vpavgw\0" "vpblendd\0" "vpblendvb\0" "vpblendw\0" "vpbroadcastb\0" "vpbroadcastd\0" "vpbroadcastmb2d\0"
@@ -2727,8 +2786,8 @@ const char InstDB::_nameData[] =
"vstmxcsr\0" "vsubpd\0" "vsubps\0" "vsubsd\0" "vsubss\0" "vtestpd\0" "vtestps\0" "vucomisd\0" "vucomiss\0"
"vunpckhpd\0" "vunpckhps\0" "vunpcklpd\0" "vunpcklps\0" "vxorpd\0" "vxorps\0" "vzeroall\0" "vzeroupper\0" "wbinvd\0"
"wbnoinvd\0" "wrfsbase\0" "wrgsbase\0" "wrmsr\0" "xabort\0" "xadd\0" "xbegin\0" "xend\0" "xgetbv\0" "xlatb\0"
- "xrstors\0" "xrstors64\0" "xsavec\0" "xsavec64\0" "xsaveopt\0" "xsaveopt64\0" "xsaves\0" "xsaves64\0" "xsetbv\0"
- "xtest";
+ "xresldtrk\0" "xrstors\0" "xrstors64\0" "xsavec\0" "xsavec64\0" "xsaveopt\0" "xsaveopt64\0" "xsaves\0" "xsaves64\0"
+ "xsetbv\0" "xsusldtrk\0" "xtest";
const InstDB::InstNameIndex InstDB::instNameIndex[26] = {
{ Inst::kIdAaa , Inst::kIdArpl + 1 },
@@ -2981,264 +3040,275 @@ const InstDB::InstSignature InstDB::_instSignatureTable[] = {
ROW(2, 1, 1, 0, 29 , 45 , 0 , 0 , 0 , 0 ), // #201 {m32|mem, xmm}
ROW(2, 1, 1, 0, 45 , 29 , 0 , 0 , 0 , 0 ), // {xmm, m32|mem}
ROW(3, 1, 1, 0, 45 , 45 , 45 , 0 , 0 , 0 ), // {xmm, xmm, xmm}
- ROW(2, 1, 1, 0, 86 , 85 , 0 , 0 , 0 , 0 ), // #204 {xmm|ymm, xmm|m64|mem|r64}
+ ROW(4, 1, 1, 0, 84 , 84 , 45 , 46 , 0 , 0 ), // #204 {k, k, xmm, xmm|m128|mem}
+ ROW(4, 1, 1, 0, 84 , 84 , 48 , 49 , 0 , 0 ), // {k, k, ymm, ymm|m256|mem}
+ ROW(4, 1, 1, 0, 84 , 84 , 51 , 52 , 0 , 0 ), // {k, k, zmm, zmm|m512|mem}
+ ROW(2, 1, 1, 0, 86 , 85 , 0 , 0 , 0 , 0 ), // #207 {xmm|ymm, xmm|m64|mem|r64}
ROW(2, 0, 1, 0, 51 , 8 , 0 , 0 , 0 , 0 ), // {zmm, r64}
ROW(2, 1, 1, 0, 51 , 60 , 0 , 0 , 0 , 0 ), // {zmm, xmm|m64|mem}
- ROW(4, 1, 1, 0, 84 , 45 , 46 , 10 , 0 , 0 ), // #207 {k, xmm, xmm|m128|mem, i8|u8}
+ ROW(4, 1, 1, 0, 84 , 45 , 46 , 10 , 0 , 0 ), // #210 {k, xmm, xmm|m128|mem, i8|u8}
ROW(4, 1, 1, 0, 84 , 48 , 49 , 10 , 0 , 0 ), // {k, ymm, ymm|m256|mem, i8|u8}
ROW(4, 1, 1, 0, 84 , 51 , 52 , 10 , 0 , 0 ), // {k, zmm, zmm|m512|mem, i8|u8}
- ROW(3, 1, 1, 0, 82 , 45 , 46 , 0 , 0 , 0 ), // #210 {xmm|k, xmm, xmm|m128|mem}
+ ROW(3, 1, 1, 0, 82 , 45 , 46 , 0 , 0 , 0 ), // #213 {xmm|k, xmm, xmm|m128|mem}
ROW(3, 1, 1, 0, 83 , 48 , 49 , 0 , 0 , 0 ), // {ymm|k, ymm, ymm|m256|mem}
ROW(3, 1, 1, 0, 84 , 51 , 52 , 0 , 0 , 0 ), // {k, zmm, zmm|m512|mem}
- ROW(2, 1, 1, 0, 87 , 45 , 0 , 0 , 0 , 0 ), // #213 {xmm|m32|mem, xmm}
+ ROW(2, 1, 1, 0, 87 , 45 , 0 , 0 , 0 , 0 ), // #216 {xmm|m32|mem, xmm}
ROW(2, 1, 1, 0, 60 , 48 , 0 , 0 , 0 , 0 ), // {xmm|m64|mem, ymm}
ROW(2, 1, 1, 0, 46 , 51 , 0 , 0 , 0 , 0 ), // {xmm|m128|mem, zmm}
- ROW(2, 1, 1, 0, 60 , 45 , 0 , 0 , 0 , 0 ), // #216 {xmm|m64|mem, xmm}
+ ROW(2, 1, 1, 0, 60 , 45 , 0 , 0 , 0 , 0 ), // #219 {xmm|m64|mem, xmm}
ROW(2, 1, 1, 0, 46 , 48 , 0 , 0 , 0 , 0 ), // {xmm|m128|mem, ymm}
ROW(2, 1, 1, 0, 49 , 51 , 0 , 0 , 0 , 0 ), // {ymm|m256|mem, zmm}
- ROW(2, 1, 1, 0, 88 , 45 , 0 , 0 , 0 , 0 ), // #219 {xmm|m16|mem, xmm}
+ ROW(2, 1, 1, 0, 88 , 45 , 0 , 0 , 0 , 0 ), // #222 {xmm|m16|mem, xmm}
ROW(2, 1, 1, 0, 87 , 48 , 0 , 0 , 0 , 0 ), // {xmm|m32|mem, ymm}
ROW(2, 1, 1, 0, 60 , 51 , 0 , 0 , 0 , 0 ), // {xmm|m64|mem, zmm}
- ROW(2, 1, 1, 0, 45 , 87 , 0 , 0 , 0 , 0 ), // #222 {xmm, xmm|m32|mem}
+ ROW(2, 1, 1, 0, 45 , 87 , 0 , 0 , 0 , 0 ), // #225 {xmm, xmm|m32|mem}
ROW(2, 1, 1, 0, 48 , 60 , 0 , 0 , 0 , 0 ), // {ymm, xmm|m64|mem}
ROW(2, 1, 1, 0, 51 , 46 , 0 , 0 , 0 , 0 ), // {zmm, xmm|m128|mem}
- ROW(2, 1, 1, 0, 45 , 88 , 0 , 0 , 0 , 0 ), // #225 {xmm, xmm|m16|mem}
+ ROW(2, 1, 1, 0, 45 , 88 , 0 , 0 , 0 , 0 ), // #228 {xmm, xmm|m16|mem}
ROW(2, 1, 1, 0, 48 , 87 , 0 , 0 , 0 , 0 ), // {ymm, xmm|m32|mem}
ROW(2, 1, 1, 0, 51 , 60 , 0 , 0 , 0 , 0 ), // {zmm, xmm|m64|mem}
- ROW(2, 1, 1, 0, 61 , 45 , 0 , 0 , 0 , 0 ), // #228 {vm32x, xmm}
+ ROW(2, 1, 1, 0, 61 , 45 , 0 , 0 , 0 , 0 ), // #231 {vm32x, xmm}
ROW(2, 1, 1, 0, 62 , 48 , 0 , 0 , 0 , 0 ), // {vm32y, ymm}
ROW(2, 1, 1, 0, 63 , 51 , 0 , 0 , 0 , 0 ), // {vm32z, zmm}
- ROW(2, 1, 1, 0, 64 , 45 , 0 , 0 , 0 , 0 ), // #231 {vm64x, xmm}
+ ROW(2, 1, 1, 0, 64 , 45 , 0 , 0 , 0 , 0 ), // #234 {vm64x, xmm}
ROW(2, 1, 1, 0, 65 , 48 , 0 , 0 , 0 , 0 ), // {vm64y, ymm}
ROW(2, 1, 1, 0, 66 , 51 , 0 , 0 , 0 , 0 ), // {vm64z, zmm}
- ROW(3, 1, 1, 0, 84 , 45 , 46 , 0 , 0 , 0 ), // #234 {k, xmm, xmm|m128|mem}
+ ROW(3, 1, 1, 0, 84 , 45 , 46 , 0 , 0 , 0 ), // #237 {k, xmm, xmm|m128|mem}
ROW(3, 1, 1, 0, 84 , 48 , 49 , 0 , 0 , 0 ), // {k, ymm, ymm|m256|mem}
ROW(3, 1, 1, 0, 84 , 51 , 52 , 0 , 0 , 0 ), // {k, zmm, zmm|m512|mem}
- ROW(3, 1, 1, 0, 6 , 6 , 28 , 0 , 0 , 0 ), // #237 {r32, r32, r32|m32|mem}
+ ROW(3, 1, 1, 0, 6 , 6 , 28 , 0 , 0 , 0 ), // #240 {r32, r32, r32|m32|mem}
ROW(3, 0, 1, 0, 8 , 8 , 15 , 0 , 0 , 0 ), // {r64, r64, r64|m64|mem}
- ROW(3, 1, 1, 0, 6 , 28 , 6 , 0 , 0 , 0 ), // #239 {r32, r32|m32|mem, r32}
+ ROW(3, 1, 1, 0, 6 , 28 , 6 , 0 , 0 , 0 ), // #242 {r32, r32|m32|mem, r32}
ROW(3, 0, 1, 0, 8 , 15 , 8 , 0 , 0 , 0 ), // {r64, r64|m64|mem, r64}
- ROW(2, 1, 0, 0, 89 , 28 , 0 , 0 , 0 , 0 ), // #241 {bnd, r32|m32|mem}
+ ROW(2, 1, 0, 0, 89 , 28 , 0 , 0 , 0 , 0 ), // #244 {bnd, r32|m32|mem}
ROW(2, 0, 1, 0, 89 , 15 , 0 , 0 , 0 , 0 ), // {bnd, r64|m64|mem}
- ROW(2, 1, 1, 0, 89 , 90 , 0 , 0 , 0 , 0 ), // #243 {bnd, bnd|mem}
+ ROW(2, 1, 1, 0, 89 , 90 , 0 , 0 , 0 , 0 ), // #246 {bnd, bnd|mem}
ROW(2, 1, 1, 0, 91 , 89 , 0 , 0 , 0 , 0 ), // {mem, bnd}
- ROW(2, 1, 0, 0, 4 , 29 , 0 , 0 , 0 , 0 ), // #245 {r16, m32|mem}
+ ROW(2, 1, 0, 0, 4 , 29 , 0 , 0 , 0 , 0 ), // #248 {r16, m32|mem}
ROW(2, 1, 0, 0, 6 , 30 , 0 , 0 , 0 , 0 ), // {r32, m64|mem}
- ROW(1, 1, 0, 0, 92 , 0 , 0 , 0 , 0 , 0 ), // #247 {rel16|r16|m16|r32|m32}
+ ROW(1, 1, 0, 0, 92 , 0 , 0 , 0 , 0 , 0 ), // #250 {rel16|r16|m16|r32|m32}
ROW(1, 1, 1, 0, 93 , 0 , 0 , 0 , 0 , 0 ), // {rel32|r64|m64|mem}
- ROW(2, 1, 1, 0, 6 , 94 , 0 , 0 , 0 , 0 ), // #249 {r32, r8lo|r8hi|m8|r16|m16|r32|m32}
+ ROW(2, 1, 1, 0, 6 , 94 , 0 , 0 , 0 , 0 ), // #252 {r32, r8lo|r8hi|m8|r16|m16|r32|m32}
ROW(2, 0, 1, 0, 8 , 95 , 0 , 0 , 0 , 0 ), // {r64, r8lo|r8hi|m8|r64|m64}
- ROW(1, 1, 0, 0, 96 , 0 , 0 , 0 , 0 , 0 ), // #251 {r16|r32}
- ROW(1, 1, 1, 0, 31 , 0 , 0 , 0 , 0 , 0 ), // #252 {r8lo|r8hi|m8|r16|m16|r32|m32|r64|m64|mem}
- ROW(2, 1, 0, 0, 97 , 53 , 0 , 0 , 0 , 0 ), // #253 {es:[memBase], m512|mem}
+ ROW(1, 1, 0, 0, 96 , 0 , 0 , 0 , 0 , 0 ), // #254 {r16|r32}
+ ROW(1, 1, 1, 0, 31 , 0 , 0 , 0 , 0 , 0 ), // #255 {r8lo|r8hi|m8|r16|m16|r32|m32|r64|m64|mem}
+ ROW(2, 1, 0, 0, 97 , 53 , 0 , 0 , 0 , 0 ), // #256 {es:[memBase], m512|mem}
ROW(2, 0, 1, 0, 97 , 53 , 0 , 0 , 0 , 0 ), // {es:[memBase], m512|mem}
- ROW(3, 1, 1, 0, 45 , 10 , 10 , 0 , 0 , 0 ), // #255 {xmm, i8|u8, i8|u8}
- ROW(2, 1, 1, 0, 45 , 45 , 0 , 0 , 0 , 0 ), // #256 {xmm, xmm}
- ROW(0, 1, 1, 0, 0 , 0 , 0 , 0 , 0 , 0 ), // #257 {}
- ROW(1, 1, 1, 0, 78 , 0 , 0 , 0 , 0 , 0 ), // #258 {st}
- ROW(0, 1, 1, 0, 0 , 0 , 0 , 0 , 0 , 0 ), // #259 {}
- ROW(1, 1, 1, 0, 98 , 0 , 0 , 0 , 0 , 0 ), // #260 {m32|m64|st}
- ROW(2, 1, 1, 0, 45 , 45 , 0 , 0 , 0 , 0 ), // #261 {xmm, xmm}
+ ROW(3, 1, 1, 0, 45 , 10 , 10 , 0 , 0 , 0 ), // #258 {xmm, i8|u8, i8|u8}
+ ROW(2, 1, 1, 0, 45 , 45 , 0 , 0 , 0 , 0 ), // #259 {xmm, xmm}
+ ROW(0, 1, 1, 0, 0 , 0 , 0 , 0 , 0 , 0 ), // #260 {}
+ ROW(1, 1, 1, 0, 78 , 0 , 0 , 0 , 0 , 0 ), // #261 {st}
+ ROW(0, 1, 1, 0, 0 , 0 , 0 , 0 , 0 , 0 ), // #262 {}
+ ROW(1, 1, 1, 0, 98 , 0 , 0 , 0 , 0 , 0 ), // #263 {m32|m64|st}
+ ROW(2, 1, 1, 0, 45 , 45 , 0 , 0 , 0 , 0 ), // #264 {xmm, xmm}
ROW(4, 1, 1, 0, 45 , 45 , 10 , 10 , 0 , 0 ), // {xmm, xmm, i8|u8, i8|u8}
- ROW(2, 1, 0, 0, 6 , 47 , 0 , 0 , 0 , 0 ), // #263 {r32, m128|mem}
+ ROW(2, 1, 0, 0, 6 , 47 , 0 , 0 , 0 , 0 ), // #266 {r32, m128|mem}
ROW(2, 0, 1, 0, 8 , 47 , 0 , 0 , 0 , 0 ), // {r64, m128|mem}
- ROW(2, 1, 0, 2, 36 , 99 , 0 , 0 , 0 , 0 ), // #265 {<eax>, <ecx>}
+ ROW(2, 1, 0, 2, 36 , 99 , 0 , 0 , 0 , 0 ), // #268 {<eax>, <ecx>}
ROW(2, 0, 1, 2, 100, 99 , 0 , 0 , 0 , 0 ), // {<eax|rax>, <ecx>}
- ROW(1, 1, 1, 0, 101, 0 , 0 , 0 , 0 , 0 ), // #267 {rel8|rel32}
+ ROW(1, 1, 1, 0, 101, 0 , 0 , 0 , 0 , 0 ), // #270 {rel8|rel32}
ROW(1, 1, 0, 0, 102, 0 , 0 , 0 , 0 , 0 ), // {rel16}
- ROW(2, 1, 0, 1, 103, 104, 0 , 0 , 0 , 0 ), // #269 {<cx|ecx>, rel8}
+ ROW(2, 1, 0, 1, 103, 104, 0 , 0 , 0 , 0 ), // #272 {<cx|ecx>, rel8}
ROW(2, 0, 1, 1, 105, 104, 0 , 0 , 0 , 0 ), // {<ecx|rcx>, rel8}
- ROW(1, 1, 1, 0, 106, 0 , 0 , 0 , 0 , 0 ), // #271 {rel8|rel32|r64|m64|mem}
+ ROW(1, 1, 1, 0, 106, 0 , 0 , 0 , 0 , 0 ), // #274 {rel8|rel32|r64|m64|mem}
ROW(1, 1, 0, 0, 107, 0 , 0 , 0 , 0 , 0 ), // {rel16|r32|m32|mem}
- ROW(2, 1, 1, 0, 84 , 108, 0 , 0 , 0 , 0 ), // #273 {k, k|m8|mem|r32|r8lo|r8hi|r16}
+ ROW(2, 1, 1, 0, 84 , 108, 0 , 0 , 0 , 0 ), // #276 {k, k|m8|mem|r32|r8lo|r8hi|r16}
ROW(2, 1, 1, 0, 109, 84 , 0 , 0 , 0 , 0 ), // {m8|mem|r32|r8lo|r8hi|r16, k}
- ROW(2, 1, 1, 0, 84 , 110, 0 , 0 , 0 , 0 ), // #275 {k, k|m32|mem|r32}
+ ROW(2, 1, 1, 0, 84 , 110, 0 , 0 , 0 , 0 ), // #278 {k, k|m32|mem|r32}
ROW(2, 1, 1, 0, 28 , 84 , 0 , 0 , 0 , 0 ), // {m32|mem|r32, k}
- ROW(2, 1, 1, 0, 84 , 111, 0 , 0 , 0 , 0 ), // #277 {k, k|m64|mem|r64}
+ ROW(2, 1, 1, 0, 84 , 111, 0 , 0 , 0 , 0 ), // #280 {k, k|m64|mem|r64}
ROW(2, 1, 1, 0, 15 , 84 , 0 , 0 , 0 , 0 ), // {m64|mem|r64, k}
- ROW(2, 1, 1, 0, 84 , 112, 0 , 0 , 0 , 0 ), // #279 {k, k|m16|mem|r32|r16}
+ ROW(2, 1, 1, 0, 84 , 112, 0 , 0 , 0 , 0 ), // #282 {k, k|m16|mem|r32|r16}
ROW(2, 1, 1, 0, 113, 84 , 0 , 0 , 0 , 0 ), // {m16|mem|r32|r16, k}
- ROW(2, 1, 1, 0, 4 , 27 , 0 , 0 , 0 , 0 ), // #281 {r16, r16|m16|mem}
+ ROW(2, 1, 1, 0, 4 , 27 , 0 , 0 , 0 , 0 ), // #284 {r16, r16|m16|mem}
ROW(2, 1, 1, 0, 6 , 113, 0 , 0 , 0 , 0 ), // {r32, r32|m16|mem|r16}
- ROW(2, 1, 0, 0, 4 , 29 , 0 , 0 , 0 , 0 ), // #283 {r16, m32|mem}
+ ROW(2, 1, 0, 0, 4 , 29 , 0 , 0 , 0 , 0 ), // #286 {r16, m32|mem}
ROW(2, 1, 0, 0, 6 , 79 , 0 , 0 , 0 , 0 ), // {r32, m48|mem}
- ROW(2, 1, 1, 0, 4 , 27 , 0 , 0 , 0 , 0 ), // #285 {r16, r16|m16|mem}
+ ROW(2, 1, 1, 0, 4 , 27 , 0 , 0 , 0 , 0 ), // #288 {r16, r16|m16|mem}
ROW(2, 1, 1, 0, 114, 113, 0 , 0 , 0 , 0 ), // {r32|r64, r32|m16|mem|r16}
- ROW(2, 1, 1, 0, 59 , 28 , 0 , 0 , 0 , 0 ), // #287 {mm|xmm, r32|m32|mem}
+ ROW(2, 1, 1, 0, 59 , 28 , 0 , 0 , 0 , 0 ), // #290 {mm|xmm, r32|m32|mem}
ROW(2, 1, 1, 0, 28 , 59 , 0 , 0 , 0 , 0 ), // {r32|m32|mem, mm|xmm}
- ROW(2, 1, 1, 0, 45 , 87 , 0 , 0 , 0 , 0 ), // #289 {xmm, xmm|m32|mem}
+ ROW(2, 1, 1, 0, 45 , 87 , 0 , 0 , 0 , 0 ), // #292 {xmm, xmm|m32|mem}
ROW(2, 1, 1, 0, 29 , 45 , 0 , 0 , 0 , 0 ), // {m32|mem, xmm}
- ROW(2, 1, 1, 0, 4 , 9 , 0 , 0 , 0 , 0 ), // #291 {r16, r8lo|r8hi|m8}
+ ROW(2, 1, 1, 0, 4 , 9 , 0 , 0 , 0 , 0 ), // #294 {r16, r8lo|r8hi|m8}
ROW(2, 1, 1, 0, 114, 115, 0 , 0 , 0 , 0 ), // {r32|r64, r8lo|r8hi|m8|r16|m16}
- ROW(2, 0, 1, 0, 4 , 27 , 0 , 0 , 0 , 0 ), // #293 {r16, r16|m16|mem}
+ ROW(2, 0, 1, 0, 4 , 27 , 0 , 0 , 0 , 0 ), // #296 {r16, r16|m16|mem}
ROW(2, 0, 1, 0, 114, 28 , 0 , 0 , 0 , 0 ), // {r32|r64, r32|m32|mem}
- ROW(4, 1, 1, 1, 6 , 6 , 28 , 35 , 0 , 0 ), // #295 {r32, r32, r32|m32|mem, <edx>}
+ ROW(4, 1, 1, 1, 6 , 6 , 28 , 35 , 0 , 0 ), // #298 {r32, r32, r32|m32|mem, <edx>}
ROW(4, 0, 1, 1, 8 , 8 , 15 , 37 , 0 , 0 ), // {r64, r64, r64|m64|mem, <rdx>}
- ROW(0, 1, 1, 0, 0 , 0 , 0 , 0 , 0 , 0 ), // #297 {}
+ ROW(0, 1, 1, 0, 0 , 0 , 0 , 0 , 0 , 0 ), // #300 {}
ROW(1, 1, 1, 0, 116, 0 , 0 , 0 , 0 , 0 ), // {r16|m16|r32|m32}
- ROW(2, 1, 1, 0, 57 , 117, 0 , 0 , 0 , 0 ), // #299 {mm, mm|m64|mem}
+ ROW(2, 1, 1, 0, 57 , 117, 0 , 0 , 0 , 0 ), // #302 {mm, mm|m64|mem}
ROW(2, 1, 1, 0, 45 , 46 , 0 , 0 , 0 , 0 ), // {xmm, xmm|m128|mem}
- ROW(3, 1, 1, 0, 57 , 117, 10 , 0 , 0 , 0 ), // #301 {mm, mm|m64|mem, i8|u8}
+ ROW(3, 1, 1, 0, 57 , 117, 10 , 0 , 0 , 0 ), // #304 {mm, mm|m64|mem, i8|u8}
ROW(3, 1, 1, 0, 45 , 46 , 10 , 0 , 0 , 0 ), // {xmm, xmm|m128|mem, i8|u8}
- ROW(3, 1, 1, 0, 6 , 59 , 10 , 0 , 0 , 0 ), // #303 {r32, mm|xmm, i8|u8}
+ ROW(3, 1, 1, 0, 6 , 59 , 10 , 0 , 0 , 0 ), // #306 {r32, mm|xmm, i8|u8}
ROW(3, 1, 1, 0, 21 , 45 , 10 , 0 , 0 , 0 ), // {m16|mem, xmm, i8|u8}
- ROW(2, 1, 1, 0, 57 , 118, 0 , 0 , 0 , 0 ), // #305 {mm, i8|u8|mm|m64|mem}
+ ROW(2, 1, 1, 0, 57 , 118, 0 , 0 , 0 , 0 ), // #308 {mm, i8|u8|mm|m64|mem}
ROW(2, 1, 1, 0, 45 , 54 , 0 , 0 , 0 , 0 ), // {xmm, i8|u8|xmm|m128|mem}
- ROW(1, 1, 0, 0, 6 , 0 , 0 , 0 , 0 , 0 ), // #307 {r32}
+ ROW(1, 1, 0, 0, 6 , 0 , 0 , 0 , 0 , 0 ), // #310 {r32}
ROW(1, 0, 1, 0, 8 , 0 , 0 , 0 , 0 , 0 ), // {r64}
- ROW(0, 1, 1, 0, 0 , 0 , 0 , 0 , 0 , 0 ), // #309 {}
+ ROW(0, 1, 1, 0, 0 , 0 , 0 , 0 , 0 , 0 ), // #312 {}
ROW(1, 1, 1, 0, 119, 0 , 0 , 0 , 0 , 0 ), // {u16}
- ROW(3, 1, 1, 0, 6 , 28 , 10 , 0 , 0 , 0 ), // #311 {r32, r32|m32|mem, i8|u8}
+ ROW(3, 1, 1, 0, 6 , 28 , 10 , 0 , 0 , 0 ), // #314 {r32, r32|m32|mem, i8|u8}
ROW(3, 0, 1, 0, 8 , 15 , 10 , 0 , 0 , 0 ), // {r64, r64|m64|mem, i8|u8}
- ROW(4, 1, 1, 0, 45 , 45 , 46 , 45 , 0 , 0 ), // #313 {xmm, xmm, xmm|m128|mem, xmm}
+ ROW(4, 1, 1, 0, 45 , 45 , 46 , 45 , 0 , 0 ), // #316 {xmm, xmm, xmm|m128|mem, xmm}
ROW(4, 1, 1, 0, 48 , 48 , 49 , 48 , 0 , 0 ), // {ymm, ymm, ymm|m256|mem, ymm}
- ROW(2, 1, 1, 0, 45 , 120, 0 , 0 , 0 , 0 ), // #315 {xmm, xmm|m128|ymm|m256}
+ ROW(2, 1, 1, 0, 45 , 120, 0 , 0 , 0 , 0 ), // #318 {xmm, xmm|m128|ymm|m256}
ROW(2, 1, 1, 0, 48 , 52 , 0 , 0 , 0 , 0 ), // {ymm, zmm|m512|mem}
- ROW(4, 1, 1, 0, 45 , 45 , 45 , 60 , 0 , 0 ), // #317 {xmm, xmm, xmm, xmm|m64|mem}
+ ROW(4, 1, 1, 0, 45 , 45 , 45 , 60 , 0 , 0 ), // #320 {xmm, xmm, xmm, xmm|m64|mem}
ROW(4, 1, 1, 0, 45 , 45 , 30 , 45 , 0 , 0 ), // {xmm, xmm, m64|mem, xmm}
- ROW(4, 1, 1, 0, 45 , 45 , 45 , 87 , 0 , 0 ), // #319 {xmm, xmm, xmm, xmm|m32|mem}
+ ROW(4, 1, 1, 0, 45 , 45 , 45 , 87 , 0 , 0 ), // #322 {xmm, xmm, xmm, xmm|m32|mem}
ROW(4, 1, 1, 0, 45 , 45 , 29 , 45 , 0 , 0 ), // {xmm, xmm, m32|mem, xmm}
- ROW(4, 1, 1, 0, 48 , 48 , 46 , 10 , 0 , 0 ), // #321 {ymm, ymm, xmm|m128|mem, i8|u8}
+ ROW(4, 1, 1, 0, 48 , 48 , 46 , 10 , 0 , 0 ), // #324 {ymm, ymm, xmm|m128|mem, i8|u8}
ROW(4, 1, 1, 0, 51 , 51 , 46 , 10 , 0 , 0 ), // {zmm, zmm, xmm|m128|mem, i8|u8}
- ROW(1, 1, 0, 1, 36 , 0 , 0 , 0 , 0 , 0 ), // #323 {<eax>}
- ROW(1, 0, 1, 1, 38 , 0 , 0 , 0 , 0 , 0 ), // #324 {<rax>}
- ROW(2, 1, 1, 0, 28 , 45 , 0 , 0 , 0 , 0 ), // #325 {r32|m32|mem, xmm}
+ ROW(1, 1, 0, 1, 36 , 0 , 0 , 0 , 0 , 0 ), // #326 {<eax>}
+ ROW(1, 0, 1, 1, 38 , 0 , 0 , 0 , 0 , 0 ), // #327 {<rax>}
+ ROW(2, 1, 1, 0, 28 , 45 , 0 , 0 , 0 , 0 ), // #328 {r32|m32|mem, xmm}
ROW(2, 1, 1, 0, 45 , 28 , 0 , 0 , 0 , 0 ), // {xmm, r32|m32|mem}
- ROW(2, 1, 1, 0, 30 , 45 , 0 , 0 , 0 , 0 ), // #327 {m64|mem, xmm}
+ ROW(2, 1, 1, 0, 30 , 45 , 0 , 0 , 0 , 0 ), // #330 {m64|mem, xmm}
ROW(3, 1, 1, 0, 45 , 45 , 30 , 0 , 0 , 0 ), // {xmm, xmm, m64|mem}
- ROW(2, 1, 0, 0, 28 , 6 , 0 , 0 , 0 , 0 ), // #329 {r32|m32|mem, r32}
+ ROW(2, 1, 0, 0, 28 , 6 , 0 , 0 , 0 , 0 ), // #332 {r32|m32|mem, r32}
ROW(2, 0, 1, 0, 15 , 8 , 0 , 0 , 0 , 0 ), // {r64|m64|mem, r64}
- ROW(2, 1, 0, 0, 6 , 28 , 0 , 0 , 0 , 0 ), // #331 {r32, r32|m32|mem}
+ ROW(2, 1, 0, 0, 6 , 28 , 0 , 0 , 0 , 0 ), // #334 {r32, r32|m32|mem}
ROW(2, 0, 1, 0, 8 , 15 , 0 , 0 , 0 , 0 ), // {r64, r64|m64|mem}
- ROW(3, 1, 1, 0, 45 , 45 , 54 , 0 , 0 , 0 ), // #333 {xmm, xmm, xmm|m128|mem|i8|u8}
+ ROW(3, 1, 1, 0, 45 , 45 , 54 , 0 , 0 , 0 ), // #336 {xmm, xmm, xmm|m128|mem|i8|u8}
ROW(3, 1, 1, 0, 45 , 47 , 121, 0 , 0 , 0 ), // {xmm, m128|mem, i8|u8|xmm}
- ROW(2, 1, 1, 0, 74 , 45 , 0 , 0 , 0 , 0 ), // #335 {vm64x|vm64y, xmm}
+ ROW(2, 1, 1, 0, 74 , 45 , 0 , 0 , 0 , 0 ), // #338 {vm64x|vm64y, xmm}
ROW(2, 1, 1, 0, 66 , 48 , 0 , 0 , 0 , 0 ), // {vm64z, ymm}
- ROW(3, 1, 1, 0, 45 , 45 , 46 , 0 , 0 , 0 ), // #337 {xmm, xmm, xmm|m128|mem}
+ ROW(3, 1, 1, 0, 45 , 45 , 46 , 0 , 0 , 0 ), // #340 {xmm, xmm, xmm|m128|mem}
ROW(3, 1, 1, 0, 45 , 47 , 45 , 0 , 0 , 0 ), // {xmm, m128|mem, xmm}
- ROW(2, 1, 1, 0, 61 , 86 , 0 , 0 , 0 , 0 ), // #339 {vm32x, xmm|ymm}
+ ROW(2, 1, 1, 0, 61 , 86 , 0 , 0 , 0 , 0 ), // #342 {vm32x, xmm|ymm}
ROW(2, 1, 1, 0, 62 , 51 , 0 , 0 , 0 , 0 ), // {vm32y, zmm}
- ROW(1, 1, 0, 1, 33 , 0 , 0 , 0 , 0 , 0 ), // #341 {<ax>}
- ROW(2, 1, 0, 1, 33 , 10 , 0 , 0 , 0 , 0 ), // #342 {<ax>, i8|u8}
- ROW(2, 1, 0, 0, 27 , 4 , 0 , 0 , 0 , 0 ), // #343 {r16|m16|mem, r16}
- ROW(3, 1, 1, 1, 45 , 46 , 122, 0 , 0 , 0 ), // #344 {xmm, xmm|m128|mem, <xmm0>}
- ROW(2, 1, 1, 0, 89 , 123, 0 , 0 , 0 , 0 ), // #345 {bnd, mib}
- ROW(2, 1, 1, 0, 89 , 91 , 0 , 0 , 0 , 0 ), // #346 {bnd, mem}
- ROW(2, 1, 1, 0, 123, 89 , 0 , 0 , 0 , 0 ), // #347 {mib, bnd}
- ROW(1, 1, 1, 0, 124, 0 , 0 , 0 , 0 , 0 ), // #348 {r16|r32|r64}
- ROW(1, 1, 1, 1, 33 , 0 , 0 , 0 , 0 , 0 ), // #349 {<ax>}
- ROW(2, 1, 1, 2, 35 , 36 , 0 , 0 , 0 , 0 ), // #350 {<edx>, <eax>}
- ROW(1, 1, 1, 0, 91 , 0 , 0 , 0 , 0 , 0 ), // #351 {mem}
- ROW(1, 1, 1, 1, 125, 0 , 0 , 0 , 0 , 0 ), // #352 {<ds:[memBase|zax]>}
- ROW(2, 1, 1, 2, 126, 127, 0 , 0 , 0 , 0 ), // #353 {<ds:[memBase|zsi]>, <es:[memBase|zdi]>}
- ROW(3, 1, 1, 0, 45 , 60 , 10 , 0 , 0 , 0 ), // #354 {xmm, xmm|m64|mem, i8|u8}
- ROW(3, 1, 1, 0, 45 , 87 , 10 , 0 , 0 , 0 ), // #355 {xmm, xmm|m32|mem, i8|u8}
- ROW(5, 0, 1, 4, 47 , 37 , 38 , 128, 129, 0 ), // #356 {m128|mem, <rdx>, <rax>, <rcx>, <rbx>}
- ROW(5, 1, 1, 4, 30 , 35 , 36 , 99 , 130, 0 ), // #357 {m64|mem, <edx>, <eax>, <ecx>, <ebx>}
- ROW(4, 1, 1, 4, 36 , 130, 99 , 35 , 0 , 0 ), // #358 {<eax>, <ebx>, <ecx>, <edx>}
- ROW(2, 0, 1, 2, 37 , 38 , 0 , 0 , 0 , 0 ), // #359 {<rdx>, <rax>}
- ROW(2, 1, 1, 0, 57 , 46 , 0 , 0 , 0 , 0 ), // #360 {mm, xmm|m128|mem}
- ROW(2, 1, 1, 0, 45 , 117, 0 , 0 , 0 , 0 ), // #361 {xmm, mm|m64|mem}
- ROW(2, 1, 1, 0, 57 , 60 , 0 , 0 , 0 , 0 ), // #362 {mm, xmm|m64|mem}
- ROW(2, 1, 1, 0, 114, 60 , 0 , 0 , 0 , 0 ), // #363 {r32|r64, xmm|m64|mem}
- ROW(2, 1, 1, 0, 45 , 131, 0 , 0 , 0 , 0 ), // #364 {xmm, r32|m32|mem|r64|m64}
- ROW(2, 1, 1, 0, 114, 87 , 0 , 0 , 0 , 0 ), // #365 {r32|r64, xmm|m32|mem}
- ROW(2, 1, 1, 2, 34 , 33 , 0 , 0 , 0 , 0 ), // #366 {<dx>, <ax>}
- ROW(1, 1, 1, 1, 36 , 0 , 0 , 0 , 0 , 0 ), // #367 {<eax>}
- ROW(2, 1, 1, 0, 12 , 10 , 0 , 0 , 0 , 0 ), // #368 {i16|u16, i8|u8}
- ROW(3, 1, 1, 0, 28 , 45 , 10 , 0 , 0 , 0 ), // #369 {r32|m32|mem, xmm, i8|u8}
- ROW(1, 1, 1, 0, 80 , 0 , 0 , 0 , 0 , 0 ), // #370 {m80|mem}
- ROW(1, 1, 1, 0, 132, 0 , 0 , 0 , 0 , 0 ), // #371 {m16|m32}
- ROW(1, 1, 1, 0, 133, 0 , 0 , 0 , 0 , 0 ), // #372 {m16|m32|m64}
- ROW(1, 1, 1, 0, 134, 0 , 0 , 0 , 0 , 0 ), // #373 {m32|m64|m80|st}
- ROW(1, 1, 1, 0, 21 , 0 , 0 , 0 , 0 , 0 ), // #374 {m16|mem}
- ROW(1, 1, 1, 0, 135, 0 , 0 , 0 , 0 , 0 ), // #375 {ax|m16|mem}
- ROW(1, 0, 1, 0, 91 , 0 , 0 , 0 , 0 , 0 ), // #376 {mem}
- ROW(2, 1, 1, 0, 136, 137, 0 , 0 , 0 , 0 ), // #377 {al|ax|eax, i8|u8|dx}
- ROW(2, 1, 1, 0, 138, 139, 0 , 0 , 0 , 0 ), // #378 {es:[memBase|zdi], dx}
- ROW(1, 1, 1, 0, 10 , 0 , 0 , 0 , 0 , 0 ), // #379 {i8|u8}
- ROW(0, 1, 0, 0, 0 , 0 , 0 , 0 , 0 , 0 ), // #380 {}
- ROW(0, 0, 1, 0, 0 , 0 , 0 , 0 , 0 , 0 ), // #381 {}
- ROW(3, 1, 1, 0, 84 , 84 , 84 , 0 , 0 , 0 ), // #382 {k, k, k}
- ROW(2, 1, 1, 0, 84 , 84 , 0 , 0 , 0 , 0 ), // #383 {k, k}
- ROW(3, 1, 1, 0, 84 , 84 , 10 , 0 , 0 , 0 ), // #384 {k, k, i8|u8}
- ROW(1, 1, 1, 1, 140, 0 , 0 , 0 , 0 , 0 ), // #385 {<ah>}
- ROW(1, 1, 1, 0, 29 , 0 , 0 , 0 , 0 , 0 ), // #386 {m32|mem}
- ROW(2, 1, 1, 0, 124, 141, 0 , 0 , 0 , 0 ), // #387 {r16|r32|r64, mem|m8|m16|m32|m48|m64|m80|m128|m256|m512|m1024}
- ROW(1, 1, 1, 0, 27 , 0 , 0 , 0 , 0 , 0 ), // #388 {r16|m16|mem}
- ROW(1, 1, 1, 0, 114, 0 , 0 , 0 , 0 , 0 ), // #389 {r32|r64}
- ROW(2, 1, 1, 2, 142, 126, 0 , 0 , 0 , 0 ), // #390 {<al|ax|eax|rax>, <ds:[memBase|zsi]>}
- ROW(3, 1, 1, 0, 114, 28 , 14 , 0 , 0 , 0 ), // #391 {r32|r64, r32|m32|mem, i32|u32}
- ROW(3, 1, 1, 1, 45 , 45 , 143, 0 , 0 , 0 ), // #392 {xmm, xmm, <ds:[memBase|zdi]>}
- ROW(3, 1, 1, 1, 57 , 57 , 143, 0 , 0 , 0 ), // #393 {mm, mm, <ds:[memBase|zdi]>}
- ROW(3, 1, 1, 3, 125, 99 , 35 , 0 , 0 , 0 ), // #394 {<ds:[memBase|zax]>, <ecx>, <edx>}
- ROW(2, 1, 1, 0, 97 , 53 , 0 , 0 , 0 , 0 ), // #395 {es:[memBase], m512|mem}
- ROW(2, 1, 1, 0, 57 , 45 , 0 , 0 , 0 , 0 ), // #396 {mm, xmm}
- ROW(2, 1, 1, 0, 6 , 45 , 0 , 0 , 0 , 0 ), // #397 {r32, xmm}
- ROW(2, 1, 1, 0, 30 , 57 , 0 , 0 , 0 , 0 ), // #398 {m64|mem, mm}
- ROW(2, 1, 1, 0, 45 , 57 , 0 , 0 , 0 , 0 ), // #399 {xmm, mm}
- ROW(2, 1, 1, 2, 127, 126, 0 , 0 , 0 , 0 ), // #400 {<es:[memBase|zdi]>, <ds:[memBase|zsi]>}
- ROW(2, 1, 1, 2, 36 , 99 , 0 , 0 , 0 , 0 ), // #401 {<eax>, <ecx>}
- ROW(3, 1, 1, 3, 36 , 99 , 130, 0 , 0 , 0 ), // #402 {<eax>, <ecx>, <ebx>}
- ROW(2, 1, 1, 0, 144, 136, 0 , 0 , 0 , 0 ), // #403 {u8|dx, al|ax|eax}
- ROW(2, 1, 1, 0, 139, 145, 0 , 0 , 0 , 0 ), // #404 {dx, ds:[memBase|zsi]}
- ROW(6, 1, 1, 3, 45 , 46 , 10 , 99 , 36 , 35 ), // #405 {xmm, xmm|m128|mem, i8|u8, <ecx>, <eax>, <edx>}
- ROW(6, 1, 1, 3, 45 , 46 , 10 , 122, 36 , 35 ), // #406 {xmm, xmm|m128|mem, i8|u8, <xmm0>, <eax>, <edx>}
- ROW(4, 1, 1, 1, 45 , 46 , 10 , 99 , 0 , 0 ), // #407 {xmm, xmm|m128|mem, i8|u8, <ecx>}
- ROW(4, 1, 1, 1, 45 , 46 , 10 , 122, 0 , 0 ), // #408 {xmm, xmm|m128|mem, i8|u8, <xmm0>}
- ROW(3, 1, 1, 0, 109, 45 , 10 , 0 , 0 , 0 ), // #409 {r32|m8|mem|r8lo|r8hi|r16, xmm, i8|u8}
- ROW(3, 0, 1, 0, 15 , 45 , 10 , 0 , 0 , 0 ), // #410 {r64|m64|mem, xmm, i8|u8}
- ROW(3, 1, 1, 0, 45 , 109, 10 , 0 , 0 , 0 ), // #411 {xmm, r32|m8|mem|r8lo|r8hi|r16, i8|u8}
- ROW(3, 1, 1, 0, 45 , 28 , 10 , 0 , 0 , 0 ), // #412 {xmm, r32|m32|mem, i8|u8}
- ROW(3, 0, 1, 0, 45 , 15 , 10 , 0 , 0 , 0 ), // #413 {xmm, r64|m64|mem, i8|u8}
- ROW(3, 1, 1, 0, 59 , 113, 10 , 0 , 0 , 0 ), // #414 {mm|xmm, r32|m16|mem|r16, i8|u8}
- ROW(2, 1, 1, 0, 6 , 59 , 0 , 0 , 0 , 0 ), // #415 {r32, mm|xmm}
- ROW(2, 1, 1, 0, 45 , 10 , 0 , 0 , 0 , 0 ), // #416 {xmm, i8|u8}
- ROW(2, 1, 1, 0, 31 , 81 , 0 , 0 , 0 , 0 ), // #417 {r8lo|r8hi|m8|r16|m16|r32|m32|r64|m64|mem, cl|i8|u8}
- ROW(1, 0, 1, 0, 114, 0 , 0 , 0 , 0 , 0 ), // #418 {r32|r64}
- ROW(3, 1, 1, 3, 35 , 36 , 99 , 0 , 0 , 0 ), // #419 {<edx>, <eax>, <ecx>}
- ROW(2, 1, 1, 2, 142, 127, 0 , 0 , 0 , 0 ), // #420 {<al|ax|eax|rax>, <es:[memBase|zdi]>}
- ROW(1, 1, 1, 0, 1 , 0 , 0 , 0 , 0 , 0 ), // #421 {r8lo|r8hi|m8|mem}
- ROW(1, 1, 1, 0, 146, 0 , 0 , 0 , 0 , 0 ), // #422 {r16|m16|mem|r32|r64}
- ROW(2, 1, 1, 2, 127, 142, 0 , 0 , 0 , 0 ), // #423 {<es:[memBase|zdi]>, <al|ax|eax|rax>}
- ROW(6, 1, 1, 0, 51 , 51 , 51 , 51 , 51 , 47 ), // #424 {zmm, zmm, zmm, zmm, zmm, m128|mem}
- ROW(6, 1, 1, 0, 45 , 45 , 45 , 45 , 45 , 47 ), // #425 {xmm, xmm, xmm, xmm, xmm, m128|mem}
- ROW(3, 1, 1, 0, 45 , 45 , 60 , 0 , 0 , 0 ), // #426 {xmm, xmm, xmm|m64|mem}
- ROW(3, 1, 1, 0, 45 , 45 , 87 , 0 , 0 , 0 ), // #427 {xmm, xmm, xmm|m32|mem}
- ROW(2, 1, 1, 0, 48 , 47 , 0 , 0 , 0 , 0 ), // #428 {ymm, m128|mem}
- ROW(2, 1, 1, 0, 147, 60 , 0 , 0 , 0 , 0 ), // #429 {ymm|zmm, xmm|m64|mem}
- ROW(2, 1, 1, 0, 147, 47 , 0 , 0 , 0 , 0 ), // #430 {ymm|zmm, m128|mem}
- ROW(2, 1, 1, 0, 51 , 50 , 0 , 0 , 0 , 0 ), // #431 {zmm, m256|mem}
- ROW(2, 1, 1, 0, 148, 60 , 0 , 0 , 0 , 0 ), // #432 {xmm|ymm|zmm, xmm|m64|mem}
- ROW(2, 1, 1, 0, 148, 87 , 0 , 0 , 0 , 0 ), // #433 {xmm|ymm|zmm, m32|mem|xmm}
- ROW(4, 1, 1, 0, 82 , 45 , 60 , 10 , 0 , 0 ), // #434 {xmm|k, xmm, xmm|m64|mem, i8|u8}
- ROW(4, 1, 1, 0, 82 , 45 , 87 , 10 , 0 , 0 ), // #435 {xmm|k, xmm, xmm|m32|mem, i8|u8}
- ROW(3, 1, 1, 0, 45 , 45 , 131, 0 , 0 , 0 ), // #436 {xmm, xmm, r32|m32|mem|r64|m64}
- ROW(3, 1, 1, 0, 46 , 147, 10 , 0 , 0 , 0 ), // #437 {xmm|m128|mem, ymm|zmm, i8|u8}
- ROW(4, 1, 1, 0, 45 , 45 , 60 , 10 , 0 , 0 ), // #438 {xmm, xmm, xmm|m64|mem, i8|u8}
- ROW(4, 1, 1, 0, 45 , 45 , 87 , 10 , 0 , 0 ), // #439 {xmm, xmm, xmm|m32|mem, i8|u8}
- ROW(3, 1, 1, 0, 84 , 149, 10 , 0 , 0 , 0 ), // #440 {k, xmm|m128|ymm|m256|zmm|m512, i8|u8}
- ROW(3, 1, 1, 0, 84 , 60 , 10 , 0 , 0 , 0 ), // #441 {k, xmm|m64|mem, i8|u8}
- ROW(3, 1, 1, 0, 84 , 87 , 10 , 0 , 0 , 0 ), // #442 {k, xmm|m32|mem, i8|u8}
- ROW(1, 1, 1, 0, 62 , 0 , 0 , 0 , 0 , 0 ), // #443 {vm32y}
- ROW(1, 1, 1, 0, 63 , 0 , 0 , 0 , 0 , 0 ), // #444 {vm32z}
- ROW(1, 1, 1, 0, 66 , 0 , 0 , 0 , 0 , 0 ), // #445 {vm64z}
- ROW(4, 1, 1, 0, 51 , 51 , 49 , 10 , 0 , 0 ), // #446 {zmm, zmm, ymm|m256|mem, i8|u8}
- ROW(1, 1, 1, 0, 30 , 0 , 0 , 0 , 0 , 0 ), // #447 {m64|mem}
- ROW(2, 1, 1, 0, 6 , 86 , 0 , 0 , 0 , 0 ), // #448 {r32, xmm|ymm}
- ROW(2, 1, 1, 0, 148, 150, 0 , 0 , 0 , 0 ), // #449 {xmm|ymm|zmm, xmm|m8|mem|r32|r8lo|r8hi|r16}
- ROW(2, 1, 1, 0, 148, 151, 0 , 0 , 0 , 0 ), // #450 {xmm|ymm|zmm, xmm|m32|mem|r32}
- ROW(2, 1, 1, 0, 148, 84 , 0 , 0 , 0 , 0 ), // #451 {xmm|ymm|zmm, k}
- ROW(2, 1, 1, 0, 148, 152, 0 , 0 , 0 , 0 ), // #452 {xmm|ymm|zmm, xmm|m16|mem|r32|r16}
- ROW(3, 1, 1, 0, 113, 45 , 10 , 0 , 0 , 0 ), // #453 {r32|m16|mem|r16, xmm, i8|u8}
- ROW(4, 1, 1, 0, 45 , 45 , 109, 10 , 0 , 0 ), // #454 {xmm, xmm, r32|m8|mem|r8lo|r8hi|r16, i8|u8}
- ROW(4, 1, 1, 0, 45 , 45 , 28 , 10 , 0 , 0 ), // #455 {xmm, xmm, r32|m32|mem, i8|u8}
- ROW(4, 0, 1, 0, 45 , 45 , 15 , 10 , 0 , 0 ), // #456 {xmm, xmm, r64|m64|mem, i8|u8}
- ROW(4, 1, 1, 0, 45 , 45 , 113, 10 , 0 , 0 ), // #457 {xmm, xmm, r32|m16|mem|r16, i8|u8}
- ROW(2, 1, 1, 0, 84 , 148, 0 , 0 , 0 , 0 ), // #458 {k, xmm|ymm|zmm}
- ROW(1, 1, 1, 0, 102, 0 , 0 , 0 , 0 , 0 ), // #459 {rel16|rel32}
- ROW(3, 1, 1, 2, 91 , 35 , 36 , 0 , 0 , 0 ), // #460 {mem, <edx>, <eax>}
- ROW(3, 0, 1, 2, 91 , 35 , 36 , 0 , 0 , 0 ) // #461 {mem, <edx>, <eax>}
+ ROW(1, 1, 0, 1, 33 , 0 , 0 , 0 , 0 , 0 ), // #344 {<ax>}
+ ROW(2, 1, 0, 1, 33 , 10 , 0 , 0 , 0 , 0 ), // #345 {<ax>, i8|u8}
+ ROW(2, 1, 0, 0, 27 , 4 , 0 , 0 , 0 , 0 ), // #346 {r16|m16|mem, r16}
+ ROW(3, 1, 1, 1, 45 , 46 , 122, 0 , 0 , 0 ), // #347 {xmm, xmm|m128|mem, <xmm0>}
+ ROW(2, 1, 1, 0, 89 , 123, 0 , 0 , 0 , 0 ), // #348 {bnd, mib}
+ ROW(2, 1, 1, 0, 89 , 91 , 0 , 0 , 0 , 0 ), // #349 {bnd, mem}
+ ROW(2, 1, 1, 0, 123, 89 , 0 , 0 , 0 , 0 ), // #350 {mib, bnd}
+ ROW(1, 1, 1, 0, 124, 0 , 0 , 0 , 0 , 0 ), // #351 {r16|r32|r64}
+ ROW(1, 1, 1, 1, 33 , 0 , 0 , 0 , 0 , 0 ), // #352 {<ax>}
+ ROW(2, 1, 1, 2, 35 , 36 , 0 , 0 , 0 , 0 ), // #353 {<edx>, <eax>}
+ ROW(1, 1, 1, 0, 91 , 0 , 0 , 0 , 0 , 0 ), // #354 {mem}
+ ROW(1, 1, 1, 1, 125, 0 , 0 , 0 , 0 , 0 ), // #355 {<ds:[memBase|zax]>}
+ ROW(2, 1, 1, 2, 126, 127, 0 , 0 , 0 , 0 ), // #356 {<ds:[memBase|zsi]>, <es:[memBase|zdi]>}
+ ROW(3, 1, 1, 0, 45 , 60 , 10 , 0 , 0 , 0 ), // #357 {xmm, xmm|m64|mem, i8|u8}
+ ROW(3, 1, 1, 0, 45 , 87 , 10 , 0 , 0 , 0 ), // #358 {xmm, xmm|m32|mem, i8|u8}
+ ROW(5, 0, 1, 4, 47 , 37 , 38 , 128, 129, 0 ), // #359 {m128|mem, <rdx>, <rax>, <rcx>, <rbx>}
+ ROW(5, 1, 1, 4, 30 , 35 , 36 , 99 , 130, 0 ), // #360 {m64|mem, <edx>, <eax>, <ecx>, <ebx>}
+ ROW(4, 1, 1, 4, 36 , 130, 99 , 35 , 0 , 0 ), // #361 {<eax>, <ebx>, <ecx>, <edx>}
+ ROW(2, 0, 1, 2, 37 , 38 , 0 , 0 , 0 , 0 ), // #362 {<rdx>, <rax>}
+ ROW(2, 1, 1, 0, 57 , 46 , 0 , 0 , 0 , 0 ), // #363 {mm, xmm|m128|mem}
+ ROW(2, 1, 1, 0, 45 , 117, 0 , 0 , 0 , 0 ), // #364 {xmm, mm|m64|mem}
+ ROW(2, 1, 1, 0, 57 , 60 , 0 , 0 , 0 , 0 ), // #365 {mm, xmm|m64|mem}
+ ROW(2, 1, 1, 0, 114, 60 , 0 , 0 , 0 , 0 ), // #366 {r32|r64, xmm|m64|mem}
+ ROW(2, 1, 1, 0, 45 , 131, 0 , 0 , 0 , 0 ), // #367 {xmm, r32|m32|mem|r64|m64}
+ ROW(2, 1, 1, 0, 114, 87 , 0 , 0 , 0 , 0 ), // #368 {r32|r64, xmm|m32|mem}
+ ROW(2, 1, 1, 2, 34 , 33 , 0 , 0 , 0 , 0 ), // #369 {<dx>, <ax>}
+ ROW(1, 1, 1, 1, 36 , 0 , 0 , 0 , 0 , 0 ), // #370 {<eax>}
+ ROW(2, 1, 1, 0, 12 , 10 , 0 , 0 , 0 , 0 ), // #371 {i16|u16, i8|u8}
+ ROW(3, 1, 1, 0, 28 , 45 , 10 , 0 , 0 , 0 ), // #372 {r32|m32|mem, xmm, i8|u8}
+ ROW(1, 1, 1, 0, 80 , 0 , 0 , 0 , 0 , 0 ), // #373 {m80|mem}
+ ROW(1, 1, 1, 0, 132, 0 , 0 , 0 , 0 , 0 ), // #374 {m16|m32}
+ ROW(1, 1, 1, 0, 133, 0 , 0 , 0 , 0 , 0 ), // #375 {m16|m32|m64}
+ ROW(1, 1, 1, 0, 134, 0 , 0 , 0 , 0 , 0 ), // #376 {m32|m64|m80|st}
+ ROW(1, 1, 1, 0, 21 , 0 , 0 , 0 , 0 , 0 ), // #377 {m16|mem}
+ ROW(1, 1, 1, 0, 135, 0 , 0 , 0 , 0 , 0 ), // #378 {ax|m16|mem}
+ ROW(1, 0, 1, 0, 91 , 0 , 0 , 0 , 0 , 0 ), // #379 {mem}
+ ROW(2, 1, 1, 0, 136, 137, 0 , 0 , 0 , 0 ), // #380 {al|ax|eax, i8|u8|dx}
+ ROW(2, 1, 1, 0, 138, 139, 0 , 0 , 0 , 0 ), // #381 {es:[memBase|zdi], dx}
+ ROW(1, 1, 1, 0, 10 , 0 , 0 , 0 , 0 , 0 ), // #382 {i8|u8}
+ ROW(0, 1, 0, 0, 0 , 0 , 0 , 0 , 0 , 0 ), // #383 {}
+ ROW(0, 0, 1, 0, 0 , 0 , 0 , 0 , 0 , 0 ), // #384 {}
+ ROW(3, 1, 1, 0, 84 , 84 , 84 , 0 , 0 , 0 ), // #385 {k, k, k}
+ ROW(2, 1, 1, 0, 84 , 84 , 0 , 0 , 0 , 0 ), // #386 {k, k}
+ ROW(3, 1, 1, 0, 84 , 84 , 10 , 0 , 0 , 0 ), // #387 {k, k, i8|u8}
+ ROW(1, 1, 1, 1, 140, 0 , 0 , 0 , 0 , 0 ), // #388 {<ah>}
+ ROW(1, 1, 1, 0, 29 , 0 , 0 , 0 , 0 , 0 ), // #389 {m32|mem}
+ ROW(1, 0, 1, 0, 53 , 0 , 0 , 0 , 0 , 0 ), // #390 {m512|mem}
+ ROW(2, 1, 1, 0, 124, 141, 0 , 0 , 0 , 0 ), // #391 {r16|r32|r64, mem|m8|m16|m32|m48|m64|m80|m128|m256|m512|m1024}
+ ROW(1, 1, 1, 0, 27 , 0 , 0 , 0 , 0 , 0 ), // #392 {r16|m16|mem}
+ ROW(1, 1, 1, 0, 114, 0 , 0 , 0 , 0 , 0 ), // #393 {r32|r64}
+ ROW(2, 1, 1, 2, 142, 126, 0 , 0 , 0 , 0 ), // #394 {<al|ax|eax|rax>, <ds:[memBase|zsi]>}
+ ROW(3, 1, 1, 0, 114, 28 , 14 , 0 , 0 , 0 ), // #395 {r32|r64, r32|m32|mem, i32|u32}
+ ROW(3, 1, 1, 1, 45 , 45 , 143, 0 , 0 , 0 ), // #396 {xmm, xmm, <ds:[memBase|zdi]>}
+ ROW(3, 1, 1, 1, 57 , 57 , 143, 0 , 0 , 0 ), // #397 {mm, mm, <ds:[memBase|zdi]>}
+ ROW(3, 1, 1, 3, 125, 99 , 35 , 0 , 0 , 0 ), // #398 {<ds:[memBase|zax]>, <ecx>, <edx>}
+ ROW(2, 1, 1, 0, 97 , 53 , 0 , 0 , 0 , 0 ), // #399 {es:[memBase], m512|mem}
+ ROW(2, 1, 1, 0, 57 , 45 , 0 , 0 , 0 , 0 ), // #400 {mm, xmm}
+ ROW(2, 1, 1, 0, 6 , 45 , 0 , 0 , 0 , 0 ), // #401 {r32, xmm}
+ ROW(2, 1, 1, 0, 30 , 57 , 0 , 0 , 0 , 0 ), // #402 {m64|mem, mm}
+ ROW(2, 1, 1, 0, 45 , 57 , 0 , 0 , 0 , 0 ), // #403 {xmm, mm}
+ ROW(2, 1, 1, 2, 127, 126, 0 , 0 , 0 , 0 ), // #404 {<es:[memBase|zdi]>, <ds:[memBase|zsi]>}
+ ROW(2, 1, 1, 2, 36 , 99 , 0 , 0 , 0 , 0 ), // #405 {<eax>, <ecx>}
+ ROW(3, 1, 1, 3, 36 , 99 , 130, 0 , 0 , 0 ), // #406 {<eax>, <ecx>, <ebx>}
+ ROW(2, 1, 1, 0, 144, 136, 0 , 0 , 0 , 0 ), // #407 {u8|dx, al|ax|eax}
+ ROW(2, 1, 1, 0, 139, 145, 0 , 0 , 0 , 0 ), // #408 {dx, ds:[memBase|zsi]}
+ ROW(6, 1, 1, 3, 45 , 46 , 10 , 99 , 36 , 35 ), // #409 {xmm, xmm|m128|mem, i8|u8, <ecx>, <eax>, <edx>}
+ ROW(6, 1, 1, 3, 45 , 46 , 10 , 122, 36 , 35 ), // #410 {xmm, xmm|m128|mem, i8|u8, <xmm0>, <eax>, <edx>}
+ ROW(4, 1, 1, 1, 45 , 46 , 10 , 99 , 0 , 0 ), // #411 {xmm, xmm|m128|mem, i8|u8, <ecx>}
+ ROW(4, 1, 1, 1, 45 , 46 , 10 , 122, 0 , 0 ), // #412 {xmm, xmm|m128|mem, i8|u8, <xmm0>}
+ ROW(3, 1, 1, 0, 109, 45 , 10 , 0 , 0 , 0 ), // #413 {r32|m8|mem|r8lo|r8hi|r16, xmm, i8|u8}
+ ROW(3, 0, 1, 0, 15 , 45 , 10 , 0 , 0 , 0 ), // #414 {r64|m64|mem, xmm, i8|u8}
+ ROW(3, 1, 1, 0, 45 , 109, 10 , 0 , 0 , 0 ), // #415 {xmm, r32|m8|mem|r8lo|r8hi|r16, i8|u8}
+ ROW(3, 1, 1, 0, 45 , 28 , 10 , 0 , 0 , 0 ), // #416 {xmm, r32|m32|mem, i8|u8}
+ ROW(3, 0, 1, 0, 45 , 15 , 10 , 0 , 0 , 0 ), // #417 {xmm, r64|m64|mem, i8|u8}
+ ROW(3, 1, 1, 0, 59 , 113, 10 , 0 , 0 , 0 ), // #418 {mm|xmm, r32|m16|mem|r16, i8|u8}
+ ROW(2, 1, 1, 0, 6 , 59 , 0 , 0 , 0 , 0 ), // #419 {r32, mm|xmm}
+ ROW(2, 1, 1, 0, 45 , 10 , 0 , 0 , 0 , 0 ), // #420 {xmm, i8|u8}
+ ROW(2, 1, 1, 0, 31 , 81 , 0 , 0 , 0 , 0 ), // #421 {r8lo|r8hi|m8|r16|m16|r32|m32|r64|m64|mem, cl|i8|u8}
+ ROW(1, 0, 1, 0, 114, 0 , 0 , 0 , 0 , 0 ), // #422 {r32|r64}
+ ROW(3, 1, 1, 3, 35 , 36 , 99 , 0 , 0 , 0 ), // #423 {<edx>, <eax>, <ecx>}
+ ROW(3, 1, 1, 3, 99 , 35 , 36 , 0 , 0 , 0 ), // #424 {<ecx>, <edx>, <eax>}
+ ROW(2, 1, 1, 2, 142, 127, 0 , 0 , 0 , 0 ), // #425 {<al|ax|eax|rax>, <es:[memBase|zdi]>}
+ ROW(1, 1, 1, 0, 1 , 0 , 0 , 0 , 0 , 0 ), // #426 {r8lo|r8hi|m8|mem}
+ ROW(1, 1, 1, 0, 146, 0 , 0 , 0 , 0 , 0 ), // #427 {r16|m16|mem|r32|r64}
+ ROW(2, 1, 1, 2, 127, 142, 0 , 0 , 0 , 0 ), // #428 {<es:[memBase|zdi]>, <al|ax|eax|rax>}
+ ROW(3, 0, 1, 0, 147, 147, 147, 0 , 0 , 0 ), // #429 {tmm, tmm, tmm}
+ ROW(2, 0, 1, 0, 147, 91 , 0 , 0 , 0 , 0 ), // #430 {tmm, tmem}
+ ROW(2, 0, 1, 0, 91 , 147, 0 , 0 , 0 , 0 ), // #431 {tmem, tmm}
+ ROW(1, 0, 1, 0, 147, 0 , 0 , 0 , 0 , 0 ), // #432 {tmm}
+ ROW(3, 1, 1, 2, 6 , 35 , 36 , 0 , 0 , 0 ), // #433 {r32, <edx>, <eax>}
+ ROW(1, 1, 1, 0, 148, 0 , 0 , 0 , 0 , 0 ), // #434 {ds:[memBase]}
+ ROW(6, 1, 1, 0, 51 , 51 , 51 , 51 , 51 , 47 ), // #435 {zmm, zmm, zmm, zmm, zmm, m128|mem}
+ ROW(6, 1, 1, 0, 45 , 45 , 45 , 45 , 45 , 47 ), // #436 {xmm, xmm, xmm, xmm, xmm, m128|mem}
+ ROW(3, 1, 1, 0, 45 , 45 , 60 , 0 , 0 , 0 ), // #437 {xmm, xmm, xmm|m64|mem}
+ ROW(3, 1, 1, 0, 45 , 45 , 87 , 0 , 0 , 0 ), // #438 {xmm, xmm, xmm|m32|mem}
+ ROW(2, 1, 1, 0, 48 , 47 , 0 , 0 , 0 , 0 ), // #439 {ymm, m128|mem}
+ ROW(2, 1, 1, 0, 149, 60 , 0 , 0 , 0 , 0 ), // #440 {ymm|zmm, xmm|m64|mem}
+ ROW(2, 1, 1, 0, 149, 47 , 0 , 0 , 0 , 0 ), // #441 {ymm|zmm, m128|mem}
+ ROW(2, 1, 1, 0, 51 , 50 , 0 , 0 , 0 , 0 ), // #442 {zmm, m256|mem}
+ ROW(2, 1, 1, 0, 150, 60 , 0 , 0 , 0 , 0 ), // #443 {xmm|ymm|zmm, xmm|m64|mem}
+ ROW(2, 1, 1, 0, 150, 87 , 0 , 0 , 0 , 0 ), // #444 {xmm|ymm|zmm, m32|mem|xmm}
+ ROW(4, 1, 1, 0, 82 , 45 , 60 , 10 , 0 , 0 ), // #445 {xmm|k, xmm, xmm|m64|mem, i8|u8}
+ ROW(4, 1, 1, 0, 82 , 45 , 87 , 10 , 0 , 0 ), // #446 {xmm|k, xmm, xmm|m32|mem, i8|u8}
+ ROW(3, 1, 1, 0, 45 , 45 , 131, 0 , 0 , 0 ), // #447 {xmm, xmm, r32|m32|mem|r64|m64}
+ ROW(3, 1, 1, 0, 46 , 149, 10 , 0 , 0 , 0 ), // #448 {xmm|m128|mem, ymm|zmm, i8|u8}
+ ROW(4, 1, 1, 0, 45 , 45 , 60 , 10 , 0 , 0 ), // #449 {xmm, xmm, xmm|m64|mem, i8|u8}
+ ROW(4, 1, 1, 0, 45 , 45 , 87 , 10 , 0 , 0 ), // #450 {xmm, xmm, xmm|m32|mem, i8|u8}
+ ROW(3, 1, 1, 0, 84 , 151, 10 , 0 , 0 , 0 ), // #451 {k, xmm|m128|ymm|m256|zmm|m512, i8|u8}
+ ROW(3, 1, 1, 0, 84 , 60 , 10 , 0 , 0 , 0 ), // #452 {k, xmm|m64|mem, i8|u8}
+ ROW(3, 1, 1, 0, 84 , 87 , 10 , 0 , 0 , 0 ), // #453 {k, xmm|m32|mem, i8|u8}
+ ROW(1, 1, 1, 0, 62 , 0 , 0 , 0 , 0 , 0 ), // #454 {vm32y}
+ ROW(1, 1, 1, 0, 63 , 0 , 0 , 0 , 0 , 0 ), // #455 {vm32z}
+ ROW(1, 1, 1, 0, 66 , 0 , 0 , 0 , 0 , 0 ), // #456 {vm64z}
+ ROW(4, 1, 1, 0, 51 , 51 , 49 , 10 , 0 , 0 ), // #457 {zmm, zmm, ymm|m256|mem, i8|u8}
+ ROW(1, 1, 1, 0, 30 , 0 , 0 , 0 , 0 , 0 ), // #458 {m64|mem}
+ ROW(2, 1, 1, 0, 6 , 86 , 0 , 0 , 0 , 0 ), // #459 {r32, xmm|ymm}
+ ROW(2, 1, 1, 0, 150, 152, 0 , 0 , 0 , 0 ), // #460 {xmm|ymm|zmm, xmm|m8|mem|r32|r8lo|r8hi|r16}
+ ROW(2, 1, 1, 0, 150, 153, 0 , 0 , 0 , 0 ), // #461 {xmm|ymm|zmm, xmm|m32|mem|r32}
+ ROW(2, 1, 1, 0, 150, 84 , 0 , 0 , 0 , 0 ), // #462 {xmm|ymm|zmm, k}
+ ROW(2, 1, 1, 0, 150, 154, 0 , 0 , 0 , 0 ), // #463 {xmm|ymm|zmm, xmm|m16|mem|r32|r16}
+ ROW(3, 1, 1, 0, 113, 45 , 10 , 0 , 0 , 0 ), // #464 {r32|m16|mem|r16, xmm, i8|u8}
+ ROW(4, 1, 1, 0, 45 , 45 , 109, 10 , 0 , 0 ), // #465 {xmm, xmm, r32|m8|mem|r8lo|r8hi|r16, i8|u8}
+ ROW(4, 1, 1, 0, 45 , 45 , 28 , 10 , 0 , 0 ), // #466 {xmm, xmm, r32|m32|mem, i8|u8}
+ ROW(4, 0, 1, 0, 45 , 45 , 15 , 10 , 0 , 0 ), // #467 {xmm, xmm, r64|m64|mem, i8|u8}
+ ROW(4, 1, 1, 0, 45 , 45 , 113, 10 , 0 , 0 ), // #468 {xmm, xmm, r32|m16|mem|r16, i8|u8}
+ ROW(2, 1, 1, 0, 84 , 150, 0 , 0 , 0 , 0 ), // #469 {k, xmm|ymm|zmm}
+ ROW(1, 1, 1, 0, 102, 0 , 0 , 0 , 0 , 0 ), // #470 {rel16|rel32}
+ ROW(3, 1, 1, 2, 91 , 35 , 36 , 0 , 0 , 0 ), // #471 {mem, <edx>, <eax>}
+ ROW(3, 0, 1, 2, 91 , 35 , 36 , 0 , 0 , 0 ) // #472 {mem, <edx>, <eax>}
};
#undef ROW
@@ -3393,6 +3463,8 @@ const InstDB::OpSignature InstDB::_opSignatureTable[] = {
ROW(F(Gpw) | F(U8), 0, 0, 0x04),
ROW(F(Mem), M(BaseOnly) | M(Ds), 0, 0x40),
ROW(F(Gpw) | F(Gpd) | F(Gpq) | F(Mem), M(M16) | M(Any), 0, 0x00),
+ ROW(F(Tmm), 0, 0, 0x00),
+ ROW(F(Mem), M(BaseOnly) | M(Ds), 0, 0x00),
ROW(F(Ymm) | F(Zmm), 0, 0, 0x00),
ROW(F(Xmm) | F(Ymm) | F(Zmm), 0, 0, 0x00),
ROW(F(Xmm) | F(Ymm) | F(Zmm) | F(Mem), M(M128) | M(M256) | M(M512), 0, 0x00),
@@ -3413,415 +3485,446 @@ const InstDB::OpSignature InstDB::_opSignatureTable[] = {
// ${InstRWInfoTable:Begin}
// ------------------- Automatically generated, do not edit -------------------
-const uint8_t InstDB::rwInfoIndex[Inst::_kIdCount * 2] = {
- 0, 0, 0, 1, 1, 0, 1, 0, 0, 1, 2, 0, 3, 0, 2, 0, 4, 0, 4, 0, 5, 0, 6, 0, 4, 0,
- 4, 0, 3, 0, 4, 0, 4, 0, 4, 0, 4, 0, 7, 0, 0, 7, 2, 0, 0, 8, 4, 0, 4, 0, 4, 0,
- 4, 0, 9, 0, 0, 10, 11, 0, 11, 0, 11, 0, 11, 0, 11, 0, 0, 4, 0, 4, 0, 12, 0, 12,
- 11, 0, 11, 0, 11, 0, 11, 0, 11, 0, 13, 0, 13, 0, 13, 0, 14, 0, 14, 0, 15, 0,
- 16, 0, 17, 0, 11, 0, 11, 0, 0, 18, 19, 0, 20, 0, 20, 0, 20, 0, 0, 10, 0, 21,
- 0, 1, 22, 0, 0, 23, 0, 0, 0, 0, 0, 0, 0, 24, 0, 24, 0, 24, 0, 0, 0, 0, 0, 0, 0,
- 24, 0, 25, 0, 0, 3, 0, 3, 0, 3, 0, 3, 0, 3, 0, 3, 0, 3, 0, 3, 0, 3, 0, 3, 0,
- 3, 0, 3, 0, 3, 0, 3, 0, 3, 0, 3, 0, 3, 0, 3, 0, 3, 0, 3, 0, 3, 0, 3, 0, 3, 0,
- 3, 0, 3, 0, 3, 0, 3, 0, 3, 0, 3, 0, 3, 0, 26, 0, 0, 4, 0, 4, 27, 0, 0, 5, 0,
- 6, 0, 28, 0, 29, 0, 30, 31, 0, 32, 0, 0, 33, 34, 0, 35, 0, 36, 0, 7, 0, 37, 0,
- 37, 0, 37, 0, 36, 0, 38, 0, 7, 0, 36, 0, 39, 0, 40, 0, 41, 0, 42, 0, 43, 0, 44,
- 0, 45, 0, 37, 0, 37, 0, 7, 0, 39, 0, 40, 0, 45, 0, 46, 0, 0, 47, 0, 1, 0, 1,
- 0, 48, 49, 50, 4, 0, 4, 0, 5, 0, 6, 0, 0, 4, 0, 4, 0, 0, 51, 0, 51, 0, 0, 0,
- 0, 52, 53, 54, 0, 0, 0, 0, 55, 56, 0, 57, 0, 58, 0, 59, 0, 0, 0, 0, 0, 57, 0,
- 57, 0, 57, 0, 57, 0, 57, 0, 57, 0, 57, 0, 57, 0, 60, 0, 61, 0, 61, 0, 60, 0,
- 0, 0, 0, 0, 0, 55, 56, 0, 57, 55, 56, 0, 57, 0, 0, 0, 57, 0, 56, 0, 56, 0, 56,
- 0, 56, 0, 56, 0, 56, 0, 56, 0, 0, 0, 0, 0, 62, 0, 62, 0, 62, 0, 56, 0, 56, 0,
- 60, 0, 0, 0, 63, 0, 24, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 55, 56, 0, 57, 0,
- 0, 0, 0, 0, 0, 0, 64, 0, 65, 0, 64, 0, 66, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 24,
- 0, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 67, 0, 65, 0, 64, 0, 67, 0, 66, 55, 56, 0,
- 57, 55, 56, 0, 57, 0, 0, 0, 61, 0, 61, 0, 61, 0, 61, 0, 0, 0, 0, 0, 0, 0, 57,
- 0, 24, 0, 24, 0, 64, 0, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4, 0, 4, 4, 0, 4, 0,
- 4, 0, 0, 0, 4, 0, 4, 0, 49, 50, 68, 69, 70, 0, 0, 48, 71, 0, 0, 72, 53, 53, 0,
- 0, 0, 0, 0, 0, 0, 0, 73, 0, 0, 24, 74, 0, 73, 0, 73, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 75, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 21, 0,
+const uint8_t InstDB::rwInfoIndexA[Inst::_kIdCount] = {
+ 0, 0, 1, 1, 0, 2, 3, 2, 4, 4, 5, 6, 4, 4, 3, 4, 4, 4, 4, 7, 0, 2, 0, 4, 4, 4,
+ 4, 8, 0, 9, 9, 9, 9, 9, 0, 0, 0, 0, 9, 9, 9, 9, 9, 10, 10, 10, 11, 11, 12, 13,
+ 14, 9, 9, 0, 15, 16, 16, 16, 0, 0, 0, 17, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
+ 3, 3, 3, 3, 3, 18, 0, 0, 19, 0, 0, 0, 0, 0, 20, 21, 0, 22, 23, 24, 7, 25, 25,
+ 25, 24, 26, 7, 24, 27, 28, 29, 30, 31, 32, 33, 25, 25, 7, 27, 28, 33, 34, 0,
+ 0, 0, 0, 35, 4, 4, 5, 6, 0, 0, 0, 36, 36, 0, 0, 37, 0, 0, 38, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 38, 0, 38, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 38, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 38, 0, 38, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4, 4, 4, 0, 4, 4, 35, 39, 40,
+ 0, 41, 0, 37, 0, 0, 0, 0, 42, 0, 43, 42, 42, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 44,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 76, 0, 77, 0, 78, 0, 79, 0, 76, 0,
- 77, 0, 76, 0, 77, 0, 78, 0, 79, 0, 78, 0, 79, 80, 0, 81, 0, 82, 0, 83, 0, 84,
- 0, 85, 0, 86, 0, 87, 0, 0, 76, 0, 77, 0, 78, 88, 0, 89, 0, 90, 0, 91, 0, 0, 79,
- 0, 84, 0, 85, 0, 86, 0, 87, 0, 84, 0, 85, 0, 86, 0, 87, 88, 0, 89, 0, 90, 0,
- 91, 0, 0, 92, 0, 93, 0, 94, 0, 76, 0, 77, 0, 78, 0, 79, 0, 76, 0, 77, 0, 78,
- 0, 79, 0, 95, 96, 0, 97, 0, 0, 98, 99, 0, 100, 0, 0, 0, 99, 0, 0, 0, 99, 0, 0,
- 24, 99, 0, 0, 24, 0, 101, 0, 102, 0, 101, 103, 0, 104, 0, 104, 0, 104, 0, 96,
- 0, 99, 0, 0, 101, 0, 105, 0, 105, 11, 0, 0, 106, 0, 107, 4, 0, 4, 0, 5, 0, 6,
- 0, 0, 0, 4, 0, 4, 0, 5, 0, 6, 0, 0, 108, 0, 108, 109, 0, 110, 0, 110, 0, 111,
- 0, 81, 0, 36, 0, 112, 0, 111, 0, 86, 0, 110, 0, 110, 0, 113, 0, 114, 0, 114,
- 0, 115, 0, 116, 0, 116, 0, 117, 0, 117, 0, 97, 0, 97, 0, 111, 0, 97, 0, 97, 0,
- 116, 0, 116, 0, 118, 0, 82, 0, 86, 0, 119, 0, 82, 0, 7, 0, 7, 0, 81, 0, 120,
- 0, 11, 0, 110, 0, 110, 0, 120, 0, 0, 4, 49, 121, 4, 0, 4, 0, 5, 0, 6, 0, 0, 122,
- 123, 0, 0, 124, 0, 48, 0, 125, 0, 48, 2, 0, 4, 0, 4, 0, 126, 0, 127, 0, 11,
- 0, 11, 0, 11, 0, 3, 0, 3, 0, 4, 0, 3, 0, 3, 0, 3, 0, 3, 0, 3, 0, 3, 0, 3, 0,
- 3, 0, 3, 0, 0, 3, 3, 0, 3, 0, 0, 0, 3, 0, 128, 0, 3, 0, 0, 12, 0, 4, 0, 4, 3,
- 0, 3, 0, 4, 0, 3, 0, 0, 129, 0, 130, 3, 0, 3, 0, 4, 0, 3, 0, 0, 131, 0, 132,
- 0, 0, 0, 8, 0, 8, 0, 133, 0, 52, 0, 134, 0, 135, 39, 0, 39, 0, 128, 0, 128, 0,
- 128, 0, 128, 0, 128, 0, 128, 0, 128, 0, 128, 0, 128, 0, 128, 0, 39, 0, 128, 0,
- 128, 0, 128, 0, 39, 0, 39, 0, 128, 0, 128, 0, 128, 0, 3, 0, 3, 0, 3, 0, 136,
- 0, 3, 0, 3, 0, 3, 0, 39, 0, 39, 0, 0, 137, 0, 72, 0, 138, 0, 139, 3, 0, 3, 0,
- 4, 0, 4, 0, 3, 0, 3, 0, 4, 0, 4, 0, 4, 0, 4, 0, 3, 0, 3, 0, 4, 0, 4, 0, 140,
- 0, 141, 0, 142, 0, 36, 0, 36, 0, 36, 0, 141, 0, 141, 0, 142, 0, 36, 0, 36, 0,
- 36, 0, 141, 0, 4, 0, 3, 0, 128, 0, 3, 0, 3, 0, 4, 0, 3, 0, 3, 0, 0, 143, 0, 0,
- 0, 0, 11, 0, 0, 0, 0, 0, 0, 0, 3, 0, 0, 24, 0, 24, 0, 24, 0, 24, 0, 24, 0, 24,
- 0, 24, 3, 0, 3, 0, 0, 7, 0, 7, 0, 7, 0, 39, 3, 0, 3, 0, 3, 0, 3, 0, 54, 0, 3,
- 0, 3, 0, 3, 0, 3, 0, 3, 0, 54, 0, 3, 0, 3, 0, 3, 0, 3, 0, 3, 0, 3, 0, 3, 0,
- 3, 0, 3, 0, 3, 0, 39, 0, 144, 0, 3, 0, 3, 0, 4, 0, 3, 0, 3, 0, 3, 0, 4, 0, 3,
- 0, 0, 145, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 0, 146, 0, 7, 0, 147, 0, 146, 0, 0,
- 148, 0, 148, 0, 149, 0, 148, 0, 149, 0, 148, 0, 148, 150, 0, 0, 151, 0, 0, 146,
- 0, 146, 0, 0, 11, 0, 7, 0, 7, 0, 38, 0, 147, 0, 0, 7, 0, 147, 0, 0, 152, 146,
- 0, 146, 0, 0, 10, 2, 0, 153, 0, 0, 154, 0, 154, 0, 154, 0, 154, 0, 154, 0,
- 154, 0, 154, 0, 154, 0, 154, 0, 154, 0, 154, 0, 154, 0, 154, 0, 154, 0, 154,
- 0, 154, 0, 154, 0, 154, 0, 154, 0, 154, 0, 154, 0, 154, 0, 154, 0, 154, 0, 154,
- 0, 154, 0, 154, 0, 154, 0, 154, 0, 154, 0, 0, 0, 64, 4, 0, 4, 0, 4, 0, 0, 4,
- 4, 0, 4, 0, 0, 12, 146, 0, 0, 155, 0, 10, 146, 0, 0, 155, 0, 10, 0, 4, 0, 4,
- 0, 64, 0, 47, 0, 156, 0, 148, 0, 156, 7, 0, 7, 0, 38, 0, 147, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 157, 158, 0, 0, 156, 2, 0, 4, 0, 4, 0, 5, 0, 6, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 11, 0, 19, 0, 11, 0, 11, 0, 31, 0, 32, 0, 0,
- 0, 4, 0, 4, 0, 4, 0, 4, 0, 0, 159, 0, 160, 0, 159, 0, 160, 0, 8, 0, 8, 0, 161,
- 0, 162, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 7, 0, 0, 7, 0, 8, 0, 8, 0, 8, 0,
- 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 163, 0, 163,
- 164, 0, 40, 0, 165, 0, 166, 0, 165, 0, 166, 0, 164, 0, 40, 0, 165, 0, 166,
- 0, 165, 0, 166, 0, 167, 0, 168, 0, 0, 8, 0, 8, 0, 169, 0, 170, 31, 0, 32, 0, 171,
- 0, 171, 0, 172, 0, 11, 0, 0, 8, 120, 0, 173, 0, 173, 0, 11, 0, 173, 0, 11,
- 0, 172, 0, 11, 0, 172, 0, 0, 174, 172, 0, 11, 0, 172, 0, 11, 0, 173, 0, 40, 0,
- 0, 175, 40, 0, 0, 176, 0, 177, 0, 178, 45, 0, 45, 0, 173, 0, 11, 0, 173, 0,
- 11, 0, 11, 0, 172, 0, 11, 0, 172, 0, 40, 0, 40, 0, 45, 0, 45, 0, 172, 0, 11, 0,
- 11, 0, 173, 0, 0, 176, 0, 177, 0, 8, 0, 8, 0, 8, 0, 161, 0, 162, 0, 8, 0, 179,
- 0, 8, 0, 101, 0, 101, 180, 0, 180, 0, 11, 0, 11, 0, 0, 181, 0, 182, 0, 183,
- 0, 182, 0, 183, 0, 181, 0, 182, 0, 183, 0, 182, 0, 183, 0, 52, 0, 184, 0, 184,
- 0, 185, 0, 186, 0, 184, 0, 184, 0, 187, 0, 188, 0, 184, 0, 184, 0, 187, 0, 188,
- 0, 184, 0, 184, 0, 187, 0, 188, 0, 189, 0, 189, 0, 190, 0, 191, 0, 184, 0,
- 184, 0, 184, 0, 184, 0, 184, 0, 184, 0, 189, 0, 189, 0, 184, 0, 184, 0, 187,
- 0, 188, 0, 184, 0, 184, 0, 187, 0, 188, 0, 184, 0, 184, 0, 187, 0, 188, 0, 184,
- 0, 184, 0, 184, 0, 184, 0, 184, 0, 184, 0, 189, 0, 189, 0, 189, 0, 189, 0, 190,
- 0, 191, 0, 184, 0, 184, 0, 187, 0, 188, 0, 184, 0, 184, 0, 187, 0, 188, 0,
- 184, 0, 184, 0, 187, 0, 188, 0, 189, 0, 189, 0, 190, 0, 191, 0, 184, 0, 184,
- 0, 187, 0, 188, 0, 184, 0, 184, 0, 187, 0, 188, 0, 184, 0, 184, 0, 192, 0, 193,
- 0, 189, 0, 189, 0, 190, 0, 191, 0, 194, 0, 194, 0, 39, 0, 195, 11, 0, 11, 0,
- 39, 0, 196, 0, 99, 197, 99, 198, 0, 24, 0, 24, 0, 24, 0, 24, 0, 24, 0, 24, 0,
- 24, 0, 24, 99, 198, 99, 199, 11, 0, 11, 0, 0, 200, 0, 201, 0, 11, 0, 11, 0, 200,
- 0, 201, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 202, 0, 203, 0, 204,
- 0, 203, 0, 204, 0, 202, 0, 203, 0, 204, 0, 203, 0, 204, 0, 162, 111, 0, 0, 98,
- 0, 106, 0, 205, 0, 205, 0, 8, 0, 8, 0, 161, 0, 162, 0, 0, 0, 206, 0, 0, 0, 8,
- 0, 8, 0, 161, 0, 162, 0, 0, 0, 207, 0, 0, 208, 0, 208, 0, 81, 0, 209, 0, 208,
- 0, 208, 0, 208, 0, 208, 0, 208, 0, 208, 0, 208, 0, 208, 0, 0, 210, 211, 212,
- 211, 212, 0, 213, 116, 214, 116, 214, 215, 0, 216, 0, 111, 0, 111, 0, 111, 0,
- 111, 0, 217, 0, 116, 218, 11, 0, 11, 0, 118, 219, 208, 0, 208, 0, 0, 8, 0, 220,
- 0, 206, 171, 0, 0, 0, 0, 221, 0, 207, 0, 8, 0, 8, 0, 161, 0, 162, 222, 0, 0,
- 220, 0, 8, 0, 8, 0, 223, 0, 223, 11, 0, 11, 0, 11, 0, 11, 0, 0, 8, 0, 8, 0, 8,
- 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8,
- 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 163, 0, 8, 224, 0, 45, 0, 225, 0, 225,
- 0, 40, 0, 226, 0, 0, 8, 0, 189, 0, 227, 0, 227, 0, 8, 0, 8, 0, 8, 0, 8, 0, 129,
- 0, 130, 0, 8, 0, 8, 0, 8, 0, 8, 0, 131, 0, 132, 0, 227, 0, 227, 0, 227, 0,
- 227, 0, 227, 0, 227, 0, 179, 0, 179, 171, 0, 171, 0, 171, 0, 171, 0, 0, 179,
- 0, 179, 0, 179, 0, 179, 0, 179, 0, 179, 11, 0, 11, 0, 0, 184, 0, 184, 0, 184,
- 0, 184, 0, 228, 0, 228, 0, 8, 0, 8, 0, 8, 0, 184, 0, 8, 0, 8, 0, 184, 0, 184,
- 0, 189, 0, 189, 0, 229, 0, 229, 0, 229, 0, 8, 0, 229, 0, 8, 0, 184, 0, 184, 0,
- 184, 0, 184, 0, 184, 0, 8, 11, 0, 11, 0, 11, 0, 11, 0, 0, 133, 0, 52, 0, 134,
- 0, 230, 99, 198, 99, 197, 99, 199, 99, 198, 7, 0, 7, 0, 7, 0, 0, 8, 7, 0, 0,
- 8, 7, 0, 7, 0, 7, 0, 7, 0, 7, 0, 7, 0, 0, 8, 7, 0, 7, 0, 136, 0, 7, 0, 0, 8, 7,
- 0, 0, 8, 0, 8, 7, 0, 0, 231, 0, 162, 0, 161, 0, 232, 11, 0, 11, 0, 0, 233, 0,
- 233, 0, 233, 0, 233, 0, 233, 0, 233, 0, 233, 0, 233, 0, 233, 0, 233, 0, 233,
- 0, 233, 0, 184, 0, 184, 0, 8, 0, 8, 0, 205, 0, 205, 0, 8, 0, 8, 0, 8, 0, 8, 0,
- 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 234, 0,
- 234, 0, 235, 0, 174, 0, 225, 0, 225, 0, 225, 0, 225, 0, 140, 0, 234, 0, 236,
- 0, 174, 0, 235, 0, 235, 0, 174, 0, 236, 0, 174, 0, 235, 0, 174, 0, 237, 0, 238,
- 0, 172, 0, 172, 0, 172, 0, 237, 0, 235, 0, 174, 0, 236, 0, 174, 0, 235, 0, 174,
- 0, 234, 0, 174, 0, 237, 0, 238, 0, 172, 0, 172, 0, 172, 0, 237, 0, 0, 8, 0,
- 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 11, 0, 11, 0, 11, 0, 11, 0, 0,
- 8, 0, 8, 0, 8, 0, 239, 0, 11, 0, 11, 0, 8, 0, 8, 0, 11, 0, 11, 0, 8, 0, 8, 0,
- 240, 0, 240, 0, 240, 0, 240, 0, 8, 111, 0, 111, 0, 241, 0, 111, 0, 0, 240, 0,
- 240, 0, 240, 0, 240, 0, 240, 0, 240, 0, 8, 0, 8, 0, 184, 0, 184, 0, 184, 0, 8,
- 0, 240, 0, 240, 0, 8, 0, 8, 0, 184, 0, 184, 0, 184, 0, 8, 0, 8, 0, 227, 0, 11,
- 0, 11, 0, 11, 0, 8, 0, 8, 0, 8, 0, 242, 0, 243, 0, 242, 0, 8, 0, 8, 0, 8, 0,
- 242, 0, 242, 0, 242, 0, 8, 0, 8, 0, 8, 0, 242, 0, 242, 0, 243, 0, 242, 0, 8,
- 0, 8, 0, 8, 0, 242, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 184, 0,
- 184, 222, 0, 0, 227, 0, 227, 0, 227, 0, 227, 0, 227, 0, 227, 0, 227, 0, 227,
- 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8,
- 0, 200, 0, 201, 11, 0, 11, 0, 0, 200, 0, 201, 180, 0, 180, 0, 0, 200, 0, 201,
- 11, 0, 0, 201, 0, 11, 0, 11, 0, 200, 0, 201, 0, 11, 0, 11, 0, 200, 0, 201, 0,
- 11, 0, 11, 0, 200, 0, 201, 11, 0, 11, 0, 0, 200, 0, 201, 180, 0, 180, 0, 0, 200,
- 0, 201, 11, 0, 0, 201, 0, 8, 0, 8, 0, 161, 0, 162, 111, 0, 111, 0, 0, 24, 0,
- 24, 0, 24, 0, 24, 0, 24, 0, 24, 0, 24, 0, 24, 111, 0, 241, 0, 0, 8, 0, 8, 0,
- 8, 0, 8, 0, 8, 0, 8, 11, 0, 11, 0, 0, 200, 0, 201, 0, 157, 0, 8, 0, 8, 0, 161,
- 0, 162, 222, 0, 222, 0, 31, 0, 32, 0, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 102, 0, 102, 0, 244, 0, 0, 245, 0, 0, 0, 246, 0, 0, 0,
- 0, 149, 0, 0, 2, 0, 4, 0, 4, 0, 0, 247, 0, 247, 0, 247, 0, 247, 0, 248, 0, 248,
- 0, 248, 0, 248, 0, 248, 0, 248, 0, 248, 0, 248, 0, 244, 0, 0
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 45, 46, 47, 48, 49, 50, 51, 52, 0, 0, 0, 53,
+ 54, 55, 56, 0, 0, 0, 0, 0, 0, 0, 0, 0, 53, 54, 55, 56, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 57, 58, 0, 59, 0, 60, 0, 59, 0, 59, 0, 59, 0, 0, 0, 0, 61, 62,
+ 62, 62, 57, 59, 0, 0, 0, 9, 0, 0, 4, 4, 5, 6, 0, 0, 4, 4, 5, 6, 0, 0, 63, 64,
+ 64, 65, 46, 24, 36, 65, 51, 64, 64, 66, 67, 67, 68, 69, 69, 70, 70, 58, 58, 65,
+ 58, 58, 69, 69, 71, 47, 51, 72, 47, 7, 7, 46, 73, 9, 64, 64, 73, 0, 35, 4, 4,
+ 5, 6, 0, 74, 0, 0, 0, 0, 2, 4, 4, 75, 76, 9, 9, 9, 3, 3, 4, 3, 3, 3, 3, 3, 3,
+ 3, 3, 3, 0, 3, 3, 0, 3, 77, 3, 0, 0, 0, 3, 3, 4, 3, 0, 0, 3, 3, 4, 3, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 27, 27, 77, 77, 77, 77, 77, 77, 77, 77, 77, 77, 27, 77,
+ 77, 77, 27, 27, 77, 77, 77, 3, 3, 3, 78, 3, 3, 3, 27, 27, 0, 0, 0, 0, 3, 3,
+ 4, 4, 3, 3, 4, 4, 4, 4, 3, 3, 4, 4, 79, 80, 81, 24, 24, 24, 80, 80, 81, 24, 24,
+ 24, 80, 4, 3, 77, 3, 3, 4, 3, 3, 0, 0, 0, 9, 0, 0, 0, 3, 0, 0, 0, 0, 0, 0, 0,
+ 3, 3, 0, 0, 0, 0, 3, 3, 3, 3, 82, 3, 3, 0, 3, 3, 3, 82, 3, 3, 3, 3, 3, 3, 3,
+ 3, 3, 3, 27, 83, 3, 3, 4, 3, 3, 3, 4, 3, 0, 0, 0, 0, 0, 0, 0, 3, 84, 7, 85, 84,
+ 0, 0, 0, 0, 0, 0, 0, 0, 86, 0, 0, 0, 0, 84, 84, 0, 0, 0, 0, 0, 0, 7, 85, 0,
+ 84, 84, 0, 2, 87, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4, 4, 4, 0, 4, 4, 0, 84, 0, 0, 84, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 7, 7, 26, 85, 0, 0, 0, 0, 0, 0, 88, 0, 0, 2, 4, 4, 5,
+ 6, 0, 0, 0, 0, 0, 0, 0, 9, 0, 0, 0, 0, 0, 15, 89, 89, 0, 90, 0, 0, 9, 9, 20, 21,
+ 0, 0, 0, 4, 4, 4, 4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 7, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 91, 28, 92, 93, 92, 93, 91, 28, 92,
+ 93, 92, 93, 94, 95, 0, 0, 0, 0, 20, 21, 96, 96, 97, 9, 0, 73, 98, 98, 9, 98, 9,
+ 97, 9, 97, 0, 97, 9, 97, 9, 98, 28, 0, 28, 0, 0, 0, 33, 33, 98, 9, 98, 9, 9,
+ 97, 9, 97, 28, 28, 33, 33, 97, 9, 9, 98, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 99, 99, 9, 9, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 9,
+ 9, 27, 100, 59, 59, 0, 0, 0, 0, 0, 0, 0, 0, 59, 59, 9, 9, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 65, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 101, 101, 46, 102, 101, 101, 101, 101, 101,
+ 101, 101, 101, 0, 103, 103, 0, 69, 69, 104, 105, 65, 65, 65, 65, 106, 69, 9, 9,
+ 71, 101, 101, 0, 0, 0, 96, 0, 0, 0, 0, 0, 0, 0, 107, 0, 0, 0, 0, 0, 0, 0, 9,
+ 9, 9, 9, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 108, 33, 109, 109, 28, 110, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 96, 96, 96, 96, 0, 0, 0, 0, 0, 0, 9, 9, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 9, 9,
+ 9, 9, 0, 0, 0, 0, 59, 59, 59, 59, 7, 7, 7, 0, 7, 0, 7, 7, 7, 7, 7, 7, 0, 7, 7,
+ 78, 7, 0, 7, 0, 0, 7, 0, 0, 0, 0, 9, 9, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 111, 111, 112,
+ 113, 109, 109, 109, 109, 79, 111, 114, 113, 112, 112, 113, 114, 113, 112, 113,
+ 115, 116, 97, 97, 97, 115, 112, 113, 114, 113, 112, 113, 111, 113, 115, 116,
+ 97, 97, 97, 115, 0, 0, 0, 0, 0, 0, 0, 0, 0, 9, 9, 9, 9, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 65, 65, 117, 65, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 107, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 9, 9, 0, 0, 99,
+ 99, 0, 0, 9, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 9, 9, 0, 0, 99, 99, 0, 0,
+ 9, 0, 0, 0, 0, 0, 65, 65, 0, 0, 0, 0, 0, 0, 0, 0, 65, 117, 0, 0, 0, 0, 0, 0, 9,
+ 9, 0, 0, 0, 0, 0, 0, 0, 107, 107, 20, 21, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 118, 0, 119, 0, 0, 0, 2, 4, 4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0
+};
+
+const uint8_t InstDB::rwInfoIndexB[Inst::_kIdCount] = {
+ 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 0, 3, 0, 0, 0,
+ 0, 0, 4, 0, 0, 0, 0, 0, 5, 5, 6, 6, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 7, 0, 0, 0, 0, 4, 8, 1, 0, 9, 0, 0, 0, 10, 10, 10, 0, 0, 0, 10, 11, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 5, 5, 0, 12, 13, 14, 15, 16, 0, 0, 17, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 18, 1, 1, 19, 20, 0, 0, 0, 0, 5,
+ 5, 0, 0, 0, 0, 21, 22, 0, 0, 23, 24, 25, 26, 0, 0, 24, 24, 24, 24, 24, 24, 24,
+ 24, 27, 28, 28, 27, 0, 0, 0, 23, 24, 23, 24, 0, 24, 23, 23, 23, 23, 23, 23,
+ 23, 0, 0, 29, 29, 29, 23, 23, 27, 0, 30, 10, 0, 0, 0, 0, 0, 0, 23, 24, 0, 0,
+ 0, 31, 32, 31, 33, 0, 0, 0, 0, 0, 10, 31, 0, 0, 0, 0, 34, 32, 31, 34, 33, 23,
+ 24, 23, 24, 0, 28, 28, 28, 28, 0, 0, 0, 24, 10, 10, 31, 31, 0, 0, 0, 0, 5, 5,
+ 0, 0, 0, 0, 0, 0, 20, 35, 0, 19, 0, 36, 37, 0, 0, 0, 0, 0, 10, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 38, 39, 40, 41, 38, 39, 38, 39, 40, 41, 40, 41, 0, 0,
+ 0, 0, 0, 0, 0, 0, 38, 39, 40, 0, 0, 0, 0, 41, 42, 43, 44, 45, 42, 43, 44, 45,
+ 0, 0, 0, 0, 46, 47, 48, 38, 39, 40, 41, 38, 39, 40, 41, 49, 0, 0, 50, 0, 51, 0,
+ 0, 0, 0, 0, 10, 0, 10, 52, 53, 52, 0, 0, 0, 0, 0, 0, 52, 54, 54, 0, 55, 56,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 57, 57, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 5,
+ 58, 0, 0, 0, 0, 59, 0, 60, 19, 61, 19, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 62, 0, 0, 0, 0, 0, 0, 6, 5, 5, 0, 0, 0, 0, 63, 64, 0, 0,
+ 0, 0, 65, 66, 0, 0, 3, 3, 67, 21, 68, 69, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 70, 36, 71, 72, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 73, 0, 0, 0, 0, 0, 0, 0, 10, 10, 10, 10, 10, 10, 10, 0, 0,
+ 2, 2, 2, 74, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 75, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 76, 76,
+ 77, 76, 77, 78, 76, 76, 0, 79, 0, 0, 0, 0, 0, 80, 2, 2, 81, 82, 0, 0, 0, 83, 0,
+ 0, 4, 0, 0, 0, 84, 84, 84, 84, 84, 84, 84, 84, 84, 84, 84, 84, 84, 84, 84, 84,
+ 84, 84, 84, 84, 84, 84, 84, 84, 84, 84, 84, 84, 84, 84, 0, 31, 0, 0, 0, 5,
+ 0, 0, 6, 0, 85, 4, 0, 85, 4, 5, 5, 31, 18, 86, 76, 86, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 87, 0, 86, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 89, 89, 89, 89, 89,
+ 0, 0, 0, 0, 0, 90, 91, 0, 0, 0, 0, 0, 53, 91, 0, 0, 0, 0, 92, 93, 92, 93, 3, 3,
+ 94, 95, 3, 3, 3, 3, 3, 3, 0, 2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 96,
+ 96, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 3, 97, 98, 0, 0, 0, 0, 0, 0,
+ 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 99, 0, 0, 0, 0, 0, 0, 100, 0, 101, 102, 103, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 101, 102, 3, 3, 3, 94, 95,
+ 3, 104, 3, 52, 52, 0, 0, 0, 0, 105, 106, 107, 106, 107, 105, 106, 107, 106,
+ 107, 21, 108, 108, 109, 110, 108, 108, 111, 112, 108, 108, 111, 112, 108, 108,
+ 111, 112, 113, 113, 114, 115, 108, 108, 108, 108, 108, 108, 113, 113, 108, 108,
+ 111, 112, 108, 108, 111, 112, 108, 108, 111, 112, 108, 108, 108, 108, 108,
+ 108, 113, 113, 113, 113, 114, 115, 108, 108, 111, 112, 108, 108, 111, 112, 108,
+ 108, 111, 112, 113, 113, 114, 115, 108, 108, 111, 112, 108, 108, 111, 112, 108,
+ 108, 116, 117, 113, 113, 114, 115, 118, 118, 74, 119, 0, 0, 0, 0, 120, 121,
+ 10, 10, 10, 10, 10, 10, 10, 10, 121, 122, 0, 0, 123, 124, 80, 80, 123, 124,
+ 3, 3, 3, 3, 3, 3, 3, 125, 126, 127, 126, 127, 125, 126, 127, 126, 127, 95, 0,
+ 50, 55, 128, 128, 3, 3, 94, 95, 0, 129, 0, 3, 3, 94, 95, 0, 130, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 131, 132, 132, 133, 134, 134, 0, 0, 0, 0, 0, 0, 0, 135,
+ 0, 0, 136, 0, 0, 3, 137, 129, 0, 0, 138, 130, 3, 3, 94, 95, 0, 137, 3, 3,
+ 139, 139, 140, 140, 0, 0, 0, 0, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
+ 3, 3, 3, 3, 3, 3, 96, 3, 0, 0, 0, 0, 0, 0, 3, 113, 141, 141, 3, 3, 3, 3, 63,
+ 64, 3, 3, 3, 3, 65, 66, 141, 141, 141, 141, 141, 141, 104, 104, 0, 0, 0, 0, 104,
+ 104, 104, 104, 104, 104, 0, 0, 108, 108, 108, 108, 142, 142, 3, 3, 3, 108,
+ 3, 3, 108, 108, 113, 113, 143, 143, 143, 3, 143, 3, 108, 108, 108, 108, 108,
+ 3, 0, 0, 0, 0, 67, 21, 68, 144, 121, 120, 122, 121, 0, 0, 0, 3, 0, 3, 0, 0, 0,
+ 0, 0, 0, 3, 0, 0, 0, 0, 3, 0, 3, 3, 0, 145, 95, 94, 146, 0, 0, 147, 147, 147,
+ 147, 147, 147, 147, 147, 147, 147, 147, 147, 108, 108, 3, 3, 128, 128, 3, 3,
+ 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 3, 3, 3, 3, 3, 3, 3, 3, 3, 0, 0, 0, 0, 3, 3, 3, 148, 80, 80, 3, 3, 80, 80,
+ 3, 3, 149, 149, 149, 149, 3, 0, 0, 0, 0, 149, 149, 149, 149, 149, 149, 3, 3, 108,
+ 108, 108, 3, 149, 149, 3, 3, 108, 108, 108, 3, 3, 141, 80, 80, 80, 3, 3, 3,
+ 150, 151, 150, 3, 3, 3, 150, 150, 150, 3, 3, 3, 150, 150, 151, 150, 3, 3, 3,
+ 150, 3, 3, 3, 3, 3, 3, 3, 3, 108, 108, 0, 141, 141, 141, 141, 141, 141, 141,
+ 141, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 123, 124, 0, 0, 123, 124, 0, 0, 123,
+ 124, 0, 124, 80, 80, 123, 124, 80, 80, 123, 124, 80, 80, 123, 124, 0, 0, 123,
+ 124, 0, 0, 123, 124, 0, 124, 3, 3, 94, 95, 0, 0, 10, 10, 10, 10, 10, 10, 10,
+ 10, 0, 0, 3, 3, 3, 3, 3, 3, 0, 0, 123, 124, 87, 3, 3, 94, 95, 0, 0, 0, 0, 3,
+ 3, 3, 3, 3, 3, 0, 0, 0, 0, 53, 53, 152, 0, 0, 0, 0, 0, 77, 0, 0, 0, 0, 0, 153,
+ 153, 153, 153, 154, 154, 154, 154, 154, 154, 154, 154, 152, 0, 0
};
-const InstDB::RWInfo InstDB::rwInfo[] = {
- { InstDB::RWInfo::kCategoryGeneric , 0 , { 0 , 0 , 0 , 0 , 0 , 0 } }, // #0 [ref=1609x]
- { InstDB::RWInfo::kCategoryGeneric , 0 , { 1 , 0 , 0 , 0 , 0 , 0 } }, // #1 [ref=7x]
+const InstDB::RWInfo InstDB::rwInfoA[] = {
+ { InstDB::RWInfo::kCategoryGeneric , 0 , { 0 , 0 , 0 , 0 , 0 , 0 } }, // #0 [ref=919x]
+ { InstDB::RWInfo::kCategoryGeneric , 0 , { 1 , 0 , 0 , 0 , 0 , 0 } }, // #1 [ref=2x]
{ InstDB::RWInfo::kCategoryGeneric , 1 , { 2 , 3 , 0 , 0 , 0 , 0 } }, // #2 [ref=7x]
- { InstDB::RWInfo::kCategoryGeneric , 2 , { 2 , 3 , 0 , 0 , 0 , 0 } }, // #3 [ref=100x]
- { InstDB::RWInfo::kCategoryGeneric , 3 , { 4 , 5 , 0 , 0 , 0 , 0 } }, // #4 [ref=69x]
- { InstDB::RWInfo::kCategoryGeneric , 4 , { 6 , 7 , 0 , 0 , 0 , 0 } }, // #5 [ref=7x]
- { InstDB::RWInfo::kCategoryGeneric , 5 , { 8 , 9 , 0 , 0 , 0 , 0 } }, // #6 [ref=7x]
- { InstDB::RWInfo::kCategoryGeneric , 3 , { 10, 5 , 0 , 0 , 0 , 0 } }, // #7 [ref=33x]
- { InstDB::RWInfo::kCategoryGeneric , 6 , { 11, 3 , 3 , 0 , 0 , 0 } }, // #8 [ref=186x]
- { InstDB::RWInfo::kCategoryGeneric , 7 , { 12, 13, 0 , 0 , 0 , 0 } }, // #9 [ref=1x]
- { InstDB::RWInfo::kCategoryGeneric , 2 , { 11, 3 , 3 , 0 , 0 , 0 } }, // #10 [ref=5x]
- { InstDB::RWInfo::kCategoryGeneric , 2 , { 11, 3 , 0 , 0 , 0 , 0 } }, // #11 [ref=81x]
- { InstDB::RWInfo::kCategoryGeneric , 3 , { 4 , 5 , 14, 0 , 0 , 0 } }, // #12 [ref=4x]
- { InstDB::RWInfo::kCategoryGeneric , 2 , { 5 , 3 , 0 , 0 , 0 , 0 } }, // #13 [ref=3x]
- { InstDB::RWInfo::kCategoryGeneric , 8 , { 10, 3 , 0 , 0 , 0 , 0 } }, // #14 [ref=2x]
- { InstDB::RWInfo::kCategoryGeneric , 9 , { 10, 5 , 0 , 0 , 0 , 0 } }, // #15 [ref=1x]
- { InstDB::RWInfo::kCategoryGeneric , 8 , { 11, 5 , 0 , 0 , 0 , 0 } }, // #16 [ref=1x]
- { InstDB::RWInfo::kCategoryGeneric , 0 , { 3 , 3 , 0 , 0 , 0 , 0 } }, // #17 [ref=1x]
- { InstDB::RWInfo::kCategoryGeneric , 0 , { 2 , 0 , 0 , 0 , 0 , 0 } }, // #18 [ref=1x]
- { InstDB::RWInfo::kCategoryGeneric , 10, { 3 , 3 , 0 , 0 , 0 , 0 } }, // #19 [ref=2x]
- { InstDB::RWInfo::kCategoryGeneric , 10, { 2 , 3 , 0 , 0 , 0 , 0 } }, // #20 [ref=3x]
- { InstDB::RWInfo::kCategoryGeneric , 11, { 3 , 0 , 0 , 0 , 0 , 0 } }, // #21 [ref=2x]
- { InstDB::RWInfo::kCategoryGeneric , 0 , { 15, 16, 0 , 0 , 0 , 0 } }, // #22 [ref=1x]
- { InstDB::RWInfo::kCategoryGeneric , 0 , { 17, 0 , 0 , 0 , 0 , 0 } }, // #23 [ref=1x]
- { InstDB::RWInfo::kCategoryGeneric , 8 , { 3 , 0 , 0 , 0 , 0 , 0 } }, // #24 [ref=34x]
- { InstDB::RWInfo::kCategoryGeneric , 0 , { 18, 0 , 0 , 0 , 0 , 0 } }, // #25 [ref=1x]
- { InstDB::RWInfo::kCategoryGeneric , 1 , { 3 , 3 , 0 , 0 , 0 , 0 } }, // #26 [ref=1x]
- { InstDB::RWInfo::kCategoryGeneric , 0 , { 19, 20, 0 , 0 , 0 , 0 } }, // #27 [ref=1x]
- { InstDB::RWInfo::kCategoryGeneric , 11, { 2 , 3 , 21, 0 , 0 , 0 } }, // #28 [ref=1x]
- { InstDB::RWInfo::kCategoryGeneric , 12, { 4 , 22, 17, 23, 24, 0 } }, // #29 [ref=1x]
- { InstDB::RWInfo::kCategoryGeneric , 13, { 25, 26, 27, 28, 29, 0 } }, // #30 [ref=1x]
- { InstDB::RWInfo::kCategoryGeneric , 4 , { 7 , 7 , 0 , 0 , 0 , 0 } }, // #31 [ref=4x]
- { InstDB::RWInfo::kCategoryGeneric , 5 , { 9 , 9 , 0 , 0 , 0 , 0 } }, // #32 [ref=4x]
- { InstDB::RWInfo::kCategoryGeneric , 0 , { 27, 30, 31, 15, 0 , 0 } }, // #33 [ref=1x]
- { InstDB::RWInfo::kCategoryGeneric , 0 , { 32, 33, 0 , 0 , 0 , 0 } }, // #34 [ref=1x]
- { InstDB::RWInfo::kCategoryGeneric , 14, { 2 , 3 , 0 , 0 , 0 , 0 } }, // #35 [ref=1x]
- { InstDB::RWInfo::kCategoryGeneric , 4 , { 10, 7 , 0 , 0 , 0 , 0 } }, // #36 [ref=10x]
- { InstDB::RWInfo::kCategoryGeneric , 3 , { 34, 5 , 0 , 0 , 0 , 0 } }, // #37 [ref=5x]
- { InstDB::RWInfo::kCategoryGeneric , 4 , { 35, 7 , 0 , 0 , 0 , 0 } }, // #38 [ref=3x]
- { InstDB::RWInfo::kCategoryGeneric , 4 , { 34, 7 , 0 , 0 , 0 , 0 } }, // #39 [ref=13x]
- { InstDB::RWInfo::kCategoryGeneric , 4 , { 11, 7 , 0 , 0 , 0 , 0 } }, // #40 [ref=9x]
- { InstDB::RWInfo::kCategoryGeneric , 4 , { 36, 7 , 0 , 0 , 0 , 0 } }, // #41 [ref=1x]
- { InstDB::RWInfo::kCategoryGeneric , 14, { 35, 3 , 0 , 0 , 0 , 0 } }, // #42 [ref=1x]
- { InstDB::RWInfo::kCategoryGeneric , 14, { 36, 3 , 0 , 0 , 0 , 0 } }, // #43 [ref=1x]
- { InstDB::RWInfo::kCategoryGeneric , 5 , { 35, 9 , 0 , 0 , 0 , 0 } }, // #44 [ref=1x]
- { InstDB::RWInfo::kCategoryGeneric , 5 , { 11, 9 , 0 , 0 , 0 , 0 } }, // #45 [ref=7x]
- { InstDB::RWInfo::kCategoryGeneric , 0 , { 37, 38, 0 , 0 , 0 , 0 } }, // #46 [ref=1x]
- { InstDB::RWInfo::kCategoryGeneric , 0 , { 27, 0 , 0 , 0 , 0 , 0 } }, // #47 [ref=2x]
- { InstDB::RWInfo::kCategoryGeneric , 10, { 2 , 0 , 0 , 0 , 0 , 0 } }, // #48 [ref=4x]
- { InstDB::RWInfo::kCategoryGeneric , 15, { 1 , 39, 0 , 0 , 0 , 0 } }, // #49 [ref=3x]
- { InstDB::RWInfo::kCategoryGeneric , 6 , { 40, 41, 3 , 0 , 0 , 0 } }, // #50 [ref=2x]
- { InstDB::RWInfo::kCategoryGeneric , 16, { 42, 43, 0 , 0 , 0 , 0 } }, // #51 [ref=2x]
- { InstDB::RWInfo::kCategoryGeneric , 17, { 42, 5 , 0 , 0 , 0 , 0 } }, // #52 [ref=4x]
- { InstDB::RWInfo::kCategoryGeneric , 0 , { 4 , 5 , 0 , 0 , 0 , 0 } }, // #53 [ref=3x]
- { InstDB::RWInfo::kCategoryGeneric , 0 , { 4 , 0 , 0 , 0 , 0 , 0 } }, // #54 [ref=3x]
- { InstDB::RWInfo::kCategoryGeneric , 0 , { 44, 45, 0 , 0 , 0 , 0 } }, // #55 [ref=6x]
- { InstDB::RWInfo::kCategoryGeneric , 18, { 3 , 0 , 0 , 0 , 0 , 0 } }, // #56 [ref=15x]
- { InstDB::RWInfo::kCategoryGeneric , 0 , { 44, 0 , 0 , 0 , 0 , 0 } }, // #57 [ref=16x]
- { InstDB::RWInfo::kCategoryGeneric , 19, { 45, 0 , 0 , 0 , 0 , 0 } }, // #58 [ref=1x]
- { InstDB::RWInfo::kCategoryGeneric , 19, { 46, 0 , 0 , 0 , 0 , 0 } }, // #59 [ref=1x]
- { InstDB::RWInfo::kCategoryGeneric , 20, { 3 , 0 , 0 , 0 , 0 , 0 } }, // #60 [ref=3x]
- { InstDB::RWInfo::kCategoryGeneric , 0 , { 45, 0 , 0 , 0 , 0 , 0 } }, // #61 [ref=6x]
- { InstDB::RWInfo::kCategoryGeneric , 18, { 11, 0 , 0 , 0 , 0 , 0 } }, // #62 [ref=3x]
- { InstDB::RWInfo::kCategoryGeneric , 21, { 13, 0 , 0 , 0 , 0 , 0 } }, // #63 [ref=1x]
- { InstDB::RWInfo::kCategoryGeneric , 8 , { 11, 0 , 0 , 0 , 0 , 0 } }, // #64 [ref=8x]
- { InstDB::RWInfo::kCategoryGeneric , 21, { 47, 0 , 0 , 0 , 0 , 0 } }, // #65 [ref=2x]
- { InstDB::RWInfo::kCategoryGeneric , 7 , { 48, 0 , 0 , 0 , 0 , 0 } }, // #66 [ref=2x]
- { InstDB::RWInfo::kCategoryGeneric , 20, { 11, 0 , 0 , 0 , 0 , 0 } }, // #67 [ref=2x]
- { InstDB::RWInfo::kCategoryImul , 2 , { 0 , 0 , 0 , 0 , 0 , 0 } }, // #68 [ref=1x]
- { InstDB::RWInfo::kCategoryImul , 22, { 0 , 0 , 0 , 0 , 0 , 0 } }, // #69 [ref=1x]
- { InstDB::RWInfo::kCategoryGeneric , 0 , { 49, 50, 0 , 0 , 0 , 0 } }, // #70 [ref=1x]
- { InstDB::RWInfo::kCategoryGeneric , 0 , { 51, 50, 0 , 0 , 0 , 0 } }, // #71 [ref=1x]
- { InstDB::RWInfo::kCategoryGeneric , 5 , { 4 , 9 , 0 , 0 , 0 , 0 } }, // #72 [ref=2x]
- { InstDB::RWInfo::kCategoryGeneric , 12, { 3 , 5 , 0 , 0 , 0 , 0 } }, // #73 [ref=3x]
- { InstDB::RWInfo::kCategoryGeneric , 0 , { 21, 28, 0 , 0 , 0 , 0 } }, // #74 [ref=1x]
- { InstDB::RWInfo::kCategoryGeneric , 0 , { 52, 0 , 0 , 0 , 0 , 0 } }, // #75 [ref=1x]
- { InstDB::RWInfo::kCategoryGeneric , 0 , { 53, 39, 39, 0 , 0 , 0 } }, // #76 [ref=6x]
- { InstDB::RWInfo::kCategoryGeneric , 0 , { 42, 9 , 9 , 0 , 0 , 0 } }, // #77 [ref=6x]
- { InstDB::RWInfo::kCategoryGeneric , 0 , { 34, 7 , 7 , 0 , 0 , 0 } }, // #78 [ref=6x]
- { InstDB::RWInfo::kCategoryGeneric , 0 , { 47, 13, 13, 0 , 0 , 0 } }, // #79 [ref=6x]
- { InstDB::RWInfo::kCategoryGeneric , 23, { 53, 39, 0 , 0 , 0 , 0 } }, // #80 [ref=1x]
- { InstDB::RWInfo::kCategoryGeneric , 24, { 42, 9 , 0 , 0 , 0 , 0 } }, // #81 [ref=4x]
- { InstDB::RWInfo::kCategoryGeneric , 25, { 34, 7 , 0 , 0 , 0 , 0 } }, // #82 [ref=3x]
- { InstDB::RWInfo::kCategoryGeneric , 26, { 47, 13, 0 , 0 , 0 , 0 } }, // #83 [ref=1x]
- { InstDB::RWInfo::kCategoryGeneric , 0 , { 53, 39, 0 , 0 , 0 , 0 } }, // #84 [ref=3x]
- { InstDB::RWInfo::kCategoryGeneric , 0 , { 42, 9 , 0 , 0 , 0 , 0 } }, // #85 [ref=3x]
- { InstDB::RWInfo::kCategoryGeneric , 0 , { 34, 7 , 0 , 0 , 0 , 0 } }, // #86 [ref=5x]
- { InstDB::RWInfo::kCategoryGeneric , 0 , { 47, 13, 0 , 0 , 0 , 0 } }, // #87 [ref=3x]
- { InstDB::RWInfo::kCategoryGeneric , 0 , { 39, 39, 0 , 0 , 0 , 0 } }, // #88 [ref=2x]
- { InstDB::RWInfo::kCategoryGeneric , 0 , { 9 , 9 , 0 , 0 , 0 , 0 } }, // #89 [ref=2x]
- { InstDB::RWInfo::kCategoryGeneric , 0 , { 7 , 7 , 0 , 0 , 0 , 0 } }, // #90 [ref=2x]
- { InstDB::RWInfo::kCategoryGeneric , 0 , { 13, 13, 0 , 0 , 0 , 0 } }, // #91 [ref=2x]
- { InstDB::RWInfo::kCategoryGeneric , 0 , { 47, 39, 39, 0 , 0 , 0 } }, // #92 [ref=1x]
- { InstDB::RWInfo::kCategoryGeneric , 0 , { 34, 9 , 9 , 0 , 0 , 0 } }, // #93 [ref=1x]
- { InstDB::RWInfo::kCategoryGeneric , 0 , { 42, 13, 13, 0 , 0 , 0 } }, // #94 [ref=1x]
- { InstDB::RWInfo::kCategoryGeneric , 0 , { 54, 0 , 0 , 0 , 0 , 0 } }, // #95 [ref=1x]
- { InstDB::RWInfo::kCategoryGeneric , 27, { 11, 3 , 0 , 0 , 0 , 0 } }, // #96 [ref=2x]
- { InstDB::RWInfo::kCategoryGeneric , 12, { 10, 5 , 0 , 0 , 0 , 0 } }, // #97 [ref=5x]
- { InstDB::RWInfo::kCategoryGeneric , 28, { 9 , 0 , 0 , 0 , 0 , 0 } }, // #98 [ref=2x]
- { InstDB::RWInfo::kCategoryGeneric , 0 , { 2 , 3 , 0 , 0 , 0 , 0 } }, // #99 [ref=13x]
- { InstDB::RWInfo::kCategoryGeneric , 8 , { 11, 3 , 0 , 0 , 0 , 0 } }, // #100 [ref=1x]
- { InstDB::RWInfo::kCategoryGeneric , 7 , { 13, 0 , 0 , 0 , 0 , 0 } }, // #101 [ref=5x]
- { InstDB::RWInfo::kCategoryGeneric , 0 , { 3 , 0 , 0 , 0 , 0 , 0 } }, // #102 [ref=3x]
- { InstDB::RWInfo::kCategoryGeneric , 0 , { 49, 19, 0 , 0 , 0 , 0 } }, // #103 [ref=1x]
- { InstDB::RWInfo::kCategoryGeneric , 0 , { 55, 0 , 0 , 0 , 0 , 0 } }, // #104 [ref=3x]
- { InstDB::RWInfo::kCategoryGeneric , 5 , { 3 , 9 , 0 , 0 , 0 , 0 } }, // #105 [ref=2x]
- { InstDB::RWInfo::kCategoryGeneric , 0 , { 5 , 5 , 20, 0 , 0 , 0 } }, // #106 [ref=2x]
- { InstDB::RWInfo::kCategoryGeneric , 0 , { 7 , 7 , 20, 0 , 0 , 0 } }, // #107 [ref=1x]
- { InstDB::RWInfo::kCategoryGeneric , 0 , { 18, 28, 56, 0 , 0 , 0 } }, // #108 [ref=2x]
- { InstDB::RWInfo::kCategoryMov , 29, { 0 , 0 , 0 , 0 , 0 , 0 } }, // #109 [ref=1x]
- { InstDB::RWInfo::kCategoryGeneric , 30, { 10, 5 , 0 , 0 , 0 , 0 } }, // #110 [ref=6x]
- { InstDB::RWInfo::kCategoryGeneric , 0 , { 11, 3 , 0 , 0 , 0 , 0 } }, // #111 [ref=14x]
- { InstDB::RWInfo::kCategoryGeneric , 16, { 11, 43, 0 , 0 , 0 , 0 } }, // #112 [ref=1x]
- { InstDB::RWInfo::kCategoryGeneric , 0 , { 35, 57, 0 , 0 , 0 , 0 } }, // #113 [ref=1x]
- { InstDB::RWInfo::kCategoryMovh64 , 13, { 0 , 0 , 0 , 0 , 0 , 0 } }, // #114 [ref=2x]
- { InstDB::RWInfo::kCategoryGeneric , 0 , { 58, 7 , 0 , 0 , 0 , 0 } }, // #115 [ref=1x]
- { InstDB::RWInfo::kCategoryGeneric , 13, { 34, 7 , 0 , 0 , 0 , 0 } }, // #116 [ref=7x]
- { InstDB::RWInfo::kCategoryGeneric , 0 , { 53, 5 , 0 , 0 , 0 , 0 } }, // #117 [ref=2x]
- { InstDB::RWInfo::kCategoryGeneric , 28, { 42, 9 , 0 , 0 , 0 , 0 } }, // #118 [ref=2x]
- { InstDB::RWInfo::kCategoryGeneric , 0 , { 20, 19, 0 , 0 , 0 , 0 } }, // #119 [ref=1x]
- { InstDB::RWInfo::kCategoryGeneric , 14, { 11, 3 , 0 , 0 , 0 , 0 } }, // #120 [ref=3x]
- { InstDB::RWInfo::kCategoryGeneric , 6 , { 59, 41, 3 , 0 , 0 , 0 } }, // #121 [ref=1x]
- { InstDB::RWInfo::kCategoryGeneric , 6 , { 11, 11, 3 , 60, 0 , 0 } }, // #122 [ref=1x]
- { InstDB::RWInfo::kCategoryGeneric , 0 , { 16, 28, 0 , 0 , 0 , 0 } }, // #123 [ref=1x]
- { InstDB::RWInfo::kCategoryGeneric , 0 , { 16, 28, 29, 0 , 0 , 0 } }, // #124 [ref=1x]
- { InstDB::RWInfo::kCategoryGeneric , 10, { 3 , 0 , 0 , 0 , 0 , 0 } }, // #125 [ref=1x]
- { InstDB::RWInfo::kCategoryGeneric , 0 , { 50, 21, 0 , 0 , 0 , 0 } }, // #126 [ref=1x]
- { InstDB::RWInfo::kCategoryGeneric , 0 , { 50, 61, 0 , 0 , 0 , 0 } }, // #127 [ref=1x]
- { InstDB::RWInfo::kCategoryGeneric , 4 , { 25, 7 , 0 , 0 , 0 , 0 } }, // #128 [ref=18x]
- { InstDB::RWInfo::kCategoryGeneric , 3 , { 5 , 5 , 0 , 62, 16, 56 } }, // #129 [ref=2x]
- { InstDB::RWInfo::kCategoryGeneric , 3 , { 5 , 5 , 0 , 63, 16, 56 } }, // #130 [ref=2x]
- { InstDB::RWInfo::kCategoryGeneric , 3 , { 5 , 5 , 0 , 62, 0 , 0 } }, // #131 [ref=2x]
- { InstDB::RWInfo::kCategoryGeneric , 3 , { 5 , 5 , 0 , 63, 0 , 0 } }, // #132 [ref=2x]
- { InstDB::RWInfo::kCategoryGeneric , 31, { 53, 5 , 0 , 0 , 0 , 0 } }, // #133 [ref=2x]
- { InstDB::RWInfo::kCategoryGeneric , 32, { 34, 5 , 0 , 0 , 0 , 0 } }, // #134 [ref=2x]
- { InstDB::RWInfo::kCategoryGeneric , 33, { 47, 3 , 0 , 0 , 0 , 0 } }, // #135 [ref=1x]
- { InstDB::RWInfo::kCategoryGeneric , 3 , { 64, 5 , 0 , 0 , 0 , 0 } }, // #136 [ref=2x]
- { InstDB::RWInfo::kCategoryGeneric , 15, { 4 , 39, 0 , 0 , 0 , 0 } }, // #137 [ref=1x]
- { InstDB::RWInfo::kCategoryGeneric , 4 , { 4 , 7 , 0 , 0 , 0 , 0 } }, // #138 [ref=1x]
- { InstDB::RWInfo::kCategoryGeneric , 27, { 2 , 13, 0 , 0 , 0 , 0 } }, // #139 [ref=1x]
- { InstDB::RWInfo::kCategoryVmov1_8 , 0 , { 0 , 0 , 0 , 0 , 0 , 0 } }, // #140 [ref=2x]
- { InstDB::RWInfo::kCategoryGeneric , 5 , { 10, 9 , 0 , 0 , 0 , 0 } }, // #141 [ref=4x]
- { InstDB::RWInfo::kCategoryGeneric , 27, { 10, 13, 0 , 0 , 0 , 0 } }, // #142 [ref=2x]
- { InstDB::RWInfo::kCategoryGeneric , 10, { 65, 0 , 0 , 0 , 0 , 0 } }, // #143 [ref=1x]
- { InstDB::RWInfo::kCategoryGeneric , 3 , { 5 , 5 , 0 , 0 , 0 , 0 } }, // #144 [ref=1x]
- { InstDB::RWInfo::kCategoryGeneric , 10, { 60, 0 , 0 , 0 , 0 , 0 } }, // #145 [ref=1x]
- { InstDB::RWInfo::kCategoryGeneric , 10, { 2 , 66, 0 , 0 , 0 , 0 } }, // #146 [ref=8x]
- { InstDB::RWInfo::kCategoryGeneric , 5 , { 36, 9 , 0 , 0 , 0 , 0 } }, // #147 [ref=4x]
- { InstDB::RWInfo::kCategoryGeneric , 0 , { 11, 0 , 0 , 0 , 0 , 0 } }, // #148 [ref=6x]
- { InstDB::RWInfo::kCategoryGeneric , 0 , { 15, 67, 28, 0 , 0 , 0 } }, // #149 [ref=3x]
- { InstDB::RWInfo::kCategoryGeneric , 0 , { 15, 67, 0 , 0 , 0 , 0 } }, // #150 [ref=1x]
- { InstDB::RWInfo::kCategoryGeneric , 0 , { 15, 67, 62, 0 , 0 , 0 } }, // #151 [ref=1x]
- { InstDB::RWInfo::kCategoryGeneric , 0 , { 68, 0 , 0 , 0 , 0 , 0 } }, // #152 [ref=1x]
- { InstDB::RWInfo::kCategoryGeneric , 0 , { 21, 20, 0 , 0 , 0 , 0 } }, // #153 [ref=1x]
- { InstDB::RWInfo::kCategoryGeneric , 31, { 69, 0 , 0 , 0 , 0 , 0 } }, // #154 [ref=30x]
- { InstDB::RWInfo::kCategoryGeneric , 11, { 2 , 3 , 66, 0 , 0 , 0 } }, // #155 [ref=2x]
- { InstDB::RWInfo::kCategoryGeneric , 34, { 11, 0 , 0 , 0 , 0 , 0 } }, // #156 [ref=3x]
- { InstDB::RWInfo::kCategoryGeneric , 28, { 42, 0 , 0 , 0 , 0 , 0 } }, // #157 [ref=2x]
- { InstDB::RWInfo::kCategoryGeneric , 0 , { 20, 21, 0 , 0 , 0 , 0 } }, // #158 [ref=1x]
- { InstDB::RWInfo::kCategoryGeneric , 12, { 70, 43, 43, 43, 43, 5 } }, // #159 [ref=2x]
- { InstDB::RWInfo::kCategoryGeneric , 12, { 4 , 5 , 5 , 5 , 5 , 5 } }, // #160 [ref=2x]
- { InstDB::RWInfo::kCategoryGeneric , 35, { 10, 5 , 7 , 0 , 0 , 0 } }, // #161 [ref=8x]
- { InstDB::RWInfo::kCategoryGeneric , 36, { 10, 5 , 9 , 0 , 0 , 0 } }, // #162 [ref=9x]
- { InstDB::RWInfo::kCategoryGeneric , 6 , { 11, 3 , 3 , 3 , 0 , 0 } }, // #163 [ref=3x]
- { InstDB::RWInfo::kCategoryGeneric , 12, { 71, 5 , 0 , 0 , 0 , 0 } }, // #164 [ref=2x]
- { InstDB::RWInfo::kCategoryGeneric , 12, { 11, 5 , 0 , 0 , 0 , 0 } }, // #165 [ref=4x]
- { InstDB::RWInfo::kCategoryGeneric , 37, { 72, 73, 0 , 0 , 0 , 0 } }, // #166 [ref=4x]
- { InstDB::RWInfo::kCategoryGeneric , 38, { 11, 7 , 0 , 0 , 0 , 0 } }, // #167 [ref=1x]
- { InstDB::RWInfo::kCategoryGeneric , 39, { 11, 9 , 0 , 0 , 0 , 0 } }, // #168 [ref=1x]
- { InstDB::RWInfo::kCategoryGeneric , 35, { 11, 5 , 7 , 0 , 0 , 0 } }, // #169 [ref=1x]
- { InstDB::RWInfo::kCategoryGeneric , 36, { 11, 5 , 9 , 0 , 0 , 0 } }, // #170 [ref=1x]
- { InstDB::RWInfo::kCategoryGeneric , 11, { 11, 3 , 0 , 0 , 0 , 0 } }, // #171 [ref=7x]
- { InstDB::RWInfo::kCategoryVmov2_1 , 40, { 0 , 0 , 0 , 0 , 0 , 0 } }, // #172 [ref=14x]
- { InstDB::RWInfo::kCategoryVmov1_2 , 14, { 0 , 0 , 0 , 0 , 0 , 0 } }, // #173 [ref=7x]
- { InstDB::RWInfo::kCategoryVmov1_2 , 41, { 0 , 0 , 0 , 0 , 0 , 0 } }, // #174 [ref=10x]
- { InstDB::RWInfo::kCategoryGeneric , 35, { 10, 74, 7 , 0 , 0 , 0 } }, // #175 [ref=1x]
- { InstDB::RWInfo::kCategoryGeneric , 42, { 10, 57, 3 , 0 , 0 , 0 } }, // #176 [ref=2x]
- { InstDB::RWInfo::kCategoryGeneric , 42, { 10, 74, 3 , 0 , 0 , 0 } }, // #177 [ref=2x]
- { InstDB::RWInfo::kCategoryGeneric , 36, { 10, 57, 9 , 0 , 0 , 0 } }, // #178 [ref=1x]
- { InstDB::RWInfo::kCategoryGeneric , 43, { 10, 5 , 5 , 0 , 0 , 0 } }, // #179 [ref=9x]
- { InstDB::RWInfo::kCategoryGeneric , 44, { 72, 43, 0 , 0 , 0 , 0 } }, // #180 [ref=6x]
- { InstDB::RWInfo::kCategoryGeneric , 45, { 10, 73, 0 , 0 , 0 , 0 } }, // #181 [ref=2x]
- { InstDB::RWInfo::kCategoryGeneric , 45, { 10, 3 , 0 , 0 , 0 , 0 } }, // #182 [ref=4x]
- { InstDB::RWInfo::kCategoryGeneric , 46, { 71, 43, 0 , 0 , 0 , 0 } }, // #183 [ref=4x]
- { InstDB::RWInfo::kCategoryGeneric , 6 , { 2 , 3 , 3 , 0 , 0 , 0 } }, // #184 [ref=60x]
- { InstDB::RWInfo::kCategoryGeneric , 35, { 4 , 57, 7 , 0 , 0 , 0 } }, // #185 [ref=1x]
- { InstDB::RWInfo::kCategoryGeneric , 36, { 4 , 74, 9 , 0 , 0 , 0 } }, // #186 [ref=1x]
- { InstDB::RWInfo::kCategoryGeneric , 35, { 6 , 7 , 7 , 0 , 0 , 0 } }, // #187 [ref=11x]
- { InstDB::RWInfo::kCategoryGeneric , 36, { 8 , 9 , 9 , 0 , 0 , 0 } }, // #188 [ref=11x]
- { InstDB::RWInfo::kCategoryGeneric , 47, { 11, 3 , 3 , 3 , 0 , 0 } }, // #189 [ref=15x]
- { InstDB::RWInfo::kCategoryGeneric , 48, { 34, 7 , 7 , 7 , 0 , 0 } }, // #190 [ref=4x]
- { InstDB::RWInfo::kCategoryGeneric , 49, { 42, 9 , 9 , 9 , 0 , 0 } }, // #191 [ref=4x]
- { InstDB::RWInfo::kCategoryGeneric , 35, { 25, 7 , 7 , 0 , 0 , 0 } }, // #192 [ref=1x]
- { InstDB::RWInfo::kCategoryGeneric , 36, { 75, 9 , 9 , 0 , 0 , 0 } }, // #193 [ref=1x]
- { InstDB::RWInfo::kCategoryGeneric , 14, { 34, 3 , 0 , 0 , 0 , 0 } }, // #194 [ref=2x]
- { InstDB::RWInfo::kCategoryGeneric , 5 , { 34, 9 , 0 , 0 , 0 , 0 } }, // #195 [ref=1x]
- { InstDB::RWInfo::kCategoryGeneric , 5 , { 42, 9 , 0 , 0 , 0 , 0 } }, // #196 [ref=1x]
- { InstDB::RWInfo::kCategoryGeneric , 8 , { 2 , 3 , 2 , 0 , 0 , 0 } }, // #197 [ref=2x]
- { InstDB::RWInfo::kCategoryGeneric , 0 , { 2 , 3 , 2 , 0 , 0 , 0 } }, // #198 [ref=4x]
- { InstDB::RWInfo::kCategoryGeneric , 18, { 4 , 3 , 4 , 0 , 0 , 0 } }, // #199 [ref=2x]
- { InstDB::RWInfo::kCategoryGeneric , 35, { 10, 57, 7 , 0 , 0 , 0 } }, // #200 [ref=11x]
- { InstDB::RWInfo::kCategoryGeneric , 36, { 10, 74, 9 , 0 , 0 , 0 } }, // #201 [ref=13x]
- { InstDB::RWInfo::kCategoryGeneric , 43, { 71, 73, 5 , 0 , 0 , 0 } }, // #202 [ref=2x]
- { InstDB::RWInfo::kCategoryGeneric , 43, { 11, 3 , 5 , 0 , 0 , 0 } }, // #203 [ref=4x]
- { InstDB::RWInfo::kCategoryGeneric , 50, { 72, 43, 73, 0 , 0 , 0 } }, // #204 [ref=4x]
- { InstDB::RWInfo::kCategoryVmaskmov , 0 , { 0 , 0 , 0 , 0 , 0 , 0 } }, // #205 [ref=4x]
- { InstDB::RWInfo::kCategoryGeneric , 13, { 34, 0 , 0 , 0 , 0 , 0 } }, // #206 [ref=2x]
- { InstDB::RWInfo::kCategoryGeneric , 0 , { 21, 0 , 0 , 0 , 0 , 0 } }, // #207 [ref=2x]
- { InstDB::RWInfo::kCategoryGeneric , 51, { 11, 3 , 0 , 0 , 0 , 0 } }, // #208 [ref=12x]
- { InstDB::RWInfo::kCategoryVmovddup , 52, { 0 , 0 , 0 , 0 , 0 , 0 } }, // #209 [ref=1x]
- { InstDB::RWInfo::kCategoryGeneric , 0 , { 10, 57, 57, 0 , 0 , 0 } }, // #210 [ref=1x]
- { InstDB::RWInfo::kCategoryGeneric , 13, { 34, 57, 0 , 0 , 0 , 0 } }, // #211 [ref=2x]
- { InstDB::RWInfo::kCategoryGeneric , 13, { 10, 7 , 7 , 0 , 0 , 0 } }, // #212 [ref=2x]
- { InstDB::RWInfo::kCategoryGeneric , 0 , { 10, 7 , 7 , 0 , 0 , 0 } }, // #213 [ref=1x]
- { InstDB::RWInfo::kCategoryGeneric , 13, { 10, 57, 7 , 0 , 0 , 0 } }, // #214 [ref=2x]
- { InstDB::RWInfo::kCategoryVmovmskpd , 0 , { 0 , 0 , 0 , 0 , 0 , 0 } }, // #215 [ref=1x]
- { InstDB::RWInfo::kCategoryVmovmskps , 0 , { 0 , 0 , 0 , 0 , 0 , 0 } }, // #216 [ref=1x]
- { InstDB::RWInfo::kCategoryGeneric , 53, { 34, 7 , 0 , 0 , 0 , 0 } }, // #217 [ref=1x]
- { InstDB::RWInfo::kCategoryGeneric , 0 , { 10, 57, 7 , 0 , 0 , 0 } }, // #218 [ref=1x]
- { InstDB::RWInfo::kCategoryGeneric , 0 , { 10, 74, 9 , 0 , 0 , 0 } }, // #219 [ref=1x]
- { InstDB::RWInfo::kCategoryGeneric , 13, { 7 , 0 , 0 , 0 , 0 , 0 } }, // #220 [ref=2x]
- { InstDB::RWInfo::kCategoryGeneric , 0 , { 76, 0 , 0 , 0 , 0 , 0 } }, // #221 [ref=1x]
- { InstDB::RWInfo::kCategoryGeneric , 2 , { 3 , 3 , 0 , 0 , 0 , 0 } }, // #222 [ref=4x]
- { InstDB::RWInfo::kCategoryGeneric , 12, { 72, 43, 43, 43, 43, 5 } }, // #223 [ref=2x]
- { InstDB::RWInfo::kCategoryGeneric , 15, { 11, 39, 0 , 0 , 0 , 0 } }, // #224 [ref=1x]
- { InstDB::RWInfo::kCategoryGeneric , 0 , { 11, 7 , 0 , 0 , 0 , 0 } }, // #225 [ref=6x]
- { InstDB::RWInfo::kCategoryGeneric , 27, { 11, 13, 0 , 0 , 0 , 0 } }, // #226 [ref=1x]
- { InstDB::RWInfo::kCategoryGeneric , 6 , { 34, 3 , 3 , 0 , 0 , 0 } }, // #227 [ref=17x]
- { InstDB::RWInfo::kCategoryGeneric , 50, { 71, 73, 73, 0 , 0 , 0 } }, // #228 [ref=2x]
- { InstDB::RWInfo::kCategoryGeneric , 22, { 11, 3 , 3 , 0 , 0 , 0 } }, // #229 [ref=4x]
- { InstDB::RWInfo::kCategoryGeneric , 7 , { 47, 5 , 0 , 0 , 0 , 0 } }, // #230 [ref=1x]
- { InstDB::RWInfo::kCategoryGeneric , 54, { 10, 5 , 39, 0 , 0 , 0 } }, // #231 [ref=1x]
- { InstDB::RWInfo::kCategoryGeneric , 55, { 10, 5 , 13, 0 , 0 , 0 } }, // #232 [ref=1x]
- { InstDB::RWInfo::kCategoryGeneric , 43, { 10, 5 , 5 , 5 , 0 , 0 } }, // #233 [ref=12x]
- { InstDB::RWInfo::kCategoryGeneric , 0 , { 34, 3 , 0 , 0 , 0 , 0 } }, // #234 [ref=4x]
- { InstDB::RWInfo::kCategoryVmov1_4 , 56, { 0 , 0 , 0 , 0 , 0 , 0 } }, // #235 [ref=6x]
- { InstDB::RWInfo::kCategoryVmov1_8 , 57, { 0 , 0 , 0 , 0 , 0 , 0 } }, // #236 [ref=3x]
- { InstDB::RWInfo::kCategoryVmov4_1 , 58, { 0 , 0 , 0 , 0 , 0 , 0 } }, // #237 [ref=4x]
- { InstDB::RWInfo::kCategoryVmov8_1 , 59, { 0 , 0 , 0 , 0 , 0 , 0 } }, // #238 [ref=2x]
- { InstDB::RWInfo::kCategoryGeneric , 60, { 10, 5 , 5 , 5 , 0 , 0 } }, // #239 [ref=1x]
- { InstDB::RWInfo::kCategoryGeneric , 61, { 10, 5 , 5 , 0 , 0 , 0 } }, // #240 [ref=12x]
- { InstDB::RWInfo::kCategoryGeneric , 18, { 11, 3 , 0 , 0 , 0 , 0 } }, // #241 [ref=2x]
- { InstDB::RWInfo::kCategoryGeneric , 22, { 11, 3 , 5 , 0 , 0 , 0 } }, // #242 [ref=9x]
- { InstDB::RWInfo::kCategoryGeneric , 62, { 11, 3 , 0 , 0 , 0 , 0 } }, // #243 [ref=2x]
- { InstDB::RWInfo::kCategoryGeneric , 0 , { 56, 16, 28, 0 , 0 , 0 } }, // #244 [ref=2x]
- { InstDB::RWInfo::kCategoryGeneric , 11, { 2 , 2 , 0 , 0 , 0 , 0 } }, // #245 [ref=1x]
- { InstDB::RWInfo::kCategoryGeneric , 51, { 2 , 2 , 0 , 0 , 0 , 0 } }, // #246 [ref=1x]
- { InstDB::RWInfo::kCategoryGeneric , 8 , { 3 , 56, 16, 0 , 0 , 0 } }, // #247 [ref=4x]
- { InstDB::RWInfo::kCategoryGeneric , 8 , { 11, 56, 16, 0 , 0 , 0 } } // #248 [ref=8x]
+ { InstDB::RWInfo::kCategoryGeneric , 2 , { 2 , 3 , 0 , 0 , 0 , 0 } }, // #3 [ref=99x]
+ { InstDB::RWInfo::kCategoryGeneric , 3 , { 4 , 5 , 0 , 0 , 0 , 0 } }, // #4 [ref=55x]
+ { InstDB::RWInfo::kCategoryGeneric , 4 , { 6 , 7 , 0 , 0 , 0 , 0 } }, // #5 [ref=6x]
+ { InstDB::RWInfo::kCategoryGeneric , 5 , { 8 , 9 , 0 , 0 , 0 , 0 } }, // #6 [ref=6x]
+ { InstDB::RWInfo::kCategoryGeneric , 3 , { 10, 5 , 0 , 0 , 0 , 0 } }, // #7 [ref=26x]
+ { InstDB::RWInfo::kCategoryGeneric , 7 , { 12, 13, 0 , 0 , 0 , 0 } }, // #8 [ref=1x]
+ { InstDB::RWInfo::kCategoryGeneric , 2 , { 11, 3 , 0 , 0 , 0 , 0 } }, // #9 [ref=65x]
+ { InstDB::RWInfo::kCategoryGeneric , 2 , { 5 , 3 , 0 , 0 , 0 , 0 } }, // #10 [ref=3x]
+ { InstDB::RWInfo::kCategoryGeneric , 8 , { 10, 3 , 0 , 0 , 0 , 0 } }, // #11 [ref=2x]
+ { InstDB::RWInfo::kCategoryGeneric , 9 , { 10, 5 , 0 , 0 , 0 , 0 } }, // #12 [ref=1x]
+ { InstDB::RWInfo::kCategoryGeneric , 8 , { 11, 5 , 0 , 0 , 0 , 0 } }, // #13 [ref=1x]
+ { InstDB::RWInfo::kCategoryGeneric , 0 , { 3 , 3 , 0 , 0 , 0 , 0 } }, // #14 [ref=1x]
+ { InstDB::RWInfo::kCategoryGeneric , 10, { 3 , 3 , 0 , 0 , 0 , 0 } }, // #15 [ref=2x]
+ { InstDB::RWInfo::kCategoryGeneric , 10, { 2 , 3 , 0 , 0 , 0 , 0 } }, // #16 [ref=3x]
+ { InstDB::RWInfo::kCategoryGeneric , 0 , { 15, 16, 0 , 0 , 0 , 0 } }, // #17 [ref=1x]
+ { InstDB::RWInfo::kCategoryGeneric , 1 , { 3 , 3 , 0 , 0 , 0 , 0 } }, // #18 [ref=1x]
+ { InstDB::RWInfo::kCategoryGeneric , 0 , { 19, 20, 0 , 0 , 0 , 0 } }, // #19 [ref=1x]
+ { InstDB::RWInfo::kCategoryGeneric , 4 , { 7 , 7 , 0 , 0 , 0 , 0 } }, // #20 [ref=4x]
+ { InstDB::RWInfo::kCategoryGeneric , 5 , { 9 , 9 , 0 , 0 , 0 , 0 } }, // #21 [ref=4x]
+ { InstDB::RWInfo::kCategoryGeneric , 0 , { 32, 33, 0 , 0 , 0 , 0 } }, // #22 [ref=1x]
+ { InstDB::RWInfo::kCategoryGeneric , 14, { 2 , 3 , 0 , 0 , 0 , 0 } }, // #23 [ref=1x]
+ { InstDB::RWInfo::kCategoryGeneric , 4 , { 10, 7 , 0 , 0 , 0 , 0 } }, // #24 [ref=10x]
+ { InstDB::RWInfo::kCategoryGeneric , 3 , { 34, 5 , 0 , 0 , 0 , 0 } }, // #25 [ref=5x]
+ { InstDB::RWInfo::kCategoryGeneric , 4 , { 35, 7 , 0 , 0 , 0 , 0 } }, // #26 [ref=2x]
+ { InstDB::RWInfo::kCategoryGeneric , 4 , { 34, 7 , 0 , 0 , 0 , 0 } }, // #27 [ref=11x]
+ { InstDB::RWInfo::kCategoryGeneric , 4 , { 11, 7 , 0 , 0 , 0 , 0 } }, // #28 [ref=9x]
+ { InstDB::RWInfo::kCategoryGeneric , 4 , { 36, 7 , 0 , 0 , 0 , 0 } }, // #29 [ref=1x]
+ { InstDB::RWInfo::kCategoryGeneric , 14, { 35, 3 , 0 , 0 , 0 , 0 } }, // #30 [ref=1x]
+ { InstDB::RWInfo::kCategoryGeneric , 14, { 36, 3 , 0 , 0 , 0 , 0 } }, // #31 [ref=1x]
+ { InstDB::RWInfo::kCategoryGeneric , 5 , { 35, 9 , 0 , 0 , 0 , 0 } }, // #32 [ref=1x]
+ { InstDB::RWInfo::kCategoryGeneric , 5 , { 11, 9 , 0 , 0 , 0 , 0 } }, // #33 [ref=7x]
+ { InstDB::RWInfo::kCategoryGeneric , 0 , { 37, 38, 0 , 0 , 0 , 0 } }, // #34 [ref=1x]
+ { InstDB::RWInfo::kCategoryGeneric , 15, { 1 , 39, 0 , 0 , 0 , 0 } }, // #35 [ref=3x]
+ { InstDB::RWInfo::kCategoryGeneric , 16, { 11, 42, 0 , 0 , 0 , 0 } }, // #36 [ref=3x]
+ { InstDB::RWInfo::kCategoryGeneric , 0 , { 4 , 5 , 0 , 0 , 0 , 0 } }, // #37 [ref=2x]
+ { InstDB::RWInfo::kCategoryGeneric , 0 , { 44, 45, 0 , 0 , 0 , 0 } }, // #38 [ref=6x]
+ { InstDB::RWInfo::kCategoryImul , 2 , { 0 , 0 , 0 , 0 , 0 , 0 } }, // #39 [ref=1x]
+ { InstDB::RWInfo::kCategoryGeneric , 0 , { 49, 50, 0 , 0 , 0 , 0 } }, // #40 [ref=1x]
+ { InstDB::RWInfo::kCategoryGeneric , 0 , { 51, 50, 0 , 0 , 0 , 0 } }, // #41 [ref=1x]
+ { InstDB::RWInfo::kCategoryGeneric , 12, { 3 , 5 , 0 , 0 , 0 , 0 } }, // #42 [ref=3x]
+ { InstDB::RWInfo::kCategoryGeneric , 0 , { 21, 28, 0 , 0 , 0 , 0 } }, // #43 [ref=1x]
+ { InstDB::RWInfo::kCategoryGeneric , 0 , { 52, 0 , 0 , 0 , 0 , 0 } }, // #44 [ref=1x]
+ { InstDB::RWInfo::kCategoryGeneric , 23, { 53, 39, 0 , 0 , 0 , 0 } }, // #45 [ref=1x]
+ { InstDB::RWInfo::kCategoryGeneric , 24, { 43, 9 , 0 , 0 , 0 , 0 } }, // #46 [ref=4x]
+ { InstDB::RWInfo::kCategoryGeneric , 25, { 34, 7 , 0 , 0 , 0 , 0 } }, // #47 [ref=3x]
+ { InstDB::RWInfo::kCategoryGeneric , 26, { 47, 13, 0 , 0 , 0 , 0 } }, // #48 [ref=1x]
+ { InstDB::RWInfo::kCategoryGeneric , 0 , { 53, 39, 0 , 0 , 0 , 0 } }, // #49 [ref=1x]
+ { InstDB::RWInfo::kCategoryGeneric , 0 , { 43, 9 , 0 , 0 , 0 , 0 } }, // #50 [ref=1x]
+ { InstDB::RWInfo::kCategoryGeneric , 0 , { 34, 7 , 0 , 0 , 0 , 0 } }, // #51 [ref=3x]
+ { InstDB::RWInfo::kCategoryGeneric , 0 , { 47, 13, 0 , 0 , 0 , 0 } }, // #52 [ref=1x]
+ { InstDB::RWInfo::kCategoryGeneric , 0 , { 39, 39, 0 , 0 , 0 , 0 } }, // #53 [ref=2x]
+ { InstDB::RWInfo::kCategoryGeneric , 0 , { 9 , 9 , 0 , 0 , 0 , 0 } }, // #54 [ref=2x]
+ { InstDB::RWInfo::kCategoryGeneric , 0 , { 7 , 7 , 0 , 0 , 0 , 0 } }, // #55 [ref=2x]
+ { InstDB::RWInfo::kCategoryGeneric , 0 , { 13, 13, 0 , 0 , 0 , 0 } }, // #56 [ref=2x]
+ { InstDB::RWInfo::kCategoryGeneric , 27, { 11, 3 , 0 , 0 , 0 , 0 } }, // #57 [ref=2x]
+ { InstDB::RWInfo::kCategoryGeneric , 12, { 10, 5 , 0 , 0 , 0 , 0 } }, // #58 [ref=5x]
+ { InstDB::RWInfo::kCategoryGeneric , 0 , { 2 , 3 , 0 , 0 , 0 , 0 } }, // #59 [ref=13x]
+ { InstDB::RWInfo::kCategoryGeneric , 8 , { 11, 3 , 0 , 0 , 0 , 0 } }, // #60 [ref=1x]
+ { InstDB::RWInfo::kCategoryGeneric , 0 , { 49, 19, 0 , 0 , 0 , 0 } }, // #61 [ref=1x]
+ { InstDB::RWInfo::kCategoryGeneric , 0 , { 55, 0 , 0 , 0 , 0 , 0 } }, // #62 [ref=3x]
+ { InstDB::RWInfo::kCategoryMov , 29, { 0 , 0 , 0 , 0 , 0 , 0 } }, // #63 [ref=1x]
+ { InstDB::RWInfo::kCategoryGeneric , 30, { 10, 5 , 0 , 0 , 0 , 0 } }, // #64 [ref=6x]
+ { InstDB::RWInfo::kCategoryGeneric , 0 , { 11, 3 , 0 , 0 , 0 , 0 } }, // #65 [ref=14x]
+ { InstDB::RWInfo::kCategoryGeneric , 0 , { 35, 57, 0 , 0 , 0 , 0 } }, // #66 [ref=1x]
+ { InstDB::RWInfo::kCategoryMovh64 , 13, { 0 , 0 , 0 , 0 , 0 , 0 } }, // #67 [ref=2x]
+ { InstDB::RWInfo::kCategoryGeneric , 0 , { 58, 7 , 0 , 0 , 0 , 0 } }, // #68 [ref=1x]
+ { InstDB::RWInfo::kCategoryGeneric , 13, { 34, 7 , 0 , 0 , 0 , 0 } }, // #69 [ref=7x]
+ { InstDB::RWInfo::kCategoryGeneric , 0 , { 53, 5 , 0 , 0 , 0 , 0 } }, // #70 [ref=2x]
+ { InstDB::RWInfo::kCategoryGeneric , 28, { 43, 9 , 0 , 0 , 0 , 0 } }, // #71 [ref=2x]
+ { InstDB::RWInfo::kCategoryGeneric , 0 , { 20, 19, 0 , 0 , 0 , 0 } }, // #72 [ref=1x]
+ { InstDB::RWInfo::kCategoryGeneric , 14, { 11, 3 , 0 , 0 , 0 , 0 } }, // #73 [ref=3x]
+ { InstDB::RWInfo::kCategoryGeneric , 0 , { 16, 28, 0 , 0 , 0 , 0 } }, // #74 [ref=1x]
+ { InstDB::RWInfo::kCategoryGeneric , 0 , { 50, 21, 0 , 0 , 0 , 0 } }, // #75 [ref=1x]
+ { InstDB::RWInfo::kCategoryGeneric , 0 , { 50, 61, 0 , 0 , 0 , 0 } }, // #76 [ref=1x]
+ { InstDB::RWInfo::kCategoryGeneric , 4 , { 25, 7 , 0 , 0 , 0 , 0 } }, // #77 [ref=18x]
+ { InstDB::RWInfo::kCategoryGeneric , 3 , { 64, 5 , 0 , 0 , 0 , 0 } }, // #78 [ref=2x]
+ { InstDB::RWInfo::kCategoryVmov1_8 , 0 , { 0 , 0 , 0 , 0 , 0 , 0 } }, // #79 [ref=2x]
+ { InstDB::RWInfo::kCategoryGeneric , 5 , { 10, 9 , 0 , 0 , 0 , 0 } }, // #80 [ref=4x]
+ { InstDB::RWInfo::kCategoryGeneric , 27, { 10, 13, 0 , 0 , 0 , 0 } }, // #81 [ref=2x]
+ { InstDB::RWInfo::kCategoryGeneric , 0 , { 4 , 0 , 0 , 0 , 0 , 0 } }, // #82 [ref=2x]
+ { InstDB::RWInfo::kCategoryGeneric , 3 , { 5 , 5 , 0 , 0 , 0 , 0 } }, // #83 [ref=1x]
+ { InstDB::RWInfo::kCategoryGeneric , 10, { 2 , 66, 0 , 0 , 0 , 0 } }, // #84 [ref=8x]
+ { InstDB::RWInfo::kCategoryGeneric , 5 , { 36, 9 , 0 , 0 , 0 , 0 } }, // #85 [ref=3x]
+ { InstDB::RWInfo::kCategoryGeneric , 0 , { 15, 67, 0 , 0 , 0 , 0 } }, // #86 [ref=1x]
+ { InstDB::RWInfo::kCategoryGeneric , 0 , { 21, 20, 0 , 0 , 0 , 0 } }, // #87 [ref=1x]
+ { InstDB::RWInfo::kCategoryGeneric , 0 , { 20, 21, 0 , 0 , 0 , 0 } }, // #88 [ref=1x]
+ { InstDB::RWInfo::kCategoryGeneric , 8 , { 70, 3 , 0 , 0 , 0 , 0 } }, // #89 [ref=2x]
+ { InstDB::RWInfo::kCategoryGeneric , 8 , { 11, 42, 0 , 0 , 0 , 0 } }, // #90 [ref=1x]
+ { InstDB::RWInfo::kCategoryGeneric , 12, { 72, 5 , 0 , 0 , 0 , 0 } }, // #91 [ref=2x]
+ { InstDB::RWInfo::kCategoryGeneric , 12, { 11, 5 , 0 , 0 , 0 , 0 } }, // #92 [ref=4x]
+ { InstDB::RWInfo::kCategoryGeneric , 37, { 70, 73, 0 , 0 , 0 , 0 } }, // #93 [ref=4x]
+ { InstDB::RWInfo::kCategoryGeneric , 38, { 11, 7 , 0 , 0 , 0 , 0 } }, // #94 [ref=1x]
+ { InstDB::RWInfo::kCategoryGeneric , 39, { 11, 9 , 0 , 0 , 0 , 0 } }, // #95 [ref=1x]
+ { InstDB::RWInfo::kCategoryGeneric , 11, { 11, 3 , 0 , 0 , 0 , 0 } }, // #96 [ref=7x]
+ { InstDB::RWInfo::kCategoryVmov2_1 , 40, { 0 , 0 , 0 , 0 , 0 , 0 } }, // #97 [ref=14x]
+ { InstDB::RWInfo::kCategoryVmov1_2 , 14, { 0 , 0 , 0 , 0 , 0 , 0 } }, // #98 [ref=7x]
+ { InstDB::RWInfo::kCategoryGeneric , 44, { 70, 42, 0 , 0 , 0 , 0 } }, // #99 [ref=6x]
+ { InstDB::RWInfo::kCategoryGeneric , 5 , { 43, 9 , 0 , 0 , 0 , 0 } }, // #100 [ref=1x]
+ { InstDB::RWInfo::kCategoryGeneric , 51, { 11, 3 , 0 , 0 , 0 , 0 } }, // #101 [ref=12x]
+ { InstDB::RWInfo::kCategoryVmovddup , 52, { 0 , 0 , 0 , 0 , 0 , 0 } }, // #102 [ref=1x]
+ { InstDB::RWInfo::kCategoryGeneric , 13, { 34, 57, 0 , 0 , 0 , 0 } }, // #103 [ref=2x]
+ { InstDB::RWInfo::kCategoryVmovmskpd , 0 , { 0 , 0 , 0 , 0 , 0 , 0 } }, // #104 [ref=1x]
+ { InstDB::RWInfo::kCategoryVmovmskps , 0 , { 0 , 0 , 0 , 0 , 0 , 0 } }, // #105 [ref=1x]
+ { InstDB::RWInfo::kCategoryGeneric , 53, { 34, 7 , 0 , 0 , 0 , 0 } }, // #106 [ref=1x]
+ { InstDB::RWInfo::kCategoryGeneric , 2 , { 3 , 3 , 0 , 0 , 0 , 0 } }, // #107 [ref=4x]
+ { InstDB::RWInfo::kCategoryGeneric , 15, { 11, 39, 0 , 0 , 0 , 0 } }, // #108 [ref=1x]
+ { InstDB::RWInfo::kCategoryGeneric , 0 , { 11, 7 , 0 , 0 , 0 , 0 } }, // #109 [ref=6x]
+ { InstDB::RWInfo::kCategoryGeneric , 27, { 11, 13, 0 , 0 , 0 , 0 } }, // #110 [ref=1x]
+ { InstDB::RWInfo::kCategoryGeneric , 0 , { 34, 3 , 0 , 0 , 0 , 0 } }, // #111 [ref=4x]
+ { InstDB::RWInfo::kCategoryVmov1_4 , 57, { 0 , 0 , 0 , 0 , 0 , 0 } }, // #112 [ref=6x]
+ { InstDB::RWInfo::kCategoryVmov1_2 , 41, { 0 , 0 , 0 , 0 , 0 , 0 } }, // #113 [ref=9x]
+ { InstDB::RWInfo::kCategoryVmov1_8 , 58, { 0 , 0 , 0 , 0 , 0 , 0 } }, // #114 [ref=3x]
+ { InstDB::RWInfo::kCategoryVmov4_1 , 59, { 0 , 0 , 0 , 0 , 0 , 0 } }, // #115 [ref=4x]
+ { InstDB::RWInfo::kCategoryVmov8_1 , 60, { 0 , 0 , 0 , 0 , 0 , 0 } }, // #116 [ref=2x]
+ { InstDB::RWInfo::kCategoryGeneric , 18, { 11, 3 , 0 , 0 , 0 , 0 } }, // #117 [ref=2x]
+ { InstDB::RWInfo::kCategoryGeneric , 11, { 2 , 2 , 0 , 0 , 0 , 0 } }, // #118 [ref=1x]
+ { InstDB::RWInfo::kCategoryGeneric , 51, { 2 , 2 , 0 , 0 , 0 , 0 } } // #119 [ref=1x]
+};
+
+const InstDB::RWInfo InstDB::rwInfoB[] = {
+ { InstDB::RWInfo::kCategoryGeneric , 0 , { 0 , 0 , 0 , 0 , 0 , 0 } }, // #0 [ref=727x]
+ { InstDB::RWInfo::kCategoryGeneric , 0 , { 1 , 0 , 0 , 0 , 0 , 0 } }, // #1 [ref=5x]
+ { InstDB::RWInfo::kCategoryGeneric , 3 , { 10, 5 , 0 , 0 , 0 , 0 } }, // #2 [ref=7x]
+ { InstDB::RWInfo::kCategoryGeneric , 6 , { 11, 3 , 3 , 0 , 0 , 0 } }, // #3 [ref=186x]
+ { InstDB::RWInfo::kCategoryGeneric , 2 , { 11, 3 , 3 , 0 , 0 , 0 } }, // #4 [ref=5x]
+ { InstDB::RWInfo::kCategoryGeneric , 3 , { 4 , 5 , 0 , 0 , 0 , 0 } }, // #5 [ref=14x]
+ { InstDB::RWInfo::kCategoryGeneric , 3 , { 4 , 5 , 14, 0 , 0 , 0 } }, // #6 [ref=4x]
+ { InstDB::RWInfo::kCategoryGeneric , 0 , { 2 , 0 , 0 , 0 , 0 , 0 } }, // #7 [ref=1x]
+ { InstDB::RWInfo::kCategoryGeneric , 11, { 3 , 0 , 0 , 0 , 0 , 0 } }, // #8 [ref=2x]
+ { InstDB::RWInfo::kCategoryGeneric , 0 , { 17, 0 , 0 , 0 , 0 , 0 } }, // #9 [ref=1x]
+ { InstDB::RWInfo::kCategoryGeneric , 8 , { 3 , 0 , 0 , 0 , 0 , 0 } }, // #10 [ref=34x]
+ { InstDB::RWInfo::kCategoryGeneric , 0 , { 18, 0 , 0 , 0 , 0 , 0 } }, // #11 [ref=1x]
+ { InstDB::RWInfo::kCategoryGeneric , 4 , { 6 , 7 , 0 , 0 , 0 , 0 } }, // #12 [ref=1x]
+ { InstDB::RWInfo::kCategoryGeneric , 5 , { 8 , 9 , 0 , 0 , 0 , 0 } }, // #13 [ref=1x]
+ { InstDB::RWInfo::kCategoryGeneric , 11, { 2 , 3 , 21, 0 , 0 , 0 } }, // #14 [ref=1x]
+ { InstDB::RWInfo::kCategoryGeneric , 12, { 4 , 22, 17, 23, 24, 0 } }, // #15 [ref=1x]
+ { InstDB::RWInfo::kCategoryGeneric , 13, { 25, 26, 27, 28, 29, 0 } }, // #16 [ref=1x]
+ { InstDB::RWInfo::kCategoryGeneric , 0 , { 27, 30, 31, 15, 0 , 0 } }, // #17 [ref=1x]
+ { InstDB::RWInfo::kCategoryGeneric , 0 , { 27, 0 , 0 , 0 , 0 , 0 } }, // #18 [ref=2x]
+ { InstDB::RWInfo::kCategoryGeneric , 10, { 2 , 0 , 0 , 0 , 0 , 0 } }, // #19 [ref=4x]
+ { InstDB::RWInfo::kCategoryGeneric , 6 , { 40, 41, 3 , 0 , 0 , 0 } }, // #20 [ref=2x]
+ { InstDB::RWInfo::kCategoryGeneric , 17, { 43, 5 , 0 , 0 , 0 , 0 } }, // #21 [ref=4x]
+ { InstDB::RWInfo::kCategoryGeneric , 0 , { 4 , 0 , 0 , 0 , 0 , 0 } }, // #22 [ref=1x]
+ { InstDB::RWInfo::kCategoryGeneric , 18, { 3 , 0 , 0 , 0 , 0 , 0 } }, // #23 [ref=15x]
+ { InstDB::RWInfo::kCategoryGeneric , 0 , { 44, 0 , 0 , 0 , 0 , 0 } }, // #24 [ref=16x]
+ { InstDB::RWInfo::kCategoryGeneric , 19, { 45, 0 , 0 , 0 , 0 , 0 } }, // #25 [ref=1x]
+ { InstDB::RWInfo::kCategoryGeneric , 19, { 46, 0 , 0 , 0 , 0 , 0 } }, // #26 [ref=1x]
+ { InstDB::RWInfo::kCategoryGeneric , 20, { 3 , 0 , 0 , 0 , 0 , 0 } }, // #27 [ref=3x]
+ { InstDB::RWInfo::kCategoryGeneric , 0 , { 45, 0 , 0 , 0 , 0 , 0 } }, // #28 [ref=6x]
+ { InstDB::RWInfo::kCategoryGeneric , 18, { 11, 0 , 0 , 0 , 0 , 0 } }, // #29 [ref=3x]
+ { InstDB::RWInfo::kCategoryGeneric , 21, { 13, 0 , 0 , 0 , 0 , 0 } }, // #30 [ref=1x]
+ { InstDB::RWInfo::kCategoryGeneric , 8 , { 11, 0 , 0 , 0 , 0 , 0 } }, // #31 [ref=8x]
+ { InstDB::RWInfo::kCategoryGeneric , 21, { 47, 0 , 0 , 0 , 0 , 0 } }, // #32 [ref=2x]
+ { InstDB::RWInfo::kCategoryGeneric , 7 , { 48, 0 , 0 , 0 , 0 , 0 } }, // #33 [ref=2x]
+ { InstDB::RWInfo::kCategoryGeneric , 20, { 11, 0 , 0 , 0 , 0 , 0 } }, // #34 [ref=2x]
+ { InstDB::RWInfo::kCategoryImul , 22, { 0 , 0 , 0 , 0 , 0 , 0 } }, // #35 [ref=1x]
+ { InstDB::RWInfo::kCategoryGeneric , 5 , { 4 , 9 , 0 , 0 , 0 , 0 } }, // #36 [ref=2x]
+ { InstDB::RWInfo::kCategoryGeneric , 0 , { 4 , 5 , 0 , 0 , 0 , 0 } }, // #37 [ref=1x]
+ { InstDB::RWInfo::kCategoryGeneric , 0 , { 53, 39, 39, 0 , 0 , 0 } }, // #38 [ref=6x]
+ { InstDB::RWInfo::kCategoryGeneric , 0 , { 43, 9 , 9 , 0 , 0 , 0 } }, // #39 [ref=6x]
+ { InstDB::RWInfo::kCategoryGeneric , 0 , { 34, 7 , 7 , 0 , 0 , 0 } }, // #40 [ref=6x]
+ { InstDB::RWInfo::kCategoryGeneric , 0 , { 47, 13, 13, 0 , 0 , 0 } }, // #41 [ref=6x]
+ { InstDB::RWInfo::kCategoryGeneric , 0 , { 53, 39, 0 , 0 , 0 , 0 } }, // #42 [ref=2x]
+ { InstDB::RWInfo::kCategoryGeneric , 0 , { 43, 9 , 0 , 0 , 0 , 0 } }, // #43 [ref=2x]
+ { InstDB::RWInfo::kCategoryGeneric , 0 , { 34, 7 , 0 , 0 , 0 , 0 } }, // #44 [ref=2x]
+ { InstDB::RWInfo::kCategoryGeneric , 0 , { 47, 13, 0 , 0 , 0 , 0 } }, // #45 [ref=2x]
+ { InstDB::RWInfo::kCategoryGeneric , 0 , { 47, 39, 39, 0 , 0 , 0 } }, // #46 [ref=1x]
+ { InstDB::RWInfo::kCategoryGeneric , 0 , { 34, 9 , 9 , 0 , 0 , 0 } }, // #47 [ref=1x]
+ { InstDB::RWInfo::kCategoryGeneric , 0 , { 43, 13, 13, 0 , 0 , 0 } }, // #48 [ref=1x]
+ { InstDB::RWInfo::kCategoryGeneric , 0 , { 54, 0 , 0 , 0 , 0 , 0 } }, // #49 [ref=1x]
+ { InstDB::RWInfo::kCategoryGeneric , 28, { 9 , 0 , 0 , 0 , 0 , 0 } }, // #50 [ref=2x]
+ { InstDB::RWInfo::kCategoryGeneric , 16, { 42, 0 , 0 , 0 , 0 , 0 } }, // #51 [ref=1x]
+ { InstDB::RWInfo::kCategoryGeneric , 7 , { 13, 0 , 0 , 0 , 0 , 0 } }, // #52 [ref=5x]
+ { InstDB::RWInfo::kCategoryGeneric , 0 , { 3 , 0 , 0 , 0 , 0 , 0 } }, // #53 [ref=4x]
+ { InstDB::RWInfo::kCategoryGeneric , 5 , { 3 , 9 , 0 , 0 , 0 , 0 } }, // #54 [ref=2x]
+ { InstDB::RWInfo::kCategoryGeneric , 0 , { 5 , 5 , 20, 0 , 0 , 0 } }, // #55 [ref=2x]
+ { InstDB::RWInfo::kCategoryGeneric , 0 , { 7 , 7 , 20, 0 , 0 , 0 } }, // #56 [ref=1x]
+ { InstDB::RWInfo::kCategoryGeneric , 0 , { 18, 28, 56, 0 , 0 , 0 } }, // #57 [ref=2x]
+ { InstDB::RWInfo::kCategoryGeneric , 6 , { 59, 41, 3 , 0 , 0 , 0 } }, // #58 [ref=1x]
+ { InstDB::RWInfo::kCategoryGeneric , 6 , { 11, 11, 3 , 60, 0 , 0 } }, // #59 [ref=1x]
+ { InstDB::RWInfo::kCategoryGeneric , 0 , { 16, 28, 29, 0 , 0 , 0 } }, // #60 [ref=1x]
+ { InstDB::RWInfo::kCategoryGeneric , 10, { 3 , 0 , 0 , 0 , 0 , 0 } }, // #61 [ref=1x]
+ { InstDB::RWInfo::kCategoryGeneric , 2 , { 2 , 3 , 0 , 0 , 0 , 0 } }, // #62 [ref=1x]
+ { InstDB::RWInfo::kCategoryGeneric , 3 , { 5 , 5 , 0 , 62, 16, 56 } }, // #63 [ref=2x]
+ { InstDB::RWInfo::kCategoryGeneric , 3 , { 5 , 5 , 0 , 63, 16, 56 } }, // #64 [ref=2x]
+ { InstDB::RWInfo::kCategoryGeneric , 3 , { 5 , 5 , 0 , 62, 0 , 0 } }, // #65 [ref=2x]
+ { InstDB::RWInfo::kCategoryGeneric , 3 , { 5 , 5 , 0 , 63, 0 , 0 } }, // #66 [ref=2x]
+ { InstDB::RWInfo::kCategoryGeneric , 31, { 53, 5 , 0 , 0 , 0 , 0 } }, // #67 [ref=2x]
+ { InstDB::RWInfo::kCategoryGeneric , 32, { 34, 5 , 0 , 0 , 0 , 0 } }, // #68 [ref=2x]
+ { InstDB::RWInfo::kCategoryGeneric , 33, { 47, 3 , 0 , 0 , 0 , 0 } }, // #69 [ref=1x]
+ { InstDB::RWInfo::kCategoryGeneric , 15, { 4 , 39, 0 , 0 , 0 , 0 } }, // #70 [ref=1x]
+ { InstDB::RWInfo::kCategoryGeneric , 4 , { 4 , 7 , 0 , 0 , 0 , 0 } }, // #71 [ref=1x]
+ { InstDB::RWInfo::kCategoryGeneric , 27, { 2 , 13, 0 , 0 , 0 , 0 } }, // #72 [ref=1x]
+ { InstDB::RWInfo::kCategoryGeneric , 10, { 65, 0 , 0 , 0 , 0 , 0 } }, // #73 [ref=1x]
+ { InstDB::RWInfo::kCategoryGeneric , 4 , { 34, 7 , 0 , 0 , 0 , 0 } }, // #74 [ref=2x]
+ { InstDB::RWInfo::kCategoryGeneric , 10, { 60, 0 , 0 , 0 , 0 , 0 } }, // #75 [ref=1x]
+ { InstDB::RWInfo::kCategoryGeneric , 0 , { 11, 0 , 0 , 0 , 0 , 0 } }, // #76 [ref=6x]
+ { InstDB::RWInfo::kCategoryGeneric , 0 , { 15, 67, 28, 0 , 0 , 0 } }, // #77 [ref=3x]
+ { InstDB::RWInfo::kCategoryGeneric , 0 , { 28, 15, 67, 0 , 0 , 0 } }, // #78 [ref=1x]
+ { InstDB::RWInfo::kCategoryGeneric , 0 , { 15, 67, 62, 0 , 0 , 0 } }, // #79 [ref=1x]
+ { InstDB::RWInfo::kCategoryGeneric , 2 , { 11, 3 , 0 , 0 , 0 , 0 } }, // #80 [ref=16x]
+ { InstDB::RWInfo::kCategoryGeneric , 4 , { 35, 7 , 0 , 0 , 0 , 0 } }, // #81 [ref=1x]
+ { InstDB::RWInfo::kCategoryGeneric , 5 , { 36, 9 , 0 , 0 , 0 , 0 } }, // #82 [ref=1x]
+ { InstDB::RWInfo::kCategoryGeneric , 0 , { 68, 0 , 0 , 0 , 0 , 0 } }, // #83 [ref=1x]
+ { InstDB::RWInfo::kCategoryGeneric , 31, { 69, 0 , 0 , 0 , 0 , 0 } }, // #84 [ref=30x]
+ { InstDB::RWInfo::kCategoryGeneric , 11, { 2 , 3 , 66, 0 , 0 , 0 } }, // #85 [ref=2x]
+ { InstDB::RWInfo::kCategoryGeneric , 34, { 11, 0 , 0 , 0 , 0 , 0 } }, // #86 [ref=3x]
+ { InstDB::RWInfo::kCategoryGeneric , 28, { 43, 0 , 0 , 0 , 0 , 0 } }, // #87 [ref=2x]
+ { InstDB::RWInfo::kCategoryGeneric , 16, { 70, 0 , 0 , 0 , 0 , 0 } }, // #88 [ref=1x]
+ { InstDB::RWInfo::kCategoryGeneric , 0 , { 71, 42, 42, 0 , 0 , 0 } }, // #89 [ref=5x]
+ { InstDB::RWInfo::kCategoryGeneric , 0 , { 70, 0 , 0 , 0 , 0 , 0 } }, // #90 [ref=1x]
+ { InstDB::RWInfo::kCategoryGeneric , 0 , { 9 , 56, 16, 0 , 0 , 0 } }, // #91 [ref=2x]
+ { InstDB::RWInfo::kCategoryGeneric , 12, { 71, 42, 42, 42, 42, 5 } }, // #92 [ref=2x]
+ { InstDB::RWInfo::kCategoryGeneric , 12, { 4 , 5 , 5 , 5 , 5 , 5 } }, // #93 [ref=2x]
+ { InstDB::RWInfo::kCategoryGeneric , 35, { 10, 5 , 7 , 0 , 0 , 0 } }, // #94 [ref=8x]
+ { InstDB::RWInfo::kCategoryGeneric , 36, { 10, 5 , 9 , 0 , 0 , 0 } }, // #95 [ref=9x]
+ { InstDB::RWInfo::kCategoryGeneric , 6 , { 11, 3 , 3 , 3 , 0 , 0 } }, // #96 [ref=3x]
+ { InstDB::RWInfo::kCategoryGeneric , 35, { 11, 5 , 7 , 0 , 0 , 0 } }, // #97 [ref=1x]
+ { InstDB::RWInfo::kCategoryGeneric , 36, { 11, 5 , 9 , 0 , 0 , 0 } }, // #98 [ref=1x]
+ { InstDB::RWInfo::kCategoryVmov1_2 , 41, { 0 , 0 , 0 , 0 , 0 , 0 } }, // #99 [ref=1x]
+ { InstDB::RWInfo::kCategoryGeneric , 35, { 10, 74, 7 , 0 , 0 , 0 } }, // #100 [ref=1x]
+ { InstDB::RWInfo::kCategoryGeneric , 42, { 10, 57, 3 , 0 , 0 , 0 } }, // #101 [ref=2x]
+ { InstDB::RWInfo::kCategoryGeneric , 42, { 10, 74, 3 , 0 , 0 , 0 } }, // #102 [ref=2x]
+ { InstDB::RWInfo::kCategoryGeneric , 36, { 10, 57, 9 , 0 , 0 , 0 } }, // #103 [ref=1x]
+ { InstDB::RWInfo::kCategoryGeneric , 43, { 10, 5 , 5 , 0 , 0 , 0 } }, // #104 [ref=9x]
+ { InstDB::RWInfo::kCategoryGeneric , 45, { 10, 73, 0 , 0 , 0 , 0 } }, // #105 [ref=2x]
+ { InstDB::RWInfo::kCategoryGeneric , 45, { 10, 3 , 0 , 0 , 0 , 0 } }, // #106 [ref=4x]
+ { InstDB::RWInfo::kCategoryGeneric , 46, { 72, 42, 0 , 0 , 0 , 0 } }, // #107 [ref=4x]
+ { InstDB::RWInfo::kCategoryGeneric , 6 , { 2 , 3 , 3 , 0 , 0 , 0 } }, // #108 [ref=60x]
+ { InstDB::RWInfo::kCategoryGeneric , 35, { 4 , 57, 7 , 0 , 0 , 0 } }, // #109 [ref=1x]
+ { InstDB::RWInfo::kCategoryGeneric , 36, { 4 , 74, 9 , 0 , 0 , 0 } }, // #110 [ref=1x]
+ { InstDB::RWInfo::kCategoryGeneric , 35, { 6 , 7 , 7 , 0 , 0 , 0 } }, // #111 [ref=11x]
+ { InstDB::RWInfo::kCategoryGeneric , 36, { 8 , 9 , 9 , 0 , 0 , 0 } }, // #112 [ref=11x]
+ { InstDB::RWInfo::kCategoryGeneric , 47, { 11, 3 , 3 , 3 , 0 , 0 } }, // #113 [ref=15x]
+ { InstDB::RWInfo::kCategoryGeneric , 48, { 34, 7 , 7 , 7 , 0 , 0 } }, // #114 [ref=4x]
+ { InstDB::RWInfo::kCategoryGeneric , 49, { 43, 9 , 9 , 9 , 0 , 0 } }, // #115 [ref=4x]
+ { InstDB::RWInfo::kCategoryGeneric , 35, { 25, 7 , 7 , 0 , 0 , 0 } }, // #116 [ref=1x]
+ { InstDB::RWInfo::kCategoryGeneric , 36, { 75, 9 , 9 , 0 , 0 , 0 } }, // #117 [ref=1x]
+ { InstDB::RWInfo::kCategoryGeneric , 14, { 34, 3 , 0 , 0 , 0 , 0 } }, // #118 [ref=2x]
+ { InstDB::RWInfo::kCategoryGeneric , 5 , { 34, 9 , 0 , 0 , 0 , 0 } }, // #119 [ref=1x]
+ { InstDB::RWInfo::kCategoryGeneric , 8 , { 2 , 3 , 2 , 0 , 0 , 0 } }, // #120 [ref=2x]
+ { InstDB::RWInfo::kCategoryGeneric , 0 , { 2 , 3 , 2 , 0 , 0 , 0 } }, // #121 [ref=4x]
+ { InstDB::RWInfo::kCategoryGeneric , 18, { 4 , 3 , 4 , 0 , 0 , 0 } }, // #122 [ref=2x]
+ { InstDB::RWInfo::kCategoryGeneric , 35, { 10, 57, 7 , 0 , 0 , 0 } }, // #123 [ref=11x]
+ { InstDB::RWInfo::kCategoryGeneric , 36, { 10, 74, 9 , 0 , 0 , 0 } }, // #124 [ref=13x]
+ { InstDB::RWInfo::kCategoryGeneric , 43, { 72, 73, 5 , 0 , 0 , 0 } }, // #125 [ref=2x]
+ { InstDB::RWInfo::kCategoryGeneric , 43, { 11, 3 , 5 , 0 , 0 , 0 } }, // #126 [ref=4x]
+ { InstDB::RWInfo::kCategoryGeneric , 50, { 70, 42, 73, 0 , 0 , 0 } }, // #127 [ref=4x]
+ { InstDB::RWInfo::kCategoryVmaskmov , 0 , { 0 , 0 , 0 , 0 , 0 , 0 } }, // #128 [ref=4x]
+ { InstDB::RWInfo::kCategoryGeneric , 13, { 34, 0 , 0 , 0 , 0 , 0 } }, // #129 [ref=2x]
+ { InstDB::RWInfo::kCategoryGeneric , 0 , { 21, 0 , 0 , 0 , 0 , 0 } }, // #130 [ref=2x]
+ { InstDB::RWInfo::kCategoryGeneric , 0 , { 10, 57, 57, 0 , 0 , 0 } }, // #131 [ref=1x]
+ { InstDB::RWInfo::kCategoryGeneric , 13, { 10, 7 , 7 , 0 , 0 , 0 } }, // #132 [ref=2x]
+ { InstDB::RWInfo::kCategoryGeneric , 0 , { 10, 7 , 7 , 0 , 0 , 0 } }, // #133 [ref=1x]
+ { InstDB::RWInfo::kCategoryGeneric , 13, { 10, 57, 7 , 0 , 0 , 0 } }, // #134 [ref=2x]
+ { InstDB::RWInfo::kCategoryGeneric , 0 , { 10, 57, 7 , 0 , 0 , 0 } }, // #135 [ref=1x]
+ { InstDB::RWInfo::kCategoryGeneric , 0 , { 10, 74, 9 , 0 , 0 , 0 } }, // #136 [ref=1x]
+ { InstDB::RWInfo::kCategoryGeneric , 13, { 7 , 0 , 0 , 0 , 0 , 0 } }, // #137 [ref=2x]
+ { InstDB::RWInfo::kCategoryGeneric , 0 , { 76, 0 , 0 , 0 , 0 , 0 } }, // #138 [ref=1x]
+ { InstDB::RWInfo::kCategoryGeneric , 54, { 34, 11, 3 , 3 , 0 , 0 } }, // #139 [ref=2x]
+ { InstDB::RWInfo::kCategoryGeneric , 12, { 70, 42, 42, 42, 42, 5 } }, // #140 [ref=2x]
+ { InstDB::RWInfo::kCategoryGeneric , 6 , { 34, 3 , 3 , 0 , 0 , 0 } }, // #141 [ref=17x]
+ { InstDB::RWInfo::kCategoryGeneric , 50, { 72, 73, 73, 0 , 0 , 0 } }, // #142 [ref=2x]
+ { InstDB::RWInfo::kCategoryGeneric , 22, { 11, 3 , 3 , 0 , 0 , 0 } }, // #143 [ref=4x]
+ { InstDB::RWInfo::kCategoryGeneric , 7 , { 47, 5 , 0 , 0 , 0 , 0 } }, // #144 [ref=1x]
+ { InstDB::RWInfo::kCategoryGeneric , 55, { 10, 5 , 39, 0 , 0 , 0 } }, // #145 [ref=1x]
+ { InstDB::RWInfo::kCategoryGeneric , 56, { 10, 5 , 13, 0 , 0 , 0 } }, // #146 [ref=1x]
+ { InstDB::RWInfo::kCategoryGeneric , 43, { 10, 5 , 5 , 5 , 0 , 0 } }, // #147 [ref=12x]
+ { InstDB::RWInfo::kCategoryGeneric , 61, { 10, 5 , 5 , 5 , 0 , 0 } }, // #148 [ref=1x]
+ { InstDB::RWInfo::kCategoryGeneric , 62, { 10, 5 , 5 , 0 , 0 , 0 } }, // #149 [ref=12x]
+ { InstDB::RWInfo::kCategoryGeneric , 22, { 11, 3 , 5 , 0 , 0 , 0 } }, // #150 [ref=9x]
+ { InstDB::RWInfo::kCategoryGeneric , 63, { 11, 3 , 0 , 0 , 0 , 0 } }, // #151 [ref=2x]
+ { InstDB::RWInfo::kCategoryGeneric , 0 , { 56, 16, 28, 0 , 0 , 0 } }, // #152 [ref=2x]
+ { InstDB::RWInfo::kCategoryGeneric , 8 , { 3 , 56, 16, 0 , 0 , 0 } }, // #153 [ref=4x]
+ { InstDB::RWInfo::kCategoryGeneric , 8 , { 11, 56, 16, 0 , 0 , 0 } } // #154 [ref=8x]
};
const InstDB::RWInfoOp InstDB::rwInfoOp[] = {
- { 0x0000000000000000u, 0x0000000000000000u, 0xFF, { 0 }, 0 }, // #0 [ref=14957x]
+ { 0x0000000000000000u, 0x0000000000000000u, 0xFF, { 0 }, 0 }, // #0 [ref=15239x]
{ 0x0000000000000003u, 0x0000000000000003u, 0x00, { 0 }, OpRWInfo::kRW | OpRWInfo::kRegPhysId }, // #1 [ref=10x]
{ 0x0000000000000000u, 0x0000000000000000u, 0xFF, { 0 }, OpRWInfo::kRW | OpRWInfo::kZExt }, // #2 [ref=217x]
- { 0x0000000000000000u, 0x0000000000000000u, 0xFF, { 0 }, OpRWInfo::kRead }, // #3 [ref=979x]
+ { 0x0000000000000000u, 0x0000000000000000u, 0xFF, { 0 }, OpRWInfo::kRead }, // #3 [ref=986x]
{ 0x000000000000FFFFu, 0x000000000000FFFFu, 0xFF, { 0 }, OpRWInfo::kRW | OpRWInfo::kZExt }, // #4 [ref=92x]
{ 0x000000000000FFFFu, 0x0000000000000000u, 0xFF, { 0 }, OpRWInfo::kRead }, // #5 [ref=305x]
{ 0x00000000000000FFu, 0x00000000000000FFu, 0xFF, { 0 }, OpRWInfo::kRW }, // #6 [ref=18x]
{ 0x00000000000000FFu, 0x0000000000000000u, 0xFF, { 0 }, OpRWInfo::kRead }, // #7 [ref=181x]
{ 0x000000000000000Fu, 0x000000000000000Fu, 0xFF, { 0 }, OpRWInfo::kRW }, // #8 [ref=18x]
- { 0x000000000000000Fu, 0x0000000000000000u, 0xFF, { 0 }, OpRWInfo::kRead }, // #9 [ref=129x]
+ { 0x000000000000000Fu, 0x0000000000000000u, 0xFF, { 0 }, OpRWInfo::kRead }, // #9 [ref=131x]
{ 0x0000000000000000u, 0x000000000000FFFFu, 0xFF, { 0 }, OpRWInfo::kWrite | OpRWInfo::kZExt }, // #10 [ref=160x]
- { 0x0000000000000000u, 0x0000000000000000u, 0xFF, { 0 }, OpRWInfo::kWrite | OpRWInfo::kZExt }, // #11 [ref=416x]
+ { 0x0000000000000000u, 0x0000000000000000u, 0xFF, { 0 }, OpRWInfo::kWrite | OpRWInfo::kZExt }, // #11 [ref=421x]
{ 0x0000000000000003u, 0x0000000000000003u, 0xFF, { 0 }, OpRWInfo::kRW }, // #12 [ref=1x]
{ 0x0000000000000003u, 0x0000000000000000u, 0xFF, { 0 }, OpRWInfo::kRead }, // #13 [ref=34x]
{ 0x000000000000FFFFu, 0x0000000000000000u, 0x00, { 0 }, OpRWInfo::kRead | OpRWInfo::kRegPhysId }, // #14 [ref=4x]
- { 0x0000000000000000u, 0x000000000000000Fu, 0x02, { 0 }, OpRWInfo::kWrite | OpRWInfo::kZExt | OpRWInfo::kRegPhysId }, // #15 [ref=7x]
- { 0x000000000000000Fu, 0x0000000000000000u, 0x00, { 0 }, OpRWInfo::kRead | OpRWInfo::kRegPhysId }, // #16 [ref=21x]
+ { 0x0000000000000000u, 0x000000000000000Fu, 0x02, { 0 }, OpRWInfo::kWrite | OpRWInfo::kZExt | OpRWInfo::kRegPhysId }, // #15 [ref=8x]
+ { 0x000000000000000Fu, 0x0000000000000000u, 0x00, { 0 }, OpRWInfo::kRead | OpRWInfo::kRegPhysId }, // #16 [ref=23x]
{ 0x00000000000000FFu, 0x00000000000000FFu, 0x00, { 0 }, OpRWInfo::kRW | OpRWInfo::kZExt | OpRWInfo::kRegPhysId }, // #17 [ref=2x]
{ 0x0000000000000000u, 0x0000000000000000u, 0x00, { 0 }, OpRWInfo::kRead | OpRWInfo::kMemPhysId }, // #18 [ref=3x]
{ 0x0000000000000000u, 0x0000000000000000u, 0x06, { 0 }, OpRWInfo::kRW | OpRWInfo::kZExt | OpRWInfo::kMemPhysId }, // #19 [ref=3x]
@@ -3833,13 +3936,13 @@ const InstDB::RWInfoOp InstDB::rwInfoOp[] = {
{ 0x00000000000000FFu, 0x00000000000000FFu, 0xFF, { 0 }, OpRWInfo::kRW | OpRWInfo::kZExt }, // #25 [ref=20x]
{ 0x000000000000000Fu, 0x000000000000000Fu, 0x02, { 0 }, OpRWInfo::kRW | OpRWInfo::kZExt | OpRWInfo::kRegPhysId }, // #26 [ref=1x]
{ 0x000000000000000Fu, 0x000000000000000Fu, 0x00, { 0 }, OpRWInfo::kRW | OpRWInfo::kZExt | OpRWInfo::kRegPhysId }, // #27 [ref=4x]
- { 0x000000000000000Fu, 0x0000000000000000u, 0x01, { 0 }, OpRWInfo::kRead | OpRWInfo::kRegPhysId }, // #28 [ref=11x]
+ { 0x000000000000000Fu, 0x0000000000000000u, 0x01, { 0 }, OpRWInfo::kRead | OpRWInfo::kRegPhysId }, // #28 [ref=12x]
{ 0x000000000000000Fu, 0x0000000000000000u, 0x03, { 0 }, OpRWInfo::kRead | OpRWInfo::kRegPhysId }, // #29 [ref=2x]
{ 0x0000000000000000u, 0x000000000000000Fu, 0x03, { 0 }, OpRWInfo::kWrite | OpRWInfo::kZExt | OpRWInfo::kRegPhysId }, // #30 [ref=1x]
{ 0x000000000000000Fu, 0x000000000000000Fu, 0x01, { 0 }, OpRWInfo::kRW | OpRWInfo::kZExt | OpRWInfo::kRegPhysId }, // #31 [ref=1x]
{ 0x0000000000000000u, 0x00000000000000FFu, 0x02, { 0 }, OpRWInfo::kWrite | OpRWInfo::kZExt | OpRWInfo::kRegPhysId }, // #32 [ref=1x]
{ 0x00000000000000FFu, 0x0000000000000000u, 0x00, { 0 }, OpRWInfo::kRead | OpRWInfo::kRegPhysId }, // #33 [ref=1x]
- { 0x0000000000000000u, 0x00000000000000FFu, 0xFF, { 0 }, OpRWInfo::kWrite | OpRWInfo::kZExt }, // #34 [ref=75x]
+ { 0x0000000000000000u, 0x00000000000000FFu, 0xFF, { 0 }, OpRWInfo::kWrite | OpRWInfo::kZExt }, // #34 [ref=77x]
{ 0x0000000000000000u, 0x00000000000000FFu, 0xFF, { 0 }, OpRWInfo::kWrite }, // #35 [ref=6x]
{ 0x0000000000000000u, 0x000000000000000Fu, 0xFF, { 0 }, OpRWInfo::kWrite }, // #36 [ref=6x]
{ 0x0000000000000000u, 0x0000000000000003u, 0x02, { 0 }, OpRWInfo::kWrite | OpRWInfo::kRegPhysId }, // #37 [ref=1x]
@@ -3847,8 +3950,8 @@ const InstDB::RWInfoOp InstDB::rwInfoOp[] = {
{ 0x0000000000000001u, 0x0000000000000000u, 0xFF, { 0 }, OpRWInfo::kRead }, // #39 [ref=28x]
{ 0x0000000000000000u, 0x0000000000000000u, 0x02, { 0 }, OpRWInfo::kRW | OpRWInfo::kRegPhysId | OpRWInfo::kZExt }, // #40 [ref=2x]
{ 0x0000000000000000u, 0x0000000000000000u, 0x00, { 0 }, OpRWInfo::kRW | OpRWInfo::kRegPhysId | OpRWInfo::kZExt }, // #41 [ref=3x]
- { 0x0000000000000000u, 0x000000000000000Fu, 0xFF, { 0 }, OpRWInfo::kWrite | OpRWInfo::kZExt }, // #42 [ref=29x]
- { 0xFFFFFFFFFFFFFFFFu, 0x0000000000000000u, 0xFF, { 0 }, OpRWInfo::kRead }, // #43 [ref=33x]
+ { 0xFFFFFFFFFFFFFFFFu, 0x0000000000000000u, 0xFF, { 0 }, OpRWInfo::kRead }, // #42 [ref=45x]
+ { 0x0000000000000000u, 0x000000000000000Fu, 0xFF, { 0 }, OpRWInfo::kWrite | OpRWInfo::kZExt }, // #43 [ref=27x]
{ 0x00000000000003FFu, 0x00000000000003FFu, 0xFF, { 0 }, OpRWInfo::kRW | OpRWInfo::kZExt }, // #44 [ref=22x]
{ 0x00000000000003FFu, 0x0000000000000000u, 0xFF, { 0 }, OpRWInfo::kRead }, // #45 [ref=13x]
{ 0x0000000000000000u, 0x00000000000003FFu, 0xFF, { 0 }, OpRWInfo::kWrite | OpRWInfo::kZExt }, // #46 [ref=1x]
@@ -3861,7 +3964,7 @@ const InstDB::RWInfoOp InstDB::rwInfoOp[] = {
{ 0x0000000000000000u, 0x0000000000000001u, 0xFF, { 0 }, OpRWInfo::kWrite | OpRWInfo::kZExt }, // #53 [ref=14x]
{ 0x0000000000000000u, 0x0000000000000001u, 0x00, { 0 }, OpRWInfo::kWrite | OpRWInfo::kRegPhysId }, // #54 [ref=1x]
{ 0x0000000000000000u, 0x0000000000000000u, 0x01, { 0 }, OpRWInfo::kRW | OpRWInfo::kRegPhysId | OpRWInfo::kZExt }, // #55 [ref=3x]
- { 0x000000000000000Fu, 0x0000000000000000u, 0x02, { 0 }, OpRWInfo::kRead | OpRWInfo::kRegPhysId }, // #56 [ref=20x]
+ { 0x000000000000000Fu, 0x0000000000000000u, 0x02, { 0 }, OpRWInfo::kRead | OpRWInfo::kRegPhysId }, // #56 [ref=22x]
{ 0x000000000000FF00u, 0x0000000000000000u, 0xFF, { 0 }, OpRWInfo::kRead }, // #57 [ref=23x]
{ 0x0000000000000000u, 0x000000000000FF00u, 0xFF, { 0 }, OpRWInfo::kWrite }, // #58 [ref=1x]
{ 0x0000000000000000u, 0x0000000000000000u, 0x02, { 0 }, OpRWInfo::kWrite | OpRWInfo::kRegPhysId | OpRWInfo::kZExt }, // #59 [ref=1x]
@@ -3872,12 +3975,12 @@ const InstDB::RWInfoOp InstDB::rwInfoOp[] = {
{ 0x0000000000000000u, 0x0000000000000007u, 0xFF, { 0 }, OpRWInfo::kWrite | OpRWInfo::kZExt }, // #64 [ref=2x]
{ 0x0000000000000000u, 0x0000000000000000u, 0x04, { 0 }, OpRWInfo::kWrite | OpRWInfo::kZExt | OpRWInfo::kRegPhysId }, // #65 [ref=1x]
{ 0x0000000000000001u, 0x0000000000000000u, 0x01, { 0 }, OpRWInfo::kRead | OpRWInfo::kRegPhysId }, // #66 [ref=10x]
- { 0x0000000000000000u, 0x000000000000000Fu, 0x00, { 0 }, OpRWInfo::kWrite | OpRWInfo::kZExt | OpRWInfo::kRegPhysId }, // #67 [ref=5x]
+ { 0x0000000000000000u, 0x000000000000000Fu, 0x00, { 0 }, OpRWInfo::kWrite | OpRWInfo::kZExt | OpRWInfo::kRegPhysId }, // #67 [ref=6x]
{ 0x0000000000000001u, 0x0000000000000000u, 0x00, { 0 }, OpRWInfo::kRead | OpRWInfo::kRegPhysId }, // #68 [ref=1x]
{ 0x0000000000000000u, 0x0000000000000001u, 0xFF, { 0 }, OpRWInfo::kWrite }, // #69 [ref=30x]
- { 0xFFFFFFFFFFFFFFFFu, 0xFFFFFFFFFFFFFFFFu, 0xFF, { 0 }, OpRWInfo::kRW | OpRWInfo::kZExt }, // #70 [ref=2x]
- { 0x0000000000000000u, 0x00000000FFFFFFFFu, 0xFF, { 0 }, OpRWInfo::kWrite | OpRWInfo::kZExt }, // #71 [ref=10x]
- { 0x0000000000000000u, 0xFFFFFFFFFFFFFFFFu, 0xFF, { 0 }, OpRWInfo::kWrite | OpRWInfo::kZExt }, // #72 [ref=16x]
+ { 0x0000000000000000u, 0xFFFFFFFFFFFFFFFFu, 0xFF, { 0 }, OpRWInfo::kWrite | OpRWInfo::kZExt }, // #70 [ref=20x]
+ { 0xFFFFFFFFFFFFFFFFu, 0xFFFFFFFFFFFFFFFFu, 0xFF, { 0 }, OpRWInfo::kRW | OpRWInfo::kZExt }, // #71 [ref=7x]
+ { 0x0000000000000000u, 0x00000000FFFFFFFFu, 0xFF, { 0 }, OpRWInfo::kWrite | OpRWInfo::kZExt }, // #72 [ref=10x]
{ 0x00000000FFFFFFFFu, 0x0000000000000000u, 0xFF, { 0 }, OpRWInfo::kRead }, // #73 [ref=16x]
{ 0x000000000000FFF0u, 0x0000000000000000u, 0xFF, { 0 }, OpRWInfo::kRead }, // #74 [ref=18x]
{ 0x000000000000000Fu, 0x000000000000000Fu, 0xFF, { 0 }, OpRWInfo::kRW | OpRWInfo::kZExt }, // #75 [ref=1x]
@@ -3885,7 +3988,7 @@ const InstDB::RWInfoOp InstDB::rwInfoOp[] = {
};
const InstDB::RWInfoRm InstDB::rwInfoRm[] = {
- { InstDB::RWInfoRm::kCategoryNone , 0x00, 0 , 0, 0 }, // #0 [ref=1809x]
+ { InstDB::RWInfoRm::kCategoryNone , 0x00, 0 , 0, 0 }, // #0 [ref=1856x]
{ InstDB::RWInfoRm::kCategoryConsistent, 0x03, 0 , InstDB::RWInfoRm::kFlagAmbiguous, 0 }, // #1 [ref=8x]
{ InstDB::RWInfoRm::kCategoryConsistent, 0x02, 0 , 0, 0 }, // #2 [ref=194x]
{ InstDB::RWInfoRm::kCategoryFixed , 0x02, 16, 0, 0 }, // #3 [ref=122x]
@@ -3893,7 +3996,7 @@ const InstDB::RWInfoRm InstDB::rwInfoRm[] = {
{ InstDB::RWInfoRm::kCategoryFixed , 0x02, 4 , 0, 0 }, // #5 [ref=33x]
{ InstDB::RWInfoRm::kCategoryConsistent, 0x04, 0 , 0, 0 }, // #6 [ref=270x]
{ InstDB::RWInfoRm::kCategoryFixed , 0x01, 2 , 0, 0 }, // #7 [ref=9x]
- { InstDB::RWInfoRm::kCategoryFixed , 0x00, 0 , 0, 0 }, // #8 [ref=60x]
+ { InstDB::RWInfoRm::kCategoryFixed , 0x00, 0 , 0, 0 }, // #8 [ref=63x]
{ InstDB::RWInfoRm::kCategoryFixed , 0x03, 0 , 0, 0 }, // #9 [ref=1x]
{ InstDB::RWInfoRm::kCategoryConsistent, 0x01, 0 , InstDB::RWInfoRm::kFlagAmbiguous, 0 }, // #10 [ref=20x]
{ InstDB::RWInfoRm::kCategoryConsistent, 0x01, 0 , 0, 0 }, // #11 [ref=13x]
@@ -3901,7 +4004,7 @@ const InstDB::RWInfoRm InstDB::rwInfoRm[] = {
{ InstDB::RWInfoRm::kCategoryFixed , 0x00, 8 , 0, 0 }, // #13 [ref=20x]
{ InstDB::RWInfoRm::kCategoryConsistent, 0x02, 0 , InstDB::RWInfoRm::kFlagAmbiguous, 0 }, // #14 [ref=15x]
{ InstDB::RWInfoRm::kCategoryFixed , 0x02, 1 , 0, 0 }, // #15 [ref=5x]
- { InstDB::RWInfoRm::kCategoryFixed , 0x00, 64, 0, 0 }, // #16 [ref=3x]
+ { InstDB::RWInfoRm::kCategoryFixed , 0x00, 64, 0, 0 }, // #16 [ref=5x]
{ InstDB::RWInfoRm::kCategoryFixed , 0x01, 4 , 0, 0 }, // #17 [ref=4x]
{ InstDB::RWInfoRm::kCategoryNone , 0x00, 0 , InstDB::RWInfoRm::kFlagAmbiguous, 0 }, // #18 [ref=22x]
{ InstDB::RWInfoRm::kCategoryFixed , 0x00, 10, 0, 0 }, // #19 [ref=2x]
@@ -3939,15 +4042,16 @@ const InstDB::RWInfoRm InstDB::rwInfoRm[] = {
{ InstDB::RWInfoRm::kCategoryConsistent, 0x03, 0 , 0, 0 }, // #51 [ref=13x]
{ InstDB::RWInfoRm::kCategoryNone , 0x02, 0 , 0, 0 }, // #52 [ref=1x]
{ InstDB::RWInfoRm::kCategoryFixed , 0x03, 8 , InstDB::RWInfoRm::kFlagAmbiguous, 0 }, // #53 [ref=1x]
- { InstDB::RWInfoRm::kCategoryFixed , 0x04, 1 , 0, 0 }, // #54 [ref=1x]
- { InstDB::RWInfoRm::kCategoryFixed , 0x04, 2 , 0, 0 }, // #55 [ref=1x]
- { InstDB::RWInfoRm::kCategoryQuarter , 0x01, 0 , 0, 0 }, // #56 [ref=6x]
- { InstDB::RWInfoRm::kCategoryEighth , 0x01, 0 , 0, 0 }, // #57 [ref=3x]
- { InstDB::RWInfoRm::kCategoryQuarter , 0x02, 0 , 0, 0 }, // #58 [ref=4x]
- { InstDB::RWInfoRm::kCategoryEighth , 0x02, 0 , 0, 0 }, // #59 [ref=2x]
- { InstDB::RWInfoRm::kCategoryFixed , 0x0C, 16, 0, 0 }, // #60 [ref=1x]
- { InstDB::RWInfoRm::kCategoryFixed , 0x06, 16, 0, 0 }, // #61 [ref=12x]
- { InstDB::RWInfoRm::kCategoryConsistent, 0x02, 0 , 0, Features::kAVX512_BW } // #62 [ref=2x]
+ { InstDB::RWInfoRm::kCategoryConsistent, 0x08, 0 , 0, 0 }, // #54 [ref=2x]
+ { InstDB::RWInfoRm::kCategoryFixed , 0x04, 1 , 0, 0 }, // #55 [ref=1x]
+ { InstDB::RWInfoRm::kCategoryFixed , 0x04, 2 , 0, 0 }, // #56 [ref=1x]
+ { InstDB::RWInfoRm::kCategoryQuarter , 0x01, 0 , 0, 0 }, // #57 [ref=6x]
+ { InstDB::RWInfoRm::kCategoryEighth , 0x01, 0 , 0, 0 }, // #58 [ref=3x]
+ { InstDB::RWInfoRm::kCategoryQuarter , 0x02, 0 , 0, 0 }, // #59 [ref=4x]
+ { InstDB::RWInfoRm::kCategoryEighth , 0x02, 0 , 0, 0 }, // #60 [ref=2x]
+ { InstDB::RWInfoRm::kCategoryFixed , 0x0C, 16, 0, 0 }, // #61 [ref=1x]
+ { InstDB::RWInfoRm::kCategoryFixed , 0x06, 16, 0, 0 }, // #62 [ref=12x]
+ { InstDB::RWInfoRm::kCategoryConsistent, 0x02, 0 , 0, Features::kAVX512_BW } // #63 [ref=2x]
};
// ----------------------------------------------------------------------------
// ${InstRWInfoTable:End}
diff --git a/src/asmjit/x86/x86instdb.h b/src/asmjit/x86/x86instdb.h
index 6bc2af5..f02c3e8 100644
--- a/src/asmjit/x86/x86instdb.h
+++ b/src/asmjit/x86/x86instdb.h
@@ -74,17 +74,18 @@ enum OpFlags : uint32_t {
kOpDReg = 0x00001000u, //!< Operand can be DReg (debug register).
kOpSt = 0x00002000u, //!< Operand can be 80-bit ST register (X87).
kOpBnd = 0x00004000u, //!< Operand can be 128-bit BND register.
- kOpAllRegs = 0x00007FFFu, //!< Combination of all possible registers.
-
- kOpI4 = 0x00010000u, //!< Operand can be unsigned 4-bit immediate.
- kOpU4 = 0x00020000u, //!< Operand can be unsigned 4-bit immediate.
- kOpI8 = 0x00040000u, //!< Operand can be signed 8-bit immediate.
- kOpU8 = 0x00080000u, //!< Operand can be unsigned 8-bit immediate.
- kOpI16 = 0x00100000u, //!< Operand can be signed 16-bit immediate.
+ kOpTmm = 0x00008000u, //!< Operand can be 0..8192-bit TMM register.
+ kOpAllRegs = 0x0000FFFFu, //!< Combination of all possible registers.
+
+ kOpI4 = 0x00010000u, //!< Operand can be unsigned 4-bit immediate.
+ kOpU4 = 0x00020000u, //!< Operand can be unsigned 4-bit immediate.
+ kOpI8 = 0x00040000u, //!< Operand can be signed 8-bit immediate.
+ kOpU8 = 0x00080000u, //!< Operand can be unsigned 8-bit immediate.
+ kOpI16 = 0x00100000u, //!< Operand can be signed 16-bit immediate.
kOpU16 = 0x00200000u, //!< Operand can be unsigned 16-bit immediate.
- kOpI32 = 0x00400000u, //!< Operand can be signed 32-bit immediate.
+ kOpI32 = 0x00400000u, //!< Operand can be signed 32-bit immediate.
kOpU32 = 0x00800000u, //!< Operand can be unsigned 32-bit immediate.
- kOpI64 = 0x01000000u, //!< Operand can be signed 64-bit immediate.
+ kOpI64 = 0x01000000u, //!< Operand can be signed 64-bit immediate.
kOpU64 = 0x02000000u, //!< Operand can be unsigned 64-bit immediate.
kOpAllImm = 0x03FF0000u, //!< Operand can be any immediate.
@@ -129,7 +130,8 @@ enum MemFlags : uint32_t {
kMemOpDs = 0x1000u, //!< Implicit memory operand's DS segment.
kMemOpEs = 0x2000u, //!< Implicit memory operand's ES segment.
- kMemOpMib = 0x4000u //!< Operand must be MIB (base+index) pointer.
+ kMemOpMib = 0x4000u, //!< Operand must be MIB (base+index) pointer.
+ kMemOpTMem = 0x8000u //!< Operand is a sib_mem (ADX memory operand).
};
// ============================================================================
@@ -156,6 +158,7 @@ enum Flags : uint32_t {
//
// These describe optional X86 prefixes that can be used to change the instruction's operation.
+ kFlagTsib = 0x00000800u, //!< Instruction uses TSIB (or SIB_MEM) encoding (MODRM followed by SIB).
kFlagRep = 0x00001000u, //!< Instruction can be prefixed with using the REP(REPE) or REPNE prefix.
kFlagRepIgnored = 0x00002000u, //!< Instruction ignores REP|REPNE prefixes, but they are accepted.
kFlagLock = 0x00004000u, //!< Instruction can be prefixed with using the LOCK prefix.
@@ -319,6 +322,8 @@ struct CommonInfo {
inline bool isMibOp() const noexcept { return hasFlag(kFlagMib); }
//! Tests whether the instruction uses VSIB.
inline bool isVsibOp() const noexcept { return hasFlag(kFlagVsib); }
+ //! Tests whether the instruction uses TSIB (AMX, instruction requires MOD+SIB).
+ inline bool isTsibOp() const noexcept { return hasFlag(kFlagTsib); }
//! Tests whether the instruction uses VEX (can be set together with EVEX if both are encodable).
inline bool isVex() const noexcept { return hasFlag(kFlagVex); }
//! Tests whether the instruction uses EVEX (can be set together with VEX if both are encodable).
diff --git a/src/asmjit/x86/x86instdb_p.h b/src/asmjit/x86/x86instdb_p.h
index b8ec1db..afeabd2 100644
--- a/src/asmjit/x86/x86instdb_p.h
+++ b/src/asmjit/x86/x86instdb_p.h
@@ -62,6 +62,8 @@ enum EncodingId : uint32_t {
kEncodingX86M_Only, //!< X86 [M] (restricted to memory operand of any size).
kEncodingX86M_Nop, //!< X86 [M] (special case of NOP instruction).
kEncodingX86R_Native, //!< X86 [R] (register must be either 32-bit or 64-bit depending on arch).
+ kEncodingX86R_FromM, //!< X86 [R] - which specifies memory address.
+ kEncodingX86R32_EDX_EAX, //!< X86 [R32] followed by implicit EDX and EAX.
kEncodingX86Rm, //!< X86 [RM] (doesn't handle single-byte size).
kEncodingX86Rm_Raw66H, //!< X86 [RM] (used by LZCNT, POPCNT, and TZCNT).
kEncodingX86Rm_NoSize, //!< X86 [RM] (doesn't add REX.W prefix if 64-bit reg is used).
@@ -132,6 +134,7 @@ enum EncodingId : uint32_t {
kEncodingExtInsertq, //!< EXT insrq (SSE4A).
kEncodingExt3dNow, //!< EXT [RMI] (3DNOW specific).
kEncodingVexOp, //!< VEX [OP].
+ kEncodingVexOpMod, //!< VEX [OP] with MODR/M.
kEncodingVexKmov, //!< VEX [RM|MR] (used by kmov[b|w|d|q]).
kEncodingVexR_Wx, //!< VEX|EVEX [R] (propagatex VEX.W if GPQ used).
kEncodingVexM, //!< VEX|EVEX [M].
@@ -154,6 +157,7 @@ enum EncodingId : uint32_t {
kEncodingVexRvm_Wx, //!< VEX|EVEX [RVM] (propagates VEX|EVEX.W if GPQ used).
kEncodingVexRvm_ZDX_Wx, //!< VEX|EVEX [RVM<ZDX>] (propagates VEX|EVEX.W if GPQ used).
kEncodingVexRvm_Lx, //!< VEX|EVEX [RVM] (propagates VEX|EVEX.L if YMM used).
+ kEncodingVexRvm_Lx_2xK, //!< VEX|EVEX [RVM] (vp2intersectd/vp2intersectq).
kEncodingVexRvmr, //!< VEX|EVEX [RVMR].
kEncodingVexRvmr_Lx, //!< VEX|EVEX [RVMR] (propagates VEX|EVEX.L if YMM used).
kEncodingVexRvmi, //!< VEX|EVEX [RVMI].
@@ -187,6 +191,11 @@ enum EncodingId : uint32_t {
kEncodingVexMovssMovsd, //!< VEX|EVEX vmovss, vmovsd.
kEncodingFma4, //!< FMA4 [R, R, R/M, R/M].
kEncodingFma4_Lx, //!< FMA4 [R, R, R/M, R/M] (propagates AVX.L if YMM used).
+ kEncodingAmxCfg, //!< AMX ldtilecfg/sttilecfg.
+ kEncodingAmxR, //!< AMX [R] - tilezero.
+ kEncodingAmxRm, //!< AMX tileloadd/tileloaddt1.
+ kEncodingAmxMr, //!< AMX tilestored.
+ kEncodingAmxRmv, //!< AMX instructions that use TMM registers.
kEncodingCount //!< Count of instruction encodings.
};
@@ -288,8 +297,10 @@ struct RWFlagsInfoTable {
uint32_t writeFlags;
};
-extern const uint8_t rwInfoIndex[Inst::_kIdCount * 2];
-extern const RWInfo rwInfo[];
+extern const uint8_t rwInfoIndexA[Inst::_kIdCount];
+extern const uint8_t rwInfoIndexB[Inst::_kIdCount];
+extern const RWInfo rwInfoA[];
+extern const RWInfo rwInfoB[];
extern const RWInfoOp rwInfoOp[];
extern const RWInfoRm rwInfoRm[];
extern const RWFlagsInfoTable _rwFlagsInfoTable[];
diff --git a/src/asmjit/x86/x86opcode_p.h b/src/asmjit/x86/x86opcode_p.h
index 164b26c..a8ccc93 100644
--- a/src/asmjit/x86/x86opcode_p.h
+++ b/src/asmjit/x86/x86opcode_p.h
@@ -337,14 +337,17 @@ struct Opcode {
k000F3A = kPP_00 | kMM_0F3A, // '0F3A'
k660000 = kPP_66 | kMM_00, // '66'
k660F00 = kPP_66 | kMM_0F, // '660F'
+ k660F01 = kPP_66 | kMM_0F01, // '660F01'
k660F38 = kPP_66 | kMM_0F38, // '660F38'
k660F3A = kPP_66 | kMM_0F3A, // '660F3A'
kF20000 = kPP_F2 | kMM_00, // 'F2'
kF20F00 = kPP_F2 | kMM_0F, // 'F20F'
+ kF20F01 = kPP_F2 | kMM_0F01, // 'F20F01'
kF20F38 = kPP_F2 | kMM_0F38, // 'F20F38'
kF20F3A = kPP_F2 | kMM_0F3A, // 'F20F3A'
kF30000 = kPP_F3 | kMM_00, // 'F3'
kF30F00 = kPP_F3 | kMM_0F, // 'F30F'
+ kF30F01 = kPP_F3 | kMM_0F01, // 'F30F01'
kF30F38 = kPP_F3 | kMM_0F38, // 'F30F38'
kF30F3A = kPP_F3 | kMM_0F3A, // 'F30F3A'
kFPU_00 = kPP_00 | kMM_00, // '__' (FPU)
diff --git a/src/asmjit/x86/x86operand.h b/src/asmjit/x86/x86operand.h
index ccbe87e..da988ce 100644
--- a/src/asmjit/x86/x86operand.h
+++ b/src/asmjit/x86/x86operand.h
@@ -108,6 +108,7 @@ class CReg;
class DReg;
class St;
class Bnd;
+class Tmm;
class Rip;
// ============================================================================
@@ -142,7 +143,8 @@ ASMJIT_DEFINE_REG_TRAITS(CReg , BaseReg::kTypeCustom + 1, BaseReg::kGroupVirt +
ASMJIT_DEFINE_REG_TRAITS(DReg , BaseReg::kTypeCustom + 2, BaseReg::kGroupVirt + 2, 0 , 16, Type::kIdVoid );
ASMJIT_DEFINE_REG_TRAITS(St , BaseReg::kTypeCustom + 3, BaseReg::kGroupVirt + 3, 10, 8 , Type::kIdF80 );
ASMJIT_DEFINE_REG_TRAITS(Bnd , BaseReg::kTypeCustom + 4, BaseReg::kGroupVirt + 4, 16, 4 , Type::kIdVoid );
-ASMJIT_DEFINE_REG_TRAITS(Rip , BaseReg::kTypeIP , BaseReg::kGroupVirt + 5, 0 , 1 , Type::kIdVoid );
+ASMJIT_DEFINE_REG_TRAITS(Tmm , BaseReg::kTypeCustom + 5, BaseReg::kGroupVirt + 5, 0 , 8 , Type::kIdVoid );
+ASMJIT_DEFINE_REG_TRAITS(Rip , BaseReg::kTypeIP , BaseReg::kGroupVirt + 6, 0 , 1 , Type::kIdVoid );
//! \endcond
//! Register (X86).
@@ -152,41 +154,78 @@ public:
//! Register type.
enum RegType : uint32_t {
- kTypeNone = BaseReg::kTypeNone, //!< No register type or invalid register.
- kTypeGpbLo = BaseReg::kTypeGp8Lo, //!< Low GPB register (AL, BL, CL, DL, ...).
- kTypeGpbHi = BaseReg::kTypeGp8Hi, //!< High GPB register (AH, BH, CH, DH only).
- kTypeGpw = BaseReg::kTypeGp16, //!< GPW register.
- kTypeGpd = BaseReg::kTypeGp32, //!< GPD register.
- kTypeGpq = BaseReg::kTypeGp64, //!< GPQ register (64-bit).
- kTypeXmm = BaseReg::kTypeVec128, //!< XMM register (SSE+).
- kTypeYmm = BaseReg::kTypeVec256, //!< YMM register (AVX+).
- kTypeZmm = BaseReg::kTypeVec512, //!< ZMM register (AVX512+).
- kTypeMm = BaseReg::kTypeOther0, //!< MMX register.
- kTypeKReg = BaseReg::kTypeOther1, //!< K register (AVX512+).
- kTypeSReg = BaseReg::kTypeCustom+0, //!< Segment register (None, ES, CS, SS, DS, FS, GS).
- kTypeCReg = BaseReg::kTypeCustom+1, //!< Control register (CR).
- kTypeDReg = BaseReg::kTypeCustom+2, //!< Debug register (DR).
- kTypeSt = BaseReg::kTypeCustom+3, //!< FPU (x87) register.
- kTypeBnd = BaseReg::kTypeCustom+4, //!< Bound register (BND).
- kTypeRip = BaseReg::kTypeIP, //!< Instruction pointer (EIP, RIP).
- kTypeCount = BaseReg::kTypeCustom+5 //!< Count of register types.
+ //! No register type or invalid register.
+ kTypeNone = BaseReg::kTypeNone,
+
+ //! Low GPB register (AL, BL, CL, DL, ...).
+ kTypeGpbLo = BaseReg::kTypeGp8Lo,
+ //! High GPB register (AH, BH, CH, DH only).
+ kTypeGpbHi = BaseReg::kTypeGp8Hi,
+ //! GPW register.
+ kTypeGpw = BaseReg::kTypeGp16,
+ //! GPD register.
+ kTypeGpd = BaseReg::kTypeGp32,
+ //! GPQ register (64-bit).
+ kTypeGpq = BaseReg::kTypeGp64,
+ //! XMM register (SSE+).
+ kTypeXmm = BaseReg::kTypeVec128,
+ //! YMM register (AVX+).
+ kTypeYmm = BaseReg::kTypeVec256,
+ //! ZMM register (AVX512+).
+ kTypeZmm = BaseReg::kTypeVec512,
+ //! MMX register.
+ kTypeMm = BaseReg::kTypeOther0,
+ //! K register (AVX512+).
+ kTypeKReg = BaseReg::kTypeOther1,
+ //! Instruction pointer (EIP, RIP).
+ kTypeRip = BaseReg::kTypeIP,
+ //! Segment register (None, ES, CS, SS, DS, FS, GS).
+ kTypeSReg = BaseReg::kTypeCustom + 0,
+ //! Control register (CR).
+ kTypeCReg = BaseReg::kTypeCustom + 1,
+ //! Debug register (DR).
+ kTypeDReg = BaseReg::kTypeCustom + 2,
+ //! FPU (x87) register.
+ kTypeSt = BaseReg::kTypeCustom + 3,
+ //! Bound register (BND).
+ kTypeBnd = BaseReg::kTypeCustom + 4,
+ //! TMM register (AMX_TILE)
+ kTypeTmm = BaseReg::kTypeCustom + 5,
+
+ //! Count of register types.
+ kTypeCount = BaseReg::kTypeCustom + 6
};
//! Register group.
enum RegGroup : uint32_t {
- kGroupGp = BaseReg::kGroupGp, //!< GP register group or none (universal).
- kGroupVec = BaseReg::kGroupVec, //!< XMM|YMM|ZMM register group (universal).
- kGroupMm = BaseReg::kGroupOther0, //!< MMX register group (legacy).
- kGroupKReg = BaseReg::kGroupOther1, //!< K register group.
-
- // These are not managed by BaseCompiler nor used by Func-API:
- kGroupSReg = BaseReg::kGroupVirt+0, //!< Segment register group.
- kGroupCReg = BaseReg::kGroupVirt+1, //!< Control register group.
- kGroupDReg = BaseReg::kGroupVirt+2, //!< Debug register group.
- kGroupSt = BaseReg::kGroupVirt+3, //!< FPU register group.
- kGroupBnd = BaseReg::kGroupVirt+4, //!< Bound register group.
- kGroupRip = BaseReg::kGroupVirt+5, //!< Instrucion pointer (IP).
- kGroupCount //!< Count of all register groups.
+ //! GP register group or none (universal).
+ kGroupGp = BaseReg::kGroupGp,
+ //! XMM|YMM|ZMM register group (universal).
+ kGroupVec = BaseReg::kGroupVec,
+ //! MMX register group (legacy).
+ kGroupMm = BaseReg::kGroupOther0,
+ //! K register group.
+ kGroupKReg = BaseReg::kGroupOther1,
+
+ // These are not managed by Compiler nor used by Func-API:
+
+ //! Segment register group.
+ kGroupSReg = BaseReg::kGroupVirt+0,
+ //! Control register group.
+ kGroupCReg = BaseReg::kGroupVirt+1,
+ //! Debug register group.
+ kGroupDReg = BaseReg::kGroupVirt+2,
+ //! FPU register group.
+ kGroupSt = BaseReg::kGroupVirt+3,
+ //! Bound register group.
+ kGroupBnd = BaseReg::kGroupVirt+4,
+ //! TMM register group.
+ kGroupTmm = BaseReg::kGroupVirt+5,
+ //! Instrucion pointer (IP).
+ kGroupRip = BaseReg::kGroupVirt+6,
+
+ //! Count of all register groups.
+ kGroupCount
};
//! Tests whether the register is a GPB register (8-bit).
@@ -221,6 +260,8 @@ public:
constexpr bool isSt() const noexcept { return hasSignature(RegTraits<kTypeSt>::kSignature); }
//! Tests whether the register is a bound register.
constexpr bool isBnd() const noexcept { return hasSignature(RegTraits<kTypeBnd>::kSignature); }
+ //! Tests whether the register is a TMM register.
+ constexpr bool isTmm() const noexcept { return hasSignature(RegTraits<kTypeTmm>::kSignature); }
//! Tests whether the register is RIP.
constexpr bool isRip() const noexcept { return hasSignature(RegTraits<kTypeRip>::kSignature); }
@@ -281,6 +322,7 @@ public:
static inline bool isDReg(const Operand_& op) noexcept { return op.as<Reg>().isDReg(); }
static inline bool isSt(const Operand_& op) noexcept { return op.as<Reg>().isSt(); }
static inline bool isBnd(const Operand_& op) noexcept { return op.as<Reg>().isBnd(); }
+ static inline bool isTmm(const Operand_& op) noexcept { return op.as<Reg>().isTmm(); }
static inline bool isRip(const Operand_& op) noexcept { return op.as<Reg>().isRip(); }
static inline bool isGpb(const Operand_& op, uint32_t rId) noexcept { return isGpb(op) & (op.id() == rId); }
@@ -299,6 +341,7 @@ public:
static inline bool isDReg(const Operand_& op, uint32_t rId) noexcept { return isDReg(op) & (op.id() == rId); }
static inline bool isSt(const Operand_& op, uint32_t rId) noexcept { return isSt(op) & (op.id() == rId); }
static inline bool isBnd(const Operand_& op, uint32_t rId) noexcept { return isBnd(op) & (op.id() == rId); }
+ static inline bool isTmm(const Operand_& op, uint32_t rId) noexcept { return isTmm(op) & (op.id() == rId); }
static inline bool isRip(const Operand_& op, uint32_t rId) noexcept { return isRip(op) & (op.id() == rId); }
};
@@ -368,19 +411,26 @@ class SReg : public Reg {
//! X86 segment id.
enum Id : uint32_t {
- kIdNone = 0, //!< No segment (default).
- kIdEs = 1, //!< ES segment.
- kIdCs = 2, //!< CS segment.
- kIdSs = 3, //!< SS segment.
- kIdDs = 4, //!< DS segment.
- kIdFs = 5, //!< FS segment.
- kIdGs = 6, //!< GS segment.
-
- //! Count of segment registers supported by AsmJit.
+ //! No segment (default).
+ kIdNone = 0,
+ //! ES segment.
+ kIdEs = 1,
+ //! CS segment.
+ kIdCs = 2,
+ //! SS segment.
+ kIdSs = 3,
+ //! DS segment.
+ kIdDs = 4,
+ //! FS segment.
+ kIdFs = 5,
+ //! GS segment.
+ kIdGs = 6,
+
+ //! Count of X86 segment registers supported by AsmJit.
//!
//! \note X86 architecture has 6 segment registers - ES, CS, SS, DS, FS, GS.
//! X64 architecture lowers them down to just FS and GS. AsmJit supports 7
- //! segment registers - all addressable in both and X64 modes and one
+ //! segment registers - all addressable in both X86 and X64 modes and one
//! extra called `SReg::kIdNone`, which is AsmJit specific and means that
//! there is no segment register specified.
kIdCount = 7
@@ -433,6 +483,8 @@ class DReg : public Reg { ASMJIT_DEFINE_FINAL_REG(DReg, Reg, RegTraits<kTypeDReg
class St : public Reg { ASMJIT_DEFINE_FINAL_REG(St, Reg, RegTraits<kTypeSt>) };
//! 128-bit BND register (BND+).
class Bnd : public Reg { ASMJIT_DEFINE_FINAL_REG(Bnd, Reg, RegTraits<kTypeBnd>) };
+//! 8192-bit TMM register (AMX).
+class Tmm : public Reg { ASMJIT_DEFINE_FINAL_REG(Tmm, Reg, RegTraits<kTypeTmm>) };
//! RIP register (X86).
class Rip : public Reg { ASMJIT_DEFINE_FINAL_REG(Rip, Reg, RegTraits<kTypeRip>) };
@@ -489,6 +541,8 @@ static constexpr DReg dr(uint32_t rId) noexcept { return DReg(rId); }
static constexpr St st(uint32_t rId) noexcept { return St(rId); }
//! Creates a 128-bit bound register operand.
static constexpr Bnd bnd(uint32_t rId) noexcept { return Bnd(rId); }
+//! Creates a TMM register operand.
+static constexpr Tmm tmm(uint32_t rId) noexcept { return Tmm(rId); }
static constexpr Gp al = Gp(GpbLo::kSignature, Gp::kIdAx);
static constexpr Gp bl = Gp(GpbLo::kSignature, Gp::kIdBx);
@@ -736,6 +790,15 @@ static constexpr Bnd bnd1 = Bnd(1);
static constexpr Bnd bnd2 = Bnd(2);
static constexpr Bnd bnd3 = Bnd(3);
+static constexpr Tmm tmm0 = Tmm(0);
+static constexpr Tmm tmm1 = Tmm(1);
+static constexpr Tmm tmm2 = Tmm(2);
+static constexpr Tmm tmm3 = Tmm(3);
+static constexpr Tmm tmm4 = Tmm(4);
+static constexpr Tmm tmm5 = Tmm(5);
+static constexpr Tmm tmm6 = Tmm(6);
+static constexpr Tmm tmm7 = Tmm(7);
+
static constexpr Rip rip = Rip(0);
#ifndef _DOXYGEN
diff --git a/tools/tablegen-x86.js b/tools/tablegen-x86.js
index dfd0f40..cc52b14 100644
--- a/tools/tablegen-x86.js
+++ b/tools/tablegen-x86.js
@@ -221,6 +221,9 @@ class GenUtils {
}
}
+ if (dbInst.attributes.Tsib)
+ f.Tsib = true;
+
if (dbInst.vsibReg)
f.Vsib = true;
@@ -509,7 +512,9 @@ class X86TableGen extends core.TableGen {
String(inst.encoding ).padEnd(19) + ", " +
String(inst.opcode0 ).padEnd(26) + ", " +
String(inst.opcode1 ).padEnd(26) + ", " +
- String("0" ).padEnd( 4) + ", " +
+ String("0" ).padEnd( 3) + ", " +
+ String("0" ).padEnd( 3) + ", " +
+ String("0" ).padEnd( 5) + ", " +
String("0" ).padEnd( 3) + ", " +
String("0" ).padEnd( 3) + "),\n";
}
@@ -930,6 +935,7 @@ const OpToAsmJitOp = {
"dreg" : "F(DReg)",
"st" : "F(St)",
"bnd" : "F(Bnd)",
+ "tmm" : "F(Tmm)",
"mem" : "F(Mem)",
"vm" : "F(Vm)",
@@ -1096,7 +1102,8 @@ class OSignature {
case "mm" :
case "xmm" :
case "ymm" :
- case "zmm" : mFlags[k] = true; break;
+ case "zmm" :
+ case "tmm" : mFlags[k] = true; break;
case "m8" :
case "m16" :
@@ -1108,8 +1115,9 @@ class OSignature {
case "m256" :
case "m512" :
case "m1024" : mFlags.mem = true; mMemFlags[k] = true; break;
- case "mib" : mFlags.mem = true; mMemFlags.mib = true; break;
- case "mem" : mFlags.mem = true; mMemFlags.mAny = true; break;
+ case "mib" : mFlags.mem = true; mMemFlags.mib = true; break;
+ case "mem" : mFlags.mem = true; mMemFlags.mAny = true; break;
+ case "tmem" : mFlags.mem = true; mMemFlags.mAny = true; break;
case "memBase" : mFlags.mem = true; mMemFlags.memBase = true; break;
case "memDS" : mFlags.mem = true; mMemFlags.memDS = true; break;
@@ -1814,8 +1822,11 @@ class InstRWInfoTable extends core.Task {
constructor() {
super("InstRWInfoTable");
- this.rwInfoIndex = [];
- this.rwInfoTable = new IndexedArray();
+ this.rwInfoIndexA = [];
+ this.rwInfoIndexB = [];
+ this.rwInfoTableA = new IndexedArray();
+ this.rwInfoTableB = new IndexedArray();
+
this.rmInfoTable = new IndexedArray();
this.opInfoTable = new IndexedArray();
@@ -1954,21 +1965,30 @@ class InstRWInfoTable extends core.Task {
CxxUtils.struct(...(rwOpsIndex.map(function(item) { return String(item).padEnd(2); })))
);
- this.rwInfoIndex.push(this.rwInfoTable.addIndexed(rwData));
+ if (i == 0)
+ this.rwInfoIndexA.push(this.rwInfoTableA.addIndexed(rwData));
+ else
+ this.rwInfoIndexB.push(this.rwInfoTableB.addIndexed(rwData));
}
});
var s = "";
- s += "const uint8_t InstDB::rwInfoIndex[Inst::_kIdCount * 2] = {\n" + StringUtils.format(this.rwInfoIndex, kIndent, -1) + "\n};\n";
+ s += "const uint8_t InstDB::rwInfoIndexA[Inst::_kIdCount] = {\n" + StringUtils.format(this.rwInfoIndexA, kIndent, -1) + "\n};\n";
+ s += "\n";
+ s += "const uint8_t InstDB::rwInfoIndexB[Inst::_kIdCount] = {\n" + StringUtils.format(this.rwInfoIndexB, kIndent, -1) + "\n};\n";
+ s += "\n";
+ s += "const InstDB::RWInfo InstDB::rwInfoA[] = {\n" + StringUtils.format(this.rwInfoTableA, kIndent, true) + "\n};\n";
s += "\n";
- s += "const InstDB::RWInfo InstDB::rwInfo[] = {\n" + StringUtils.format(this.rwInfoTable, kIndent, true) + "\n};\n";
+ s += "const InstDB::RWInfo InstDB::rwInfoB[] = {\n" + StringUtils.format(this.rwInfoTableB, kIndent, true) + "\n};\n";
s += "\n";
s += "const InstDB::RWInfoOp InstDB::rwInfoOp[] = {\n" + StringUtils.format(this.opInfoTable, kIndent, true) + "\n};\n";
s += "\n";
s += "const InstDB::RWInfoRm InstDB::rwInfoRm[] = {\n" + StringUtils.format(this.rmInfoTable, kIndent, true) + "\n};\n";
- const size = this.rwInfoIndex.length +
- this.rwInfoTable.length * 8 +
+ const size = this.rwInfoIndexA.length +
+ this.rwInfoIndexB.length +
+ this.rwInfoTableA.length * 8 +
+ this.rwInfoTableB.length * 8 +
this.rmInfoTable.length * 4 +
this.opInfoTable.length * 24;
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-11 18:57:05 +0300