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authorAlexey 'Cluster' Avdyukhin <clusterrr@clusterrr.com>2021-01-30 13:02:09 +0300
committerAlexey 'Cluster' Avdyukhin <clusterrr@clusterrr.com>2021-01-30 13:02:09 +0300
commit872b81c9438ec4b461a48fe06ff7bf21375e5867 (patch)
treeb54b0a8edcd4564465c2aea6f8b0258e1d409811
parent6141aee9dda92c178bebbfce7384751dafea96d7 (diff)
Mapper #83 support
-rw-r--r--CoolGirl_config.vh1
-rw-r--r--CoolGirl_mappers.vh74
2 files changed, 69 insertions, 6 deletions
diff --git a/CoolGirl_config.vh b/CoolGirl_config.vh
index 03dc20a..c0278cb 100644
--- a/CoolGirl_config.vh
+++ b/CoolGirl_config.vh
@@ -23,6 +23,7 @@ parameter ENABLE_MAPPER_073 = 0, // mapper #073 - VRC3
parameter ENABLE_MAPPER_075 = 0, // mapper #075 - VRC1
parameter ENABLE_MAPPER_078 = 1, // mapper #078 - Irem: Holy Diver and Uchuusen - Cosmo Carrier
parameter ENABLE_MAPPER_079_113_146 = 0, // mappers #079, #113, #146 - NINA-03/06 and Sachen 3015
+parameter ENABLE_MAPPER_083 = 0, // mapper #083 - Cony/Yoko, submapper #0 only
parameter ENABLE_MAPPER_087 = 1, // mapper #087 - Jaleco
parameter ENABLE_MAPPER_090 = 1, // mapper #090 - JY (partical support): Aladdin only
parameter ENABLE_MAPPER_090_ACCURATE_IRQ = 0,// mapper #090 accurate IRQs: for Super Mario World
diff --git a/CoolGirl_mappers.vh b/CoolGirl_mappers.vh
index bf54b01..94bcb2f 100644
--- a/CoolGirl_mappers.vh
+++ b/CoolGirl_mappers.vh
@@ -41,7 +41,8 @@ assign irq = (
vrc4_irq_out |
vrc3_irq_out |
mapper69_irq_out |
- mapper42_irq_out |
+ mapper42_irq_out |
+ mapper83_irq_out |
mapper90_irq_out) ? 1'b0 : 1'bZ;
// for MMC3 scanline-based interrupts, counts A12 rises after long A12 falls
reg mmc3_irq_enabled = 0; // register to enable/disable counter
@@ -78,14 +79,14 @@ reg mapper69_irq_enabled = 0; // register to enable/disable IRQ
reg mapper69_counter_enabled = 0; // register to enable/disable counter
reg [15:0] mapper69_irq_value = 0; // counter itself (downcounting)
reg mapper69_irq_out = 0; // stores 1 when IRQ is triggered
-// for VRC4 CPU-based interrupts
+// for VRC4, CPU-based interrupts
reg [7:0] vrc4_irq_value = 0; // counter itself (upcounting)
reg [2:0] vrc4_irq_control = 0; // IRQ settings
reg [7:0] vrc4_irq_latch = 0; // stores counter reload latch value
reg [6:0] vrc4_irq_prescaler = 0; // prescaler counter for VRC4
reg [1:0] vrc4_irq_prescaler_counter = 0; // prescaler cicles counter for VRC4
reg vrc4_irq_out = 0; // stores 1 when IRQ is triggered
-// for VRC3 CPU-based interrupts
+// for VRC3, CPU-based interrupts
reg [15:0] vrc3_irq_value = 0; // counter itself (upcounting)
reg [3:0] vrc3_irq_control = 0; // IRQ settings
reg [15:0] vrc3_irq_latch = 0; // stores counter reload latch value
@@ -94,6 +95,11 @@ reg vrc3_irq_out = 0; // stores 1 when IRQ is triggered
reg mapper42_irq_enabled = 0; // register to enable/disable counter
reg [14:0] mapper42_irq_value = 0; // counter itself (upcounting)
wire mapper42_irq_out = mapper42_irq_value[14] & mapper42_irq_value[13];
+// for mapper #83, CPU-based interrupts
+reg mapper83_irq_enabled_latch = 0;
+reg mapper83_irq_enabled = 0;
+reg [15:0] mapper83_irq_counter = 0;
+reg mapper83_irq_out = 0;
// for mapper #90, unfiltered PPU A12 counter
reg mapper90_irq_enabled = 0; // register to enable/disable counter
reg [7:0] mapper90_xor; // XOR register (is not used actually)
@@ -103,7 +109,7 @@ reg mapper90_irq_reload = 0; // flag to reload counter and prescaler from
reg mapper90_irq_reload_clear = 0; // flag to clear reload flag
reg mapper90_irq_pending = 0; // flag of pending IRQ
reg mapper90_irq_out = 0; // stores 1 when IRQ is triggered
-reg mapper90_irq_out_clear = 0; // flag to clear pending flag
+reg mapper90_irq_out_clear = 0; // flag to clear pending flag
// Mapper specific stuff
// for MMC2/MMC4
@@ -142,8 +148,10 @@ assign {cpu_data_out_enabled, cpu_data_out} =
{1'b1, mmc5_irq_out, ~new_screen, 6'b000000} :
(ENABLE_MAPPER_036 && mapper == 6'b011101 && {cpu_addr_in[14:13], cpu_addr_in[8]} == 3'b101) ? // Need by Strike Wolf, being simplified mapper, this cart still uses some TCX mapper features andrely on it
{1'b1, 2'b00, prg_bank_a[3:2], 4'b00} :
+ (ENABLE_MAPPER_083 && mapper == 6'b100011 && {cpu_addr_in[14:12]} == 3'b101) ? // $5000 - DIP switches
+ {1'b1, 6'b000000, flags[1:0]} :
(ENABLE_MAPPER_090_MULTIPLIER && (mapper == 6'b001101) && (cpu_addr_in[14:0] == 15'h5800)) ? {1'b1, mul[7:0]} :
- (ENABLE_MAPPER_090_MULTIPLIER && (mapper == 6'b001101) && (cpu_addr_in[14:0] == 15'h5801)) ? {1'b1, mul[15:8]} :
+ (ENABLE_MAPPER_090_MULTIPLIER && (mapper == 6'b001101) && (cpu_addr_in[14:0] == 15'h5801)) ? {1'b1, mul[15:8]} :
9'b000000000
): 9'b000000000;
@@ -335,7 +343,18 @@ begin
begin
mapper42_irq_value[14:0] <= mapper42_irq_value[14:0] + 1'b1;
end
-
+
+ // for mapper #83
+ if (ENABLE_MAPPER_083)
+ begin
+ if (mapper83_irq_enabled)
+ begin
+ if (mapper83_irq_counter == 0)
+ mapper83_irq_out <= 1;
+ mapper83_irq_counter = mapper83_irq_counter - 1'b1;
+ end
+ end
+
// for mapper #90
if (mapper90_irq_pending & !mapper90_irq_out_clear)
begin
@@ -1173,6 +1192,49 @@ begin
3'b110: chr_bank_a[5:2] <= cpu_data_in[3:0]; // $E000-$EFFF
3'b111: chr_bank_e[5:2] <= cpu_data_in[3:0]; // $F000-$FFFF
endcase
+ end
+
+ // Mapper #83 - used for games from Cony, also known as Yoko
+ if (ENABLE_MAPPER_083 && (mapper == 6'b100011))
+ begin
+ case (cpu_addr_in[9:8])
+ 2'b01: begin // $81xx
+ mirroring <= cpu_data_in[1:0];
+ mapper83_irq_enabled_latch <= cpu_data_in[7];
+ end
+ 2'b10: begin // 82xx
+ if (!cpu_addr_in[0])
+ begin
+ mapper83_irq_out <= 0;
+ mapper83_irq_counter[7:0] <= cpu_data_in[7:0];
+ end else begin
+ mapper83_irq_enabled <= mapper83_irq_enabled_latch;
+ mapper83_irq_counter[15:8] <= cpu_data_in[7:0];
+ end
+ end
+ 2'b11: begin // 83xx
+ if (!cpu_addr_in[4])
+ begin
+ case (cpu_addr_in[1:0])
+ 2'b00: prg_bank_a[7:0] <= cpu_data_in[7:0];
+ 2'b01: prg_bank_b[7:0] <= cpu_data_in[7:0];
+ 2'b10: prg_bank_c[7:0] <= cpu_data_in[7:0];
+ //2'b11: prg_bank_6000[7:0] <= cpu_data_in[7:0];
+ endcase
+ end else begin
+ case (cpu_addr_in[2:0])
+ 3'b000: chr_bank_a[7:0] <= cpu_data_in[7:0];
+ 3'b001: chr_bank_b[7:0] <= cpu_data_in[7:0];
+ 3'b010: chr_bank_c[7:0] <= cpu_data_in[7:0];
+ 3'b011: chr_bank_d[7:0] <= cpu_data_in[7:0];
+ 3'b100: chr_bank_e[7:0] <= cpu_data_in[7:0];
+ 3'b101: chr_bank_f[7:0] <= cpu_data_in[7:0];
+ 3'b110: chr_bank_g[7:0] <= cpu_data_in[7:0];
+ 3'b111: chr_bank_h[7:0] <= cpu_data_in[7:0];
+ endcase
+ end
+ end
+ endcase
end
end // romsel
end // write