blob: ac72301456b7372b0a2e57f038e5d4284dd45e17 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
|
TEST_RW .rs 1
TEST_XOR .rs 1
TEST_PRG_RAM_FAILED .rs 1
TEST_CHR_RAM_FAILED .rs 1
TEST_BANK .rs 1
do_tests:
; detect CHR RAM size
jsr detect_chr_ram_size
; check presense of PRG RAM
jsr prg_ram_detect
do_tests_again:
; invert TEST_XOR
lda <TEST_XOR
eor #$FF
sta <TEST_XOR
lda #%00000000 ; disable PPU
sta PPUCTRL
sta PPUMASK
jsr waitblank_simple
lda #$00
; writing
sta <TEST_RW
; reset result
sta <TEST_PRG_RAM_FAILED
sta <TEST_CHR_RAM_FAILED
lda PRG_RAM_PRESENT
beq .chr
jsr enable_prg_ram
.prg_ram:
jsr random_init
; select bank
lda #(PRG_RAM_BANKS-1)
sta <TEST_BANK
.prg_ram_test_loop_bank:
jsr beep
lda <TEST_BANK
jsr select_prg_ram_bank
lda #$00
sta <COPY_DEST_ADDR
lda #$60
sta <COPY_DEST_ADDR+1
ldy #$00
ldx #$20
.prg_ram_test_loop:
jsr random ; generate next random number
lda <TEST_RW ; reading or writing?
bne .prg_ram_test_read
lda <RANDOM
eor <TEST_XOR
sta [COPY_DEST_ADDR], y
jmp .prg_ram_test_next
.prg_ram_test_read:
lda <RANDOM
eor <TEST_XOR
cmp [COPY_DEST_ADDR], y
beq .prg_ram_test_next
lda #1
sta TEST_PRG_RAM_FAILED
.prg_ram_test_next:
iny
bne .prg_ram_test_loop
inc COPY_SOURCE_ADDR+1
inc COPY_DEST_ADDR+1
dex
bne .prg_ram_test_loop
dec <TEST_BANK
bpl .prg_ram_test_loop_bank
lda <TEST_RW
bne .chr
inc <TEST_RW
jmp .prg_ram
.chr:
jsr disable_prg_ram
lda #$00
sta TEST_RW ; writing
.chr_again:
jsr random_init
lda #1
ldx CHR_RAM_SIZE
; shift 1 to the left CHR_RAM_SIZE times
.shift_loop:
dex
bmi .shift_done
asl A
jmp .shift_loop
.shift_done:
; minus 1
sec
sbc #1
sta <TEST_BANK
jsr enable_chr_write
.chr_test_loop_bank:
jsr beep
lda <TEST_BANK
jsr select_chr_bank
lda #$00
sta PPUADDR
sta PPUADDR
ldy #$00
ldx #$20
lda <TEST_RW
beq .chr_test_loop
lda PPUDATA ; need to discard first read
.chr_test_loop:
jsr random ; generate next random number
lda <TEST_RW ; reading or writing?
bne .chr_test_read
lda <RANDOM
eor <TEST_XOR
sta PPUDATA
jmp .chr_test_next
.chr_test_read:
lda <RANDOM
eor <TEST_XOR
cmp PPUDATA
beq .chr_test_next
lda #1
sta <TEST_CHR_RAM_FAILED
.chr_test_next:
iny
bne .chr_test_loop
dex
bne .chr_test_loop
dec <TEST_BANK
bpl .chr_test_loop_bank
lda <TEST_RW
bne .tests_end
inc <TEST_RW
jmp .chr_again
; results
.tests_end:
jsr load_base_chr
jsr clear_screen
jsr load_text_attributes
jsr preload_base_palette
jsr load_palette
; PRG RAM test result
lda #$21
sta PPUADDR
lda #$A4
sta PPUADDR
lda #LOW(string_prg_ram_test)
sta <COPY_SOURCE_ADDR
lda #HIGH(string_prg_ram_test)
sta <COPY_SOURCE_ADDR+1
jsr print_text
; is it present?
lda PRG_RAM_PRESENT
bne .prg_ram_test_result
; PRG RAM is not present
lda #LOW(string_not_available)
sta <COPY_SOURCE_ADDR
lda #HIGH(string_not_available)
sta <COPY_SOURCE_ADDR+1
jmp .prg_ram_test_result_print
.prg_ram_test_result:
ldx TEST_PRG_RAM_FAILED
bne .prg_ram_test_result_fail
; PRG RAM test OK
lda #LOW(string_passed)
sta <COPY_SOURCE_ADDR
lda #HIGH(string_passed)
sta <COPY_SOURCE_ADDR+1
jmp .prg_ram_test_result_print
.prg_ram_test_result_fail:
; PRG RAM test failed
lda #LOW(string_failed)
sta <COPY_SOURCE_ADDR
lda #HIGH(string_failed)
sta <COPY_SOURCE_ADDR+1
jmp .prg_ram_test_result_print
.prg_ram_test_result_print:
jsr print_text
; CHR RAM test result
lda #$21
sta PPUADDR
lda #$E4
sta PPUADDR
lda #LOW(string_chr_ram_test)
sta <COPY_SOURCE_ADDR
lda #HIGH(string_chr_ram_test)
sta <COPY_SOURCE_ADDR+1
jsr print_text
lda <CHR_RAM_SIZE
asl A
tay
lda chr_ram_sizes, y
sta <COPY_SOURCE_ADDR
lda chr_ram_sizes+1, y
sta <COPY_SOURCE_ADDR+1
jsr print_text
ldx TEST_CHR_RAM_FAILED
bne .chr_test_result_fail
lda #LOW(string_passed)
sta <COPY_SOURCE_ADDR
lda #HIGH(string_passed)
sta <COPY_SOURCE_ADDR+1
jmp .chr_test_result_print
.chr_test_result_fail:
lda #LOW(string_failed)
sta <COPY_SOURCE_ADDR
lda #HIGH(string_failed)
sta <COPY_SOURCE_ADDR+1
.chr_test_result_print:
jsr print_text
lda #0
sta PPUSCROLL
sta PPUSCROLL
jsr waitblank_simple
lda #%00001010 ; enable PPU and show result
sta PPUMASK
ldx #$FF
.do_tests_wait:
jsr waitblank_simple
dex
bne .do_tests_wait
lda #0
ora TEST_PRG_RAM_FAILED
ora TEST_CHR_RAM_FAILED
beq .do_tests_ok
jsr error_sound
.do_tests_stop:
jmp .do_tests_wait
.do_tests_ok:
jmp do_tests_again
|
