diff options
author | Radek Doulik <radekdoulik@gmail.com> | 2022-11-10 21:24:39 +0300 |
---|---|---|
committer | GitHub <noreply@github.com> | 2022-11-10 21:24:39 +0300 |
commit | 72ad6649b505a98cae5ff296818df2d7a5da4807 (patch) | |
tree | bfb8cd1d8aa0b90184d53a0602baadb7697af06c | |
parent | cd7e8718fcf5d5e55f9529c206a8c7205b45af08 (diff) |
[wasm] Add Vector128.AndNot intrinsics (#78133)
* [wasm] Add Vector128.AndNot intrinsics
C#
var v = Vector128.Create(System.Random.Shared.Next(), System.Random.Shared.Next(), System.Random.Shared.Next(), System.Random.Shared.Next());
var v2 = Vector128.Create(System.Random.Shared.Next(), System.Random.Shared.Next(), System.Random.Shared.Next(), System.Random.Shared.Next());
v = Vector128.AndNot(v, v2);
is emitted as
...
i32x4.splat [SIMD]
local.get $5
i32x4.replace.lane 1 [SIMD]
local.get $6
i32x4.replace.lane 2 [SIMD]
local.get $7
i32x4.replace.lane 3 [SIMD]
local.get $8
i32x4.splat [SIMD]
local.get $9
i32x4.replace.lane 1 [SIMD]
local.get $10
i32x4.replace.lane 2 [SIMD]
local.get $2
i32x4.replace.lane 3 [SIMD]
v128.andnot [SIMD]
v128.store offset:8 align:3 [SIMD]
...
* Review feedback
-rw-r--r-- | src/mono/mono/mini/mini-llvm.c | 24 | ||||
-rw-r--r-- | src/mono/mono/mini/mini-ops.h | 2 | ||||
-rw-r--r-- | src/mono/mono/mini/simd-intrinsics.c | 10 |
3 files changed, 18 insertions, 18 deletions
diff --git a/src/mono/mono/mini/mini-llvm.c b/src/mono/mono/mini/mini-llvm.c index 42b09634752..0913606d9c6 100644 --- a/src/mono/mono/mini/mini-llvm.c +++ b/src/mono/mono/mini/mini-llvm.c @@ -8775,18 +8775,6 @@ MONO_RESTORE_WARNING break; } - case OP_SSE_ANDN: { - LLVMValueRef minus_one [2]; - minus_one [0] = const_int64 (-1); - minus_one [1] = const_int64 (-1); - LLVMValueRef vec_lhs_i64 = convert (ctx, lhs, sse_i8_t); - LLVMValueRef vec_xor = LLVMBuildXor (builder, vec_lhs_i64, LLVMConstVector (minus_one, 2), ""); - LLVMValueRef vec_rhs_i64 = convert (ctx, rhs, sse_i8_t); - LLVMValueRef vec_and = LLVMBuildAnd (builder, vec_rhs_i64, vec_xor, ""); - values [ins->dreg] = LLVMBuildBitCast (builder, vec_and, type_to_sse_type (ins->inst_c1), ""); - break; - } - case OP_SSE_ADDSS: case OP_SSE_SUBSS: case OP_SSE_DIVSS: @@ -9594,6 +9582,18 @@ MONO_RESTORE_WARNING #endif #if defined(TARGET_X86) || defined(TARGET_AMD64) || defined(TARGET_WASM) + case OP_VECTOR_ANDN: { + LLVMValueRef minus_one [2]; + minus_one [0] = const_int64 (-1); + minus_one [1] = const_int64 (-1); + LLVMValueRef vec_lhs_i64 = convert (ctx, lhs, sse_i8_t); + LLVMValueRef vec_xor = LLVMBuildXor (builder, vec_lhs_i64, LLVMConstVector (minus_one, 2), ""); + LLVMValueRef vec_rhs_i64 = convert (ctx, rhs, sse_i8_t); + LLVMValueRef vec_and = LLVMBuildAnd (builder, vec_rhs_i64, vec_xor, ""); + values [ins->dreg] = LLVMBuildBitCast (builder, vec_and, type_to_sse_type (ins->inst_c1), ""); + break; + } + case OP_VECTOR_IABS: { // %sub = sub <16 x i8> zeroinitializer, %arg // %cmp = icmp sgt <16 x i8> %arg, zeroinitializer diff --git a/src/mono/mono/mini/mini-ops.h b/src/mono/mono/mini/mini-ops.h index 9ccdad66af3..afe455808d5 100644 --- a/src/mono/mono/mini/mini-ops.h +++ b/src/mono/mono/mini/mini-ops.h @@ -1027,6 +1027,7 @@ MINI_OP(OP_CVTTPD2DQ, "cvttpd2dq", XREG, XREG, NONE) MINI_OP(OP_CVTTPS2DQ, "cvttps2dq", XREG, XREG, NONE) MINI_OP(OP_VECTOR_IABS, "vector_integer_abs", XREG, XREG, NONE) +MINI_OP(OP_VECTOR_ANDN, "vector_andnot", XREG, XREG, XREG) /* sse 1 */ /* inst_c1 is target type */ @@ -1044,7 +1045,6 @@ MINI_OP3(OP_SSE_SHUFPS, "sse_shufps", XREG, XREG, XREG, IREG) MINI_OP(OP_SSE_AND, "sse_and", XREG, XREG, XREG) MINI_OP(OP_SSE_OR, "sse_or", XREG, XREG, XREG) MINI_OP(OP_SSE_XOR, "sse_xor", XREG, XREG, XREG) -MINI_OP(OP_SSE_ANDN, "sse_andn", XREG, XREG, XREG) MINI_OP(OP_SSE_ADDSS, "sse_addss", XREG, XREG, XREG) MINI_OP(OP_SSE_SUBSS, "sse_subss", XREG, XREG, XREG) MINI_OP(OP_SSE_DIVSS, "sse_divss", XREG, XREG, XREG) diff --git a/src/mono/mono/mini/simd-intrinsics.c b/src/mono/mono/mini/simd-intrinsics.c index e414260389c..42076ca77f9 100644 --- a/src/mono/mono/mini/simd-intrinsics.c +++ b/src/mono/mono/mini/simd-intrinsics.c @@ -1151,7 +1151,7 @@ emit_sri_vector (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsi // args [0] & ~vector(-0.0) MonoInst *zero = emit_xzero(cfg, arg_class); // 0.0 zero = emit_simd_ins (cfg, klass, OP_NEGATION, zero->dreg, -1); // -0.0 - MonoInst *ins = emit_simd_ins (cfg, klass, OP_SSE_ANDN, zero->dreg, args [0]->dreg); + MonoInst *ins = emit_simd_ins (cfg, klass, OP_VECTOR_ANDN, zero->dreg, args [0]->dreg); ins->inst_c1 = arg0_type; return ins; } else { @@ -1184,14 +1184,14 @@ emit_sri_vector (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsi return NULL; #ifdef TARGET_ARM64 return emit_simd_ins_for_sig (cfg, klass, OP_ARM64_BIC, -1, arg0_type, fsig, args); -#elif defined(TARGET_AMD64) +#elif defined(TARGET_AMD64) || defined(TARGET_WASM) /* Swap lhs and rhs because Vector128 needs lhs & !rhs whereas SSE2 does !lhs & rhs */ MonoInst *tmp = args[0]; args[0] = args[1]; args[1] = tmp; - return emit_simd_ins_for_sig (cfg, klass, OP_SSE_ANDN, -1, arg0_type, fsig, args); + return emit_simd_ins_for_sig (cfg, klass, OP_VECTOR_ANDN, -1, arg0_type, fsig, args); #else return NULL; #endif @@ -3199,7 +3199,7 @@ static SimdIntrinsic sse_methods [] = { {SN_Add, OP_XBINOP, OP_FADD}, {SN_AddScalar, OP_SSE_ADDSS}, {SN_And, OP_SSE_AND}, - {SN_AndNot, OP_SSE_ANDN}, + {SN_AndNot, OP_VECTOR_ANDN}, {SN_CompareEqual, OP_XCOMPARE_FP, CMP_EQ}, {SN_CompareGreaterThan, OP_XCOMPARE_FP,CMP_GT}, {SN_CompareGreaterThanOrEqual, OP_XCOMPARE_FP, CMP_GE}, @@ -3290,7 +3290,7 @@ static SimdIntrinsic sse2_methods [] = { {SN_AddSaturate, OP_SSE2_ADDS}, {SN_AddScalar, OP_SSE2_ADDSD}, {SN_And, OP_SSE_AND}, - {SN_AndNot, OP_SSE_ANDN}, + {SN_AndNot, OP_VECTOR_ANDN}, {SN_Average}, {SN_CompareEqual}, {SN_CompareGreaterThan}, |