add F7 (#84)

6 files changed, 42 insertions, 7 deletions

diff --git a/Makefile b/Makefile
index 4fce17f..763456a 100644
--- a/Makefile
+++ b/Makefile
@@ -242,9 +242,20 @@ stm32f405xg_hs: clean
 						DEFINES='STM32F4 STM32F405xx USBD_SOF_DISABLED USBD_PRIMARY_OTGHS' \
 						CFLAGS='-mcpu=cortex-m4'
 
-
 stm32f401xc: clean
 	@$(MAKE) demo STARTUP='$(CMSISDEV)/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f401xc.s' \
 						LDSCRIPT='demo/stm32f401xc.ld' \
 						DEFINES='STM32F4 STM32F401xC USBD_SOF_DISABLED' \
-						CFLAGS='-mcpu=cortex-m4'						
+						CFLAGS='-mcpu=cortex-m4'
+
+stm32f745xe: clean
+	@$(MAKE) demo STARTUP='$(CMSISDEV)/ST/STM32F7xx/Source/Templates/gcc/startup_stm32f745xx.s' \
+						LDSCRIPT='demo/stm32f745xe.ld' \
+						DEFINES='STM32F7 STM32F745xx USBD_SOF_DISABLED' \
+						CFLAGS='-mcpu=cortex-m7'
+
+stm32f745xe_hs: clean
+	@$(MAKE) demo STARTUP='$(CMSISDEV)/ST/STM32F7xx/Source/Templates/gcc/startup_stm32f745xx.s' \
+						LDSCRIPT='demo/stm32f745xe.ld' \
+						DEFINES='STM32F7 STM32F745xx USBD_SOF_DISABLED USBD_PRIMARY_OTGHS' \
+						CFLAGS='-mcpu=cortex-m7'
diff --git a/demo/cdc_startup.c b/demo/cdc_startup.c
index a8705d3..ee68bde 100644
--- a/demo/cdc_startup.c
+++ b/demo/cdc_startup.c
@@ -114,7 +114,7 @@ static void cdc_init_rcc (void) {
 
 
 #elif defined(STM32F429xx) || defined(STM32F405xx) \
-    || defined(STM32F401xC) || defined(STM32F401xE)  || defined(STM32F411xE) 
+    || defined(STM32F401xC) || defined(STM32F401xE)  || defined(STM32F411xE)
     /* set flash latency 2WS */
     _BMD(FLASH->ACR, FLASH_ACR_LATENCY, FLASH_ACR_LATENCY_2WS);
     /* setting up PLL 16MHz HSI, VCO=144MHz, PLLP = 72MHz PLLQ = 48MHz  */
@@ -144,7 +144,7 @@ static void cdc_init_rcc (void) {
     _BMD(GPIOA->MODER, (0x03 << 22) | (0x03 << 24), (0x02 << 22) | (0x02 << 24));
     #endif //defined(USBD_PRIMARY_OTGHS)
 
-#elif defined(STM32F446xx)
+#elif defined(STM32F446xx) || defined(STM32F745xx)
     /* set flash latency 2WS */
     _BMD(FLASH->ACR, FLASH_ACR_LATENCY, FLASH_ACR_LATENCY_2WS);
     /* setting up PLL 16MHz HSI, VCO=144MHz, PLLP = 72MHz PLLQ = 48MHz  */
diff --git a/demo/stm32f745xe.ld b/demo/stm32f745xe.ld
new file mode 100644
index 0000000..6f1bb96
--- /dev/null
+++ b/demo/stm32f745xe.ld
@@ -0,0 +1,11 @@
+ENTRY(Reset_Handler)
+MEMORY
+{
+    ROM   (rx): ORIGIN = 0x08000000, LENGTH = 512K
+    ITCM (rwx): ORIGIN = 0x00000000, LENGTH = 16K
+    DTCM (rw):  ORIGIN = 0x20000000, LENGTH = 64K
+    RAM  (rwx): ORIGIN = 0x20010000, LENGTH = 240K
+    RAM2 (rwx): ORIGIN = 0x2004C000, LENGTH = 16K
+}
+
+INCLUDE sections.ld
diff --git a/hardware.md b/hardware.md
index ae53ccf..1c440e9 100644
--- a/hardware.md
+++ b/hardware.md
@@ -20,6 +20,7 @@
 | stm32l053x8    | NUCLEO-L053R8 + NUCLEO2USB |                                             |
 | stm32f405xg    | NUCLEO-F405RG + NUCLEO2USB | based on NUCLEO-F103RE, 0.1uF at SB33, SB38 |
 | stm32f405xg_hs | NUCLEO-F405RG + NUCLEO2USB | based on NUCLEO-F103RE, 0.1uF at SB33, SB38 |
-
+| stm32f745xe    | NUCO-V-F745VE + NUCLEO2USB |                                             |
 
 [NUCLEO2USB SHIELD](https://github.com/dmitrystu/Nucleo2USB)
+[NUCO-V](https://github.com/dmitrystu/nuco-v)
\ No newline at end of file
diff --git a/inc/usb.h b/inc/usb.h
index f77f931..5924b01 100644
--- a/inc/usb.h
+++ b/inc/usb.h
@@ -110,7 +110,7 @@
     #endif
     #define usbd_hw usbd_otgfs
 
-#elif defined(STM32F446xx)
+#elif defined(STM32F446xx) || defined(STM32F722xx) || defined (STM32F745xx)
     #define USBD_STM32F446FS
     #define USBD_STM32F446HS
 
diff --git a/readme.md b/readme.md
index da712c5..9cb346f 100644
--- a/readme.md
+++ b/readme.md
@@ -82,6 +82,17 @@ All requirements can be downloaded into a directory specified in environment var
         <td>usbd_otgfs</td>
         <td>usbd_stm32f105_otgfs.c</td>
     </tr>
+        <tr>
+        <td rowspan="2">STM32F4x6 STM32F7</td>
+        <td nowrap>Doublebuffered<br/>6 endpoints<br/>VBUS detection<br/>SOF output</td>
+        <td>usbd_otgfs</td>
+        <td>usbd_stm32f446_otgfs.c</td>
+    </tr>
+    <tr>
+        <td nowrap>Doublebuffered<br/>9 endpoints<br/>VBUS detection<br/>SOF output</td>
+        <td>usbd_otghs</td>
+        <td>usbd_stm32f446_otghs.c</td>
+    </tr>
 </table>
 
 1. Single physical endpoint can be used to implement
@@ -93,7 +104,8 @@ All requirements can be downloaded into a directory specified in environment var
 
 3. Tested with STM32L052K8, STM32L100RC, STM32L476RG, STM32F072C8, STM32F103C8, STM32F103CB,
 STM32F303CC, STM32F303RE, STM32F429ZI, STM32F105RBT6, STM32F107VCT6, STM32L433CCT6, STM32F070CBT6,
-STM32G431RB, STM32F411CEUx, STM32F405RG, STM32F446RE, STM32F373CC, STM32L053R8, GD32F103C8T6.
+STM32G431RB, STM32F411CEUx, STM32F405RG, STM32F446RE, STM32F373CC, STM32L053R8, GD32F103C8T6,
+STM32F745VE.
 See [hardware.md](hardware.md) for details.
 
 ### Implemented definitions for classes ###