diff options
| author | Fragonite <48802408+Fragonite@users.noreply.github.com> | 2021-05-02 23:10:41 +0300 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-05-02 23:10:41 +0300 |
| commit | bacc89658b0a101d6b525444e42abd9a9e08e710 (patch) | |
| tree | 997c8da98246228ddf07934719072e6935188e8c | |
| parent | d6924e0ef7ea12f781fc28689cb868db939fc606 (diff) | |
STM32F303xC Demo (#88)
* STM32F303CC Demo (Device Descriptor Request Failed)
* STM32F303xC demo is now working (updated startup code).
Co-authored-by: BuildTools <unconfigured@null.spigotmc.org>
| -rw-r--r-- | Makefile | 5 | ||||
| -rw-r--r-- | demo/cdc_startup.c | 17 | ||||
| -rw-r--r-- | demo/stm32f303xc.ld | 9 |
3 files changed, 31 insertions, 0 deletions
@@ -147,6 +147,11 @@ stm32f303xe 32f303re-nucleo: clean DEFINES='STM32F3 STM32F303xE USBD_SOF_DISABLED' \ CFLAGS='-mcpu=cortex-m4' +stm32f303xc: clean + @$(MAKE) demo STARTUP='$(CMSISDEV)/ST/STM32F3xx/Source/Templates/gcc/startup_stm32f303xc.s' \ + LDSCRIPT='demo/stm32f303xc.ld' \ + DEFINES='STM32F3 STM32F303xC USBD_SOF_DISABLED' \ + CFLAGS='-mcpu=cortex-m4' stm32f105xb: clean @$(MAKE) demo STARTUP='$(CMSISDEV)/ST/STM32F1xx/Source/Templates/gcc/startup_stm32f105xc.s' \ diff --git a/demo/cdc_startup.c b/demo/cdc_startup.c index f5e7126..202b70b 100644 --- a/demo/cdc_startup.c +++ b/demo/cdc_startup.c @@ -92,6 +92,23 @@ static void cdc_init_rcc (void) { _BMD(RCC->CFGR, RCC_CFGR_SW, RCC_CFGR_SW_PLL); _WVL(RCC->CFGR, RCC_CFGR_SWS, RCC_CFGR_SWS_PLL); +#elif defined(STM32F303xC) + /* set flash latency 1WS */ + _BMD(FLASH->ACR, FLASH_ACR_LATENCY, FLASH_ACR_LATENCY_1); + /* use PLL 48MHz clock from 8Mhz HSI */ + _BMD(RCC->CFGR, + RCC_CFGR_PLLMUL | RCC_CFGR_PLLSRC | RCC_CFGR_USBPRE, + RCC_CFGR_PLLMUL12 | RCC_CFGR_USBPRE); + _BST(RCC->CR, RCC_CR_PLLON); + _WBS(RCC->CR, RCC_CR_PLLRDY); + /* switch to PLL */ + _BMD(RCC->CFGR, RCC_CFGR_SW, RCC_CFGR_SW_PLL); + _WVL(RCC->CFGR, RCC_CFGR_SWS, RCC_CFGR_SWS_PLL); + + _BST(RCC->AHBENR, RCC_AHBENR_GPIOAEN); + _BST(GPIOA->AFR[1], (0x0E << 12) | (0x0E << 16)); + _BMD(GPIOA->MODER, (0x03 << 22) | (0x03 << 24), (0x02 << 22) | (0x02 << 24)); + #elif defined(STM32F373xC) /* set flash latency 1WS */ _BMD(FLASH->ACR, FLASH_ACR_LATENCY, FLASH_ACR_LATENCY_1); diff --git a/demo/stm32f303xc.ld b/demo/stm32f303xc.ld new file mode 100644 index 0000000..2eee88a --- /dev/null +++ b/demo/stm32f303xc.ld @@ -0,0 +1,9 @@ +ENTRY(Reset_Handler) +MEMORY +{ + ROM (rx): ORIGIN = 0x08000000, LENGTH = 256K + RAM (rwx): ORIGIN = 0x20000000, LENGTH = 40K + CCMRAM (rwx): ORIGIN = 0x10000000, LENGTH = 8K +} + +INCLUDE sections.ld |