diff options
| author | Andrew Kurushin <ajax16384@gmail.com> | 2022-08-02 18:14:55 +0300 |
|---|---|---|
| committer | Mizux <mizux.dev@gmail.com> | 2022-08-04 22:54:23 +0300 |
| commit | 6d62f2fa649d1f1522f4062475b6c9279f9ef159 (patch) | |
| tree | 4c61a5b692ee7348397f793e1fcc6248de13684a | |
| parent | f60b6f84051976e2cb226de7278c1d7edbb2b74e (diff) | |
add intel Tremont microarch
| -rw-r--r-- | include/cpuinfo_x86.h | 1 | ||||
| -rw-r--r-- | src/impl_x86__base_implementation.inl | 5 | ||||
| -rw-r--r-- | test/cpuinfo_x86_test.cc | 28 |
3 files changed, 34 insertions, 0 deletions
diff --git a/include/cpuinfo_x86.h b/include/cpuinfo_x86.h index a7ca2c6..197432f 100644 --- a/include/cpuinfo_x86.h +++ b/include/cpuinfo_x86.h @@ -139,6 +139,7 @@ typedef enum { INTEL_BDW, // BROADWELL INTEL_SKL, // SKYLAKE INTEL_ATOM_GMT, // GOLDMONT + INTEL_ATOM_TMT, // TREMONT INTEL_KBL, // KABY LAKE INTEL_CFL, // COFFEE LAKE INTEL_WHL, // WHISKEY LAKE diff --git a/src/impl_x86__base_implementation.inl b/src/impl_x86__base_implementation.inl index 8b97449..63db6ff 100644 --- a/src/impl_x86__base_implementation.inl +++ b/src/impl_x86__base_implementation.inl @@ -465,6 +465,10 @@ X86Microarchitecture GetX86Microarchitecture(const X86Info* info) { case CPUID(0x06, 0x5C): // https://en.wikipedia.org/wiki/Goldmont return INTEL_ATOM_GMT; + case CPUID(0x06, 0x96): + case CPUID(0x06, 0x9C): + // https://en.wikichip.org/wiki/intel/microarchitectures/tremont + return INTEL_ATOM_TMT; case CPUID(0x06, 0x0F): case CPUID(0x06, 0x16): // https://en.wikipedia.org/wiki/Intel_Core_(microarchitecture) @@ -1784,6 +1788,7 @@ CacheInfo GetX86CacheInfo(void) { LINE(INTEL_BDW) \ LINE(INTEL_SKL) \ LINE(INTEL_ATOM_GMT) \ + LINE(INTEL_ATOM_TMT) \ LINE(INTEL_KBL) \ LINE(INTEL_CFL) \ LINE(INTEL_WHL) \ diff --git a/test/cpuinfo_x86_test.cc b/test/cpuinfo_x86_test.cc index f81b25d..7bcc24e 100644 --- a/test/cpuinfo_x86_test.cc +++ b/test/cpuinfo_x86_test.cc @@ -1172,6 +1172,34 @@ TEST_F(CpuidX86Test, INTEL_CML_H) { EXPECT_EQ(GetX86Microarchitecture(&info), X86Microarchitecture::INTEL_CML); } +// https://github.com/InstLatx64/InstLatx64/blob/master/GenuineIntel/GenuineIntel00906C0_JasperLake_01_CPUID.txt +TEST_F(CpuidX86Test, INTEL_ATOM_TMT_JASPER_LAKE) { + cpu().SetLeaves({ + {{0x00000000, 0}, Leaf{0x0000001B, 0x756E6547, 0x6C65746E, 0x49656E69}}, + {{0x00000001, 0}, Leaf{0x000906C0, 0x00800800, 0x4FF8EBBF, 0xBFEBFBFF}}, + }); + const auto info = GetX86Info(); + + EXPECT_STREQ(info.vendor, "GenuineIntel"); + EXPECT_EQ(info.family, 0x06); + EXPECT_EQ(info.model, 0x9C); + EXPECT_EQ(GetX86Microarchitecture(&info), X86Microarchitecture::INTEL_ATOM_TMT); +} + +// https://github.com/InstLatx64/InstLatx64/blob/master/GenuineIntel/GenuineIntel0090661_ElkhartLake_CPUID01.txt +TEST_F(CpuidX86Test, INTEL_ATOM_TMT_ELKHART_LAKE) { + cpu().SetLeaves({ + {{0x00000000, 0}, Leaf{0x0000001B, 0x756E6547, 0x6C65746E, 0x49656E69}}, + {{0x00000001, 0}, Leaf{0x00090661, 0x00800800, 0x4FF8EBBF, 0xBFEBFBFF}}, + }); + const auto info = GetX86Info(); + + EXPECT_STREQ(info.vendor, "GenuineIntel"); + EXPECT_EQ(info.family, 0x06); + EXPECT_EQ(info.model, 0x96); + EXPECT_EQ(GetX86Microarchitecture(&info), X86Microarchitecture::INTEL_ATOM_TMT); +} + // http://users.atw.hu/instlatx64/GenuineIntel/GenuineIntel00306F2_HaswellEP2_CPUID.txt TEST_F(CpuidX86Test, INTEL_HASWELL_LZCNT) { cpu().SetLeaves({ |