diff options
| author | William Tambellini <wtambellini@sdl.com> | 2022-09-19 11:00:01 +0300 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2022-09-19 11:00:01 +0300 |
| commit | b69591add3c7b78e84895de0cdd1a7525fb74574 (patch) | |
| tree | 25735cc07c175e1b30da8635e41854d6e7111417 | |
| parent | cee2648cf0cebfb5e0106a2187d4b1c33851a9ec (diff) | |
Add support for detecting Intel CascadeLake CPUs (#271)
Should close
https://github.com/google/cpu_features/issues/260
| -rw-r--r-- | include/cpuinfo_x86.h | 1 | ||||
| -rw-r--r-- | src/impl_x86__base_implementation.inl | 8 | ||||
| -rw-r--r-- | test/cpuinfo_x86_test.cc | 28 |
3 files changed, 36 insertions, 1 deletions
diff --git a/include/cpuinfo_x86.h b/include/cpuinfo_x86.h index 108c9b1..49704df 100644 --- a/include/cpuinfo_x86.h +++ b/include/cpuinfo_x86.h @@ -139,6 +139,7 @@ typedef enum { INTEL_HSW, // HASWELL INTEL_BDW, // BROADWELL INTEL_SKL, // SKYLAKE + INTEL_CCL, // CASCADELAKE INTEL_ATOM_GMT, // GOLDMONT INTEL_ATOM_GMT_PLUS, // GOLDMONT+ INTEL_ATOM_TMT, // TREMONT diff --git a/src/impl_x86__base_implementation.inl b/src/impl_x86__base_implementation.inl index c34d2cf..5b50e88 100644 --- a/src/impl_x86__base_implementation.inl +++ b/src/impl_x86__base_implementation.inl @@ -514,10 +514,15 @@ X86Microarchitecture GetX86Microarchitecture(const X86Info* info) { // https://en.wikipedia.org/wiki/Broadwell_(microarchitecture) return INTEL_BDW; case CPUID(0x06, 0x4E): - case CPUID(0x06, 0x55): case CPUID(0x06, 0x5E): // https://en.wikipedia.org/wiki/Skylake_(microarchitecture) return INTEL_SKL; + case CPUID(0x06, 0x55): + if (info->stepping >= 6 && info->stepping <= 7) { + // https://en.wikipedia.org/wiki/Cascade_Lake_(microprocessor) + return INTEL_CCL; + } + return INTEL_SKL; case CPUID(0x06, 0x66): // https://en.wikipedia.org/wiki/Cannon_Lake_(microarchitecture) return INTEL_CNL; @@ -1911,6 +1916,7 @@ CacheInfo GetX86CacheInfo(void) { LINE(INTEL_HSW) \ LINE(INTEL_BDW) \ LINE(INTEL_SKL) \ + LINE(INTEL_CCL) \ LINE(INTEL_ATOM_GMT) \ LINE(INTEL_ATOM_GMT_PLUS) \ LINE(INTEL_ATOM_TMT) \ diff --git a/test/cpuinfo_x86_test.cc b/test/cpuinfo_x86_test.cc index 7049ef7..9cfde94 100644 --- a/test/cpuinfo_x86_test.cc +++ b/test/cpuinfo_x86_test.cc @@ -219,6 +219,34 @@ TEST_F(CpuidX86Test, SkyLake) { EXPECT_EQ(GetX86Microarchitecture(&info), X86Microarchitecture::INTEL_SKL); } +// http://users.atw.hu/instlatx64/GenuineIntel/GenuineIntel0050654_SkylakeXeon_CPUID8.txt +TEST_F(CpuidX86Test, SkyLakeXeon) { + cpu().SetLeaves({ + {{0x00000000, 0}, Leaf{0x00000016, 0x756E6547, 0x6C65746E, 0x49656E69}}, + {{0x00000001, 0}, Leaf{0x00050654, 0x00100800, 0x7FFEFBFF, 0xBFEBFBFF}} + }); + const auto info = GetX86Info(); + EXPECT_STREQ(info.vendor, CPU_FEATURES_VENDOR_GENUINE_INTEL); + EXPECT_EQ(info.family, 0x06); + EXPECT_EQ(info.model, 0x055); + EXPECT_EQ(info.stepping, 0x04); + EXPECT_EQ(GetX86Microarchitecture(&info), X86Microarchitecture::INTEL_SKL); +} + +// http://users.atw.hu/instlatx64/GenuineIntel/GenuineIntel0050657_CascadeLakeXeon_CPUID.txt +TEST_F(CpuidX86Test, CascadeLake) { + cpu().SetLeaves({ + {{0x00000000, 0}, Leaf{0x00000016, 0x756E6547, 0x6C65746E, 0x49656E69}}, + {{0x00000001, 0}, Leaf{0x00050657, 0x00400800, 0x7FFEFBFF, 0xBFEBFBFF}} + }); + const auto info = GetX86Info(); + EXPECT_STREQ(info.vendor, CPU_FEATURES_VENDOR_GENUINE_INTEL); + EXPECT_EQ(info.family, 0x06); + EXPECT_EQ(info.model, 0x055); + EXPECT_EQ(info.stepping, 0x07); + EXPECT_EQ(GetX86Microarchitecture(&info), X86Microarchitecture::INTEL_CCL); +} + TEST_F(CpuidX86Test, Branding) { cpu().SetLeaves({ {{0x00000000, 0}, Leaf{0x00000016, 0x756E6547, 0x6C65746E, 0x49656E69}}, |