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authorMykola Hohsadze <Mykola_Hohsadze@epam.com>2022-08-18 11:39:00 +0300
committerGitHub <noreply@github.com>2022-08-18 11:39:00 +0300
commitcd97c7cee78b40fc520675705603e7b156a1afb4 (patch)
tree30bb431e7c57f9127b664bbeb2b01c514fb68d15
parent4e8d2e3a22b95b917b1aecb921611ebd70e0184c (diff)
Get rid repeated branch (#269)
* Get rid repeated branch * Update cache type field comment
-rw-r--r--src/impl_x86__base_implementation.inl10
1 files changed, 6 insertions, 4 deletions
diff --git a/src/impl_x86__base_implementation.inl b/src/impl_x86__base_implementation.inl
index cabb867..64ea068 100644
--- a/src/impl_x86__base_implementation.inl
+++ b/src/impl_x86__base_implementation.inl
@@ -1656,16 +1656,18 @@ static void ParseCacheInfo(const int max_cpuid_leaf, uint32_t leaf_id,
const Leaf leaf = SafeCpuIdEx(max_cpuid_leaf, leaf_id, index);
int cache_type_field = ExtractBitRange(leaf.eax, 4, 0);
CacheType cache_type;
- if (cache_type_field == 0)
- break;
- else if (cache_type_field == 1)
+ if (cache_type_field == 1)
cache_type = CPU_FEATURE_CACHE_DATA;
else if (cache_type_field == 2)
cache_type = CPU_FEATURE_CACHE_INSTRUCTION;
else if (cache_type_field == 3)
cache_type = CPU_FEATURE_CACHE_UNIFIED;
else
- break; // Should not occur as per documentation.
+ // Intel Processor Identification and the CPUID Instruction Application
+ // Note 485 page 37 Table 5-10. Deterministic Cache Parameters.
+ // We skip cache parsing in case null of cache type or cache type in the
+ // range of 4-31 according to documentation.
+ break;
int level = ExtractBitRange(leaf.eax, 7, 5);
int line_size = ExtractBitRange(leaf.ebx, 11, 0) + 1;
int partitioning = ExtractBitRange(leaf.ebx, 21, 12) + 1;