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| author | Mykola Hohsadze <Mykola_Hohsadze@epam.com> | 2022-11-08 17:35:50 +0300 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2022-11-08 17:35:50 +0300 |
| commit | 19799486d2e5d88cee7f32913627adebb341a10c (patch) | |
| tree | ba1209efb77a94aaa1a08cb248ee694c8d256b4c /src | |
| parent | b7bc447203256fce26e6140372ea955affd4849e (diff) | |
Add Intel Raptor Lake uarch detection (#283)
Diffstat (limited to 'src')
| -rw-r--r-- | src/impl_x86__base_implementation.inl | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/impl_x86__base_implementation.inl b/src/impl_x86__base_implementation.inl index fefbc6b..88e5a49 100644 --- a/src/impl_x86__base_implementation.inl +++ b/src/impl_x86__base_implementation.inl @@ -581,6 +581,9 @@ X86Microarchitecture GetX86Microarchitecture(const X86Info* info) { case CPUID(0x06, 0xA7): // https://en.wikichip.org/wiki/intel/microarchitectures/rocket_lake return INTEL_RCL; + case CPUID(0x06, 0xB7): + // https://en.wikichip.org/wiki/intel/microarchitectures/raptor_lake + return INTEL_RPL; case CPUID(0x06, 0x85): // https://en.wikichip.org/wiki/intel/microarchitectures/knights_mill return INTEL_KNIGHTS_M; @@ -1948,6 +1951,7 @@ CacheInfo GetX86CacheInfo(void) { LINE(INTEL_SPR) \ LINE(INTEL_ADL) \ LINE(INTEL_RCL) \ + LINE(INTEL_RPL) \ LINE(INTEL_KNIGHTS_M) \ LINE(INTEL_KNIGHTS_L) \ LINE(INTEL_KNIGHTS_F) \ |