diff options
| author | Jeff Hammond <jeff.science@gmail.com> | 2020-09-21 10:56:26 +0300 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-09-21 10:56:26 +0300 |
| commit | 33bd72c1bcf080e8d9cf48403e0ebcbb8bf5ab5a (patch) | |
| tree | 228a771a854e7e0082af66cc4c465d3b08a8e37b /test | |
| parent | e698327713fe9b24c8cb8901c8c2560a916c7b8e (diff) | |
detect future Intel AVX/AMX features (#124)
* add Ice Lake Server and Sapphire Rapids models
The information contained in this commit was obtained from
"Intel® Architecture Instruction Set Extensions and Future Features Programming Reference" document 319433-040 from
https://software.intel.com/content/www/us/en/develop/download/intel-architecture-instruction-set-extensions-programming-reference.html
Signed-off-by: Jeff Hammond <jeff.r.hammond@intel.com>
* Tiger Lake; Ice Lake NNP-I; SPR string
Signed-off-by: Hammond, Jeff R <jeff.r.hammond@intel.com>
* add AVX512_BF16 and AVX512_VP2INTERSECT detection
Signed-off-by: Hammond, Jeff R <jeff.r.hammond@intel.com>
* correction for KNM features: s/4VBMI2/4FMAPS/g
Signed-off-by: Hammond, Jeff R <jeff.r.hammond@intel.com>
* add AMX/TMUL bits from 319433-040
Signed-off-by: Hammond, Jeff R <jeff.r.hammond@intel.com>
* add Intel copyright
Fixes #128
Diffstat (limited to 'test')
| -rw-r--r-- | test/cpuinfo_x86_test.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/test/cpuinfo_x86_test.cc b/test/cpuinfo_x86_test.cc index 10b9624..3c80eee 100644 --- a/test/cpuinfo_x86_test.cc +++ b/test/cpuinfo_x86_test.cc @@ -88,7 +88,7 @@ TEST(CpuidX86Test, SandyBridge) { EXPECT_FALSE(features.avx512bitalg); EXPECT_FALSE(features.avx512vpopcntdq); EXPECT_FALSE(features.avx512_4vnniw); - EXPECT_FALSE(features.avx512_4vbmi2); + EXPECT_FALSE(features.avx512_4fmaps); // All old cpu features should be set. EXPECT_TRUE(features.aes); EXPECT_TRUE(features.ssse3); |