diff options
| author | Andre Przywara <osp@andrep.de> | 2020-01-01 21:49:49 +0300 |
|---|---|---|
| committer | Andre Przywara <osp@andrep.de> | 2020-11-10 13:58:57 +0300 |
| commit | 205e208a70cf6fac22ed12e8f233b6df68ae76c7 (patch) | |
| tree | d10cffb6650f870ee19138d322e6d7d8d91431db /fel-spiflash.c | |
| parent | de784a7c7b00b6a1bbf9f5267c74e825f6f91365 (diff) | |
spi: Observe proper clock initialisation order
The CCU section in all Allwinner manuals asks to de-assert the reset
signal first, then to ungate the bus clock.
On a nearby note it also requires to switch dividers before changing the
clock source.
The SPI flash code violated those two rules, fix this to make the code
more robust.
Signed-off-by: Andre Przywara <osp@andrep.de>
Diffstat (limited to 'fel-spiflash.c')
| -rw-r--r-- | fel-spiflash.c | 14 |
1 files changed, 5 insertions, 9 deletions
diff --git a/fel-spiflash.c b/fel-spiflash.c index 6a556e4..4e22f60 100644 --- a/fel-spiflash.c +++ b/fel-spiflash.c @@ -245,14 +245,7 @@ static bool spi0_init(feldev_handle *dev) reg_val = readl(H6_CCM_SPI_BGR); reg_val |= H6_CCM_SPI0_GATE_RESET; writel(reg_val, H6_CCM_SPI_BGR); - - /* 24MHz from OSC24M */ - writel((1 << 31), H6_CCM_SPI0_CLK); } else { - reg_val = readl(CCM_AHB_GATING0); - reg_val |= CCM_AHB_GATE_SPI0; - writel(reg_val, CCM_AHB_GATING0); - if (spi_is_sun6i(dev)) { /* Deassert SPI0 reset */ reg_val = readl(SUN6I_BUS_SOFT_RST_REG0); @@ -260,13 +253,16 @@ static bool spi0_init(feldev_handle *dev) writel(reg_val, SUN6I_BUS_SOFT_RST_REG0); } - /* 24MHz from OSC24M */ - writel((1 << 31), CCM_SPI0_CLK); + reg_val = readl(CCM_AHB_GATING0); + reg_val |= CCM_AHB_GATE_SPI0; + writel(reg_val, CCM_AHB_GATING0); } /* divide by 4 */ writel(CCM_SPI0_CLK_DIV_BY_4, spi_is_sun6i(dev) ? SUN6I_SPI0_CCTL : SUN4I_SPI0_CCTL); + /* Choose 24MHz from OSC24M and enable clock */ + writel(1U << 31, soc_is_h6_style(dev) ? H6_CCM_SPI0_CLK : CCM_SPI0_CLK); if (spi_is_sun6i(dev)) { /* Enable SPI in the master mode and do a soft reset */ |