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| author | Icenowy Zheng <icenowy@aosc.io> | 2020-09-20 02:38:52 +0300 |
|---|---|---|
| committer | Icenowy Zheng <icenowy@aosc.io> | 2020-09-20 02:41:10 +0300 |
| commit | b330eeb844b0764191048c0cbd6556db467603ae (patch) | |
| tree | 5de50cf939ee97a740ef3afa874bedc20c093d0a /fel-spiflash.c | |
| parent | 613e4bae5c00a3d7a8c21341b61fe45b4b522cf5 (diff) | |
spi: add support for V3s SoC
The Allwinner V3s SoC have the same SPI0 pinmux configuration, SPI clock
configuration and SPI controller (base address and the controller) with
H3.
Add spiflash support for it.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Diffstat (limited to 'fel-spiflash.c')
| -rw-r--r-- | fel-spiflash.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/fel-spiflash.c b/fel-spiflash.c index 612c9a5..5de66fb 100644 --- a/fel-spiflash.c +++ b/fel-spiflash.c @@ -154,6 +154,7 @@ static bool spi0_init(feldev_handle *dev) switch (soc_info->soc_id) { case 0x1625: /* Allwinner A13 */ case 0x1680: /* Allwinner H3 */ + case 0x1681: /* Allwinner V3s */ case 0x1718: /* Allwinner H5 */ gpio_set_cfgpin(dev, PC, 0, SUNXI_GPC_SPI0); gpio_set_cfgpin(dev, PC, 1, SUNXI_GPC_SPI0); |