diff options
author | Icenowy Zheng <icenowy@aosc.io> | 2017-12-22 10:42:16 +0300 |
---|---|---|
committer | Andre Przywara <osp@andrep.de> | 2018-07-09 11:16:24 +0300 |
commit | 4acf2a922ffd918c0e20da5b55bc401bd986f9d2 (patch) | |
tree | f8435ffa0d01a884df55bb43461e3c80e130251b /uart0-helloworld-sdboot.c | |
parent | ed54b135c1968d8b9a9bf2edfa9b0b28d34bb92f (diff) |
uart0-helloworld-sdboot: allow flexible GPIO/UART0 base address
Allwinner A80 and H6 SoC has totally different memory map with other
Allwinner SoCs, and so the GPIO/UART0 base addresses are different on
these SoCs.
Use a static variable to store the base address, to fit these SoCs with
different memory map.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Andre Przywara <osp@andrep.de>
Diffstat (limited to 'uart0-helloworld-sdboot.c')
-rw-r--r-- | uart0-helloworld-sdboot.c | 37 |
1 files changed, 24 insertions, 13 deletions
diff --git a/uart0-helloworld-sdboot.c b/uart0-helloworld-sdboot.c index 6d736ac..875e139 100644 --- a/uart0-helloworld-sdboot.c +++ b/uart0-helloworld-sdboot.c @@ -148,6 +148,8 @@ enum sunxi_gpio_number { #define SUNXI_GPIO_PULL_UP (1) #define SUNXI_GPIO_PULL_DOWN (2) +static u32 pio_base; + int sunxi_gpio_set_cfgpin(u32 pin, u32 val) { u32 cfg; @@ -155,7 +157,7 @@ int sunxi_gpio_set_cfgpin(u32 pin, u32 val) u32 index = GPIO_CFG_INDEX(pin); u32 offset = GPIO_CFG_OFFSET(pin); struct sunxi_gpio *pio = - &((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[bank]; + &((struct sunxi_gpio_reg *)pio_base)->gpio_bank[bank]; cfg = readl(&pio->cfg[0] + index); cfg &= ~(0xf << offset); cfg |= val << offset; @@ -170,7 +172,7 @@ int sunxi_gpio_set_pull(u32 pin, u32 val) u32 index = GPIO_PULL_INDEX(pin); u32 offset = GPIO_PULL_OFFSET(pin); struct sunxi_gpio *pio = - &((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[bank]; + &((struct sunxi_gpio_reg *)pio_base)->gpio_bank[bank]; cfg = readl(&pio->pull[0] + index); cfg &= ~(0x3 << offset); cfg |= val << offset; @@ -184,7 +186,7 @@ int sunxi_gpio_output(u32 pin, u32 val) u32 bank = GPIO_BANK(pin); u32 num = GPIO_NUM(pin); struct sunxi_gpio *pio = - &((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[bank]; + &((struct sunxi_gpio_reg *)pio_base)->gpio_bank[bank]; dat = readl(&pio->dat); if(val) dat |= 1 << num; @@ -200,7 +202,7 @@ int sunxi_gpio_input(u32 pin) u32 bank = GPIO_BANK(pin); u32 num = GPIO_NUM(pin); struct sunxi_gpio *pio = - &((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[bank]; + &((struct sunxi_gpio_reg *)pio_base)->gpio_bank[bank]; dat = readl(&pio->dat); dat >>= num; return (dat & 0x1); @@ -394,19 +396,21 @@ void gpio_init(void) /*****************************************************************************/ -#define UART0_RBR (SUNXI_UART0_BASE + 0x0) /* receive buffer register */ -#define UART0_THR (SUNXI_UART0_BASE + 0x0) /* transmit holding register */ -#define UART0_DLL (SUNXI_UART0_BASE + 0x0) /* divisor latch low register */ +static u32 uart0_base; + +#define UART0_RBR (uart0_base + 0x0) /* receive buffer register */ +#define UART0_THR (uart0_base + 0x0) /* transmit holding register */ +#define UART0_DLL (uart0_base + 0x0) /* divisor latch low register */ -#define UART0_DLH (SUNXI_UART0_BASE + 0x4) /* divisor latch high register */ -#define UART0_IER (SUNXI_UART0_BASE + 0x4) /* interrupt enable reigster */ +#define UART0_DLH (uart0_base + 0x4) /* divisor latch high register */ +#define UART0_IER (uart0_base + 0x4) /* interrupt enable reigster */ -#define UART0_IIR (SUNXI_UART0_BASE + 0x8) /* interrupt identity register */ -#define UART0_FCR (SUNXI_UART0_BASE + 0x8) /* fifo control register */ +#define UART0_IIR (uart0_base + 0x8) /* interrupt identity register */ +#define UART0_FCR (uart0_base + 0x8) /* fifo control register */ -#define UART0_LCR (SUNXI_UART0_BASE + 0xc) /* line control register */ +#define UART0_LCR (uart0_base + 0xc) /* line control register */ -#define UART0_LSR (SUNXI_UART0_BASE + 0x14) /* line status register */ +#define UART0_LSR (uart0_base + 0x14) /* line status register */ #define BAUD_115200 (0xD) /* 24 * 1000 * 1000 / 16 / 115200 = 13 */ #define NO_PARITY (0) @@ -474,9 +478,16 @@ int get_boot_device(void) return BOOT_DEVICE_UNK; } +void bases_init(void) +{ + pio_base = SUNXI_PIO_BASE; + uart0_base = SUNXI_UART0_BASE; +} + int main(void) { soc_detection_init(); + bases_init(); gpio_init(); uart0_init(); |