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author | Tom Stellard <tstellar@redhat.com> | 2017-09-27 21:08:25 +0300 |
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committer | Tom Stellard <tstellar@redhat.com> | 2017-09-27 21:08:25 +0300 |
commit | 7f6d22cdd88f48524954167a7885f35a00006158 (patch) | |
tree | 8d444ef4234fd977cfb1446c8130efab9725430b | |
parent | 14adbd0d8b87e3a160b14dbd78bd4fd748063239 (diff) |
Merging r312337:
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r312337 | nha | 2017-09-01 09:56:32 -0700 (Fri, 01 Sep 2017) | 12 lines
AMDGPU: IMPLICIT_DEFs and DBG_VALUEs do not contribute to wait states
Summary:
This fixes a bug that was exposed on gfx9 in various
GL45-CTS.shaders.loops.*_iterations.select_iteration_count_fragment tests,
e.g. GL45-CTS.shaders.loops.do_while_uniform_iterations.select_iteration_count_fragment
Reviewers: arsenm
Subscribers: kzhuravl, wdng, yaxunl, dstuttard, tpr, t-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D36193
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llvm-svn: 314327
-rw-r--r-- | llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp | 13 | ||||
-rw-r--r-- | llvm/test/CodeGen/AMDGPU/hazard.mir | 31 |
2 files changed, 40 insertions, 4 deletions
diff --git a/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp b/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp index cd9e7fb04f16..025397b1eac0 100644 --- a/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp +++ b/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp @@ -218,12 +218,17 @@ void GCNHazardRecognizer::RecedeCycle() { int GCNHazardRecognizer::getWaitStatesSince( function_ref<bool(MachineInstr *)> IsHazard) { - int WaitStates = -1; + int WaitStates = 0; for (MachineInstr *MI : EmittedInstrs) { + if (MI) { + if (IsHazard(MI)) + return WaitStates; + + unsigned Opcode = MI->getOpcode(); + if (Opcode == AMDGPU::DBG_VALUE || Opcode == AMDGPU::IMPLICIT_DEF) + continue; + } ++WaitStates; - if (!MI || !IsHazard(MI)) - continue; - return WaitStates; } return std::numeric_limits<int>::max(); } diff --git a/llvm/test/CodeGen/AMDGPU/hazard.mir b/llvm/test/CodeGen/AMDGPU/hazard.mir new file mode 100644 index 000000000000..d495a327e9e3 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/hazard.mir @@ -0,0 +1,31 @@ +# RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs -run-pass post-RA-hazard-rec %s -o - | FileCheck -check-prefix=GCN -check-prefix=VI %s +# RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs -run-pass post-RA-hazard-rec %s -o - | FileCheck -check-prefix=GCN -check-prefix=GFX9 %s + +# GCN: bb.0.entry: +# GCN: %m0 = S_MOV_B32 +# GFX9: S_NOP 0 +# VI-NOT: S_NOP_0 +# GCN: V_INTERP_P1_F32 + +--- +name: hazard_implicit_def +alignment: 0 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: +liveins: + - { reg: '%sgpr7', virtual-reg: '' } + - { reg: '%vgpr4', virtual-reg: '' } +body: | + bb.0.entry: + liveins: %sgpr7, %vgpr4 + + %m0 = S_MOV_B32 killed %sgpr7 + %vgpr5 = IMPLICIT_DEF + %vgpr0 = V_INTERP_P1_F32 killed %vgpr4, 0, 0, implicit %m0, implicit %exec + SI_RETURN_TO_EPILOG killed %vgpr5, killed %vgpr0 + +... |