diff options
author | Danliran <zhouxion_422@126.com> | 2020-04-28 05:57:07 +0300 |
---|---|---|
committer | GitHub <noreply@github.com> | 2020-04-28 05:57:07 +0300 |
commit | 2b14e445016dd46f7de821cdf3093e2823b9ab21 (patch) | |
tree | 81272e65dc35c35571325e1cc2c01921831393e9 | |
parent | a1e0b9571b51131cf80613d061d2aa123876bd0a (diff) |
Support Huawei Kunpeng920 series CPU info detection, Kunpeng920 Series CPU base on TaiShan v110 microarchitecture. (#39)
TaiShan v110 base on armv8.2a designed by Huawei hisilicon.
-rw-r--r-- | include/cpuinfo.h | 3 | ||||
-rw-r--r-- | src/arm/cache.c | 40 | ||||
-rw-r--r-- | src/arm/uarch.c | 3 |
3 files changed, 46 insertions, 0 deletions
diff --git a/include/cpuinfo.h b/include/cpuinfo.h index e4d2d0c..903d1cf 100644 --- a/include/cpuinfo.h +++ b/include/cpuinfo.h @@ -499,6 +499,9 @@ enum cpuinfo_uarch { /** Applied Micro X-Gene. */ cpuinfo_uarch_xgene = 0x00B00100, + /** Huawei hisilicon Kunpeng Series CPU. */ + cpuinfo_uarch_taishanv110 = 0x00C00100, + /* Hygon Dhyana (a modification of AMD Zen for Chinese market). */ cpuinfo_uarch_dhyana = 0x01000100, }; diff --git a/src/arm/cache.c b/src/arm/cache.c index c2bc7d2..70f11fd 100644 --- a/src/arm/cache.c +++ b/src/arm/cache.c @@ -1448,6 +1448,46 @@ void cpuinfo_arm_decode_cache( .line_size = 64 /* assumption */ }; break; + case cpuinfo_uarch_taishanv110: + /* + * Kunpeng920 series CPU designed by Huawei hisilicon for server, + * L1 and L2 cache is private to each core, L3 is shared with all cores. + * +--------------------+-------+-----------+-----------+-----------+----------+------------+ + * | Processor model | Cores | L1D cache | L1I cache | L2 cache | L3 cache | Reference | + * +--------------------+-------+-----------+-----------+-----------+----------+------------+ + * | Kunpeng920-3226 | 32 | 64K | 64K | 512K | 32M | [1] | + * +--------------------+-------+-----------+-----------+-----------+----------+------------+ + * | Kunpeng920-4826 | 48 | 64K | 64K | 512K | 48M | [2] | + * +--------------------+-------+-----------+-----------+-----------+----------+------------+ + * | Kunpeng920-6426 | 64 | 64K | 64K | 512K | 64M | [3] | + * +--------------------+-------+-----------+-----------+-----------+----------+------------+ + * + * [1] https://en.wikichip.org/wiki/hisilicon/kunpeng/920-3226 + * [2] https://en.wikichip.org/wiki/hisilicon/kunpeng/920-4826 + * [3] https://en.wikichip.org/wiki/hisilicon/kunpeng/920-6426 + */ + *l1i = (struct cpuinfo_cache) { + .size = 64 * 1024, + .associativity = 4 /* assumption */, + .line_size = 128 /* assumption */, + }; + *l1d = (struct cpuinfo_cache) { + .size = 64 * 1024, + .associativity = 4 /* assumption */, + .line_size = 128 /* assumption */, + }; + *l2 = (struct cpuinfo_cache) { + .size = 512 * 1024, + .associativity = 8 /* assumption */, + .line_size = 128 /* assumption */, + .flags = CPUINFO_CACHE_INCLUSIVE /* assumption */, + }; + *l3 = (struct cpuinfo_cache) { + .size = cluster_cores * 1024 * 1024, + .associativity = 16 /* assumption */, + .line_size = 128 /* assumption */, + }; + break; #endif case cpuinfo_uarch_cortex_a12: case cpuinfo_uarch_cortex_a32: diff --git a/src/arm/uarch.c b/src/arm/uarch.c index 2aef9e7..e5e3cbc 100644 --- a/src/arm/uarch.c +++ b/src/arm/uarch.c @@ -155,6 +155,9 @@ void cpuinfo_arm_decode_vendor_uarch( case 'H': *vendor = cpuinfo_vendor_huawei; switch (midr_get_part(midr)) { + case 0xD01: /* Kunpeng920 ARM-base CPU*/ + *uarch = cpuinfo_uarch_taishanv110; + break; case 0xD40: /* Kirin 980 Big/Medium cores -> Cortex-A76 */ *vendor = cpuinfo_vendor_arm; *uarch = cpuinfo_uarch_cortex_a76; |