Upstream cpuinfo updates in XNNPACK as of XNNPACK:d793f6c2ec145be3ddbffea951e6e5480f4646b8.

1 files changed, 5 insertions, 0 deletions

diff --git a/README.md b/README.md
index ee5fb82..97e65cd 100644
--- a/README.md
+++ b/README.md
@@ -49,6 +49,7 @@ Detect if target is a 32-bit or 64-bit ARM system:
 ```
 
 Check if the host CPU support ARM NEON
+
 ```c
 cpuinfo_initialize();
 if (cpuinfo_has_arm_neon()) {
@@ -57,6 +58,7 @@ if (cpuinfo_has_arm_neon()) {
 ```
 
 Check if the host CPU supports x86 AVX
+
 ```c
 cpuinfo_initialize();
 if (cpuinfo_has_x86_avx()) {
@@ -65,6 +67,7 @@ if (cpuinfo_has_x86_avx()) {
 ```
 
 Check if the thread runs on a Cortex-A53 core
+
 ```c
 cpuinfo_initialize();
 switch (cpuinfo_get_current_core()->uarch) {
@@ -78,12 +81,14 @@ switch (cpuinfo_get_current_core()->uarch) {
 ```
 
 Get the size of level 1 data cache on the fastest core in the processor (e.g. big core in big.LITTLE ARM systems):
+
 ```c
 cpuinfo_initialize();
 const size_t l1_size = cpuinfo_get_processor(0)->cache.l1d->size;
 ```
 
 Pin thread to cores sharing L2 cache with the current core (Linux or Android)
+
 ```c
 cpuinfo_initialize();
 cpu_set_t cpu_set;