Huawei Mate 20 mock test

5 files changed, 140 insertions, 28 deletions

diff --git a/src/arm/cache.c b/src/arm/cache.c
index c972a2d..5ada7d9 100644
--- a/src/arm/cache.c
+++ b/src/arm/cache.c
@@ -690,10 +690,12 @@ void cpuinfo_arm_decode_cache(
 			 *  +--------------------+-------+-----------+-----------+-----------+----------+------------+
 			 *  | Snapdragon 845     | 4(+4) |    32K    |    32K    |    128K   |    2M    | [1], sysfs |
 			 *  | Exynos 9810        | 4(+4) |     ?     |     ?     |    None   |   512K   |     [2]    |
+			 *  | Kirin 980          | 4(+4) |    32K    |    32K    |    128K   |    4M    |     [3]    |
 			 *  +--------------------+-------+-----------+-----------+-----------+----------+------------+
 			 *
 			 * [1] https://www.anandtech.com/show/12114/qualcomm-announces-snapdragon-845-soc
 			 * [2] https://www.anandtech.com/show/12478/exynos-9810-handson-awkward-first-results
+			 * [3] https://en.wikichip.org/wiki/hisilicon/kirin/980
 			 */
 			if (midr_is_qualcomm_cortex_a55_silver(midr)) {
 				/* Qualcomm-modified Cortex-A55 in Snapdragon 710 / 845 */
@@ -712,22 +714,22 @@ void cpuinfo_arm_decode_cache(
 				*l1i = (struct cpuinfo_cache) {
 					.size = 32 * 1024,
 					.associativity = 4,
-					.line_size = 64
+					.line_size = 64,
 				};
 				*l1d = (struct cpuinfo_cache) {
 					.size = 32 * 1024,
 					.associativity = 4,
-					.line_size = 64
+					.line_size = 64,
 				};
 				*l2 = (struct cpuinfo_cache) {
 					.size = 128 * 1024,
 					.associativity = 4,
-					.line_size = 64
+					.line_size = 64,
 				};
 				*l3 = (struct cpuinfo_cache) {
 					.size = l3_size,
 					.associativity = 16,
-					.line_size = 64
+					.line_size = 64,
 				};
 			} else {
 				/* Standard Cortex-A55 */
@@ -735,18 +737,44 @@ void cpuinfo_arm_decode_cache(
 				*l1i = (struct cpuinfo_cache) {
 					.size = 32 * 1024,
 					.associativity = 4,
-					.line_size = 64
+					.line_size = 64,
 				};
 				*l1d = (struct cpuinfo_cache) {
 					.size = 32 * 1024,
 					.associativity = 4,
-					.line_size = 64
-				};
-				*l2 = (struct cpuinfo_cache) {
-					.size = 512 * 1024,
-					.associativity = 16,
-					.line_size = 64
+					.line_size = 64,
 				};
+				if (chipset->series == cpuinfo_arm_chipset_series_samsung_exynos) {
+					*l2 = (struct cpuinfo_cache) {
+						.size = 512 * 1024,
+						/* DynamIQ */
+						.associativity = 16,
+						.line_size = 64,
+					};
+				} else {
+					uint32_t l3_size = 1024 * 1024;
+					switch (chipset->series) {
+						case cpuinfo_arm_chipset_series_hisilicon_kirin:
+							/* Kirin 980: 4M L3 cache */
+							if (chipset->model == 980) {
+								l3_size = 4 * 1024 * 1024;
+							}
+							break;
+						default:
+							break;
+					}
+					*l2 = (struct cpuinfo_cache) {
+						.size = 128 * 1024,
+						.associativity = 4,
+						.line_size = 64,
+					};
+					*l3 = (struct cpuinfo_cache) {
+						.size = l3_size,
+						/* DynamIQ */
+						.associativity = 16,
+						.line_size = 64,
+					};
+				}
 			}
 			break;
 		case cpuinfo_uarch_cortex_a57:
@@ -1018,6 +1046,79 @@ void cpuinfo_arm_decode_cache(
 			};
 			break;
 		}
+		case cpuinfo_uarch_cortex_a76:
+		{
+			/*
+			 * ARM Cortex-A76 Core Technical Reference Manual
+			 * A6.1. About the L1 memory system
+			 *   The L1 memory system consists of separate instruction and data caches. Both have a fixed size of 64KB.
+			 *
+			 * A6.1.1 L1 instruction-side memory system
+			 *   The L1 instruction memory system has the following key features:
+			 *    - Virtually Indexed, Physically Tagged (VIPT), which behaves as a Physically Indexed,
+			 *      Physically Tagged (PIPT) 4-way set-associative L1 data cache.
+			 *    - Fixed cache line length of 64 bytes.
+			 *
+			 * A6.1.2 L1 data-side memory system
+			 *   The L1 data memory system has the following features:
+			 *    - Virtually Indexed, Physically Tagged (VIPT), which behaves as a Physically Indexed,
+			 *      Physically Tagged (PIPT) 4-way set-associative L1 data cache.
+			 *    - Fixed cache line length of 64 bytes.
+			 *    - Pseudo-LRU cache replacement policy.
+			 *
+			 * A7.1 About the L2 memory system
+			 *   The L2 memory subsystem consist of:
+			 *    - An 8-way set associative L2 cache with a configurable size of 128KB, 256KB or 512KB.
+			 *      Cache lines have a fixed length of 64 bytes.
+			 *    - Strictly inclusive with L1 data cache. Weakly inclusive with L1 instruction cache.
+			 *    - Dynamic biased replacement policy.
+			 *    - Modified Exclusive Shared Invalid (MESI) coherency.
+			 *
+			 *  +--------------------+-------+-----------+-----------+-----------+----------+------------+
+			 *  | Processor model    | Cores | L1D cache | L1I cache | L2 cache  | L3 cache | Reference  |
+			 *  +--------------------+-------+-----------+-----------+-----------+----------+------------+
+			 *  | Kirin 980          | 4(+4) |    64K    |    64K    |    512K   |    4M    |  [1], [2]  |
+			 *  +--------------------+-------+-----------+-----------+-----------+----------+------------+
+			 *
+			 * [1] https://www.anandtech.com/show/13298/hisilicon-announces-the-kirin-980-first-a76-g76-on-7nm
+			 * [2] https://en.wikichip.org/wiki/hisilicon/kirin/980
+			 */
+			uint32_t l2_size = 256 * 1024;
+			uint32_t l3_size = 1024 * 1024;
+			switch (chipset->series) {
+				case cpuinfo_arm_chipset_series_hisilicon_kirin:
+					/* Kirin 980: 512K L2 cache + 4M L3 cache */
+					if (chipset->model == 980) {
+						l2_size = 512 * 1024;
+						l3_size = 4 * 1024 * 1024;
+					}
+					break;
+				default:
+					break;
+			}
+			*l1i = (struct cpuinfo_cache) {
+				.size = 64 * 1024,
+				.associativity = 4,
+				.line_size = 64,
+			};
+			*l1d = (struct cpuinfo_cache) {
+				.size = 64 * 1024,
+				.associativity = 4,
+				.line_size = 64,
+			};
+			*l2 = (struct cpuinfo_cache) {
+				.size = l2_size,
+				.associativity = 8,
+				.line_size = 64,
+				.flags = CPUINFO_CACHE_INCLUSIVE,
+			};
+			*l3 = (struct cpuinfo_cache) {
+				.size = l3_size,
+				.associativity = 16,
+				.line_size = 64,
+			};
+			break;
+		}
 #if CPUINFO_ARCH_ARM && !defined(__ARM_ARCH_8A__)
 		case cpuinfo_uarch_scorpion:
 			/*
diff --git a/src/arm/linux/aarch32-isa.c b/src/arm/linux/aarch32-isa.c
index 1a6d8a4..d552ca2 100644
--- a/src/arm/linux/aarch32-isa.c
+++ b/src/arm/linux/aarch32-isa.c
@@ -30,6 +30,7 @@ void cpuinfo_arm_linux_decode_isa_from_proc_cpuinfo(
 	uint32_t midr,
 	uint32_t architecture_version,
 	uint32_t architecture_flags,
+	const struct cpuinfo_arm_chipset chipset[restrict static 1],
 	struct cpuinfo_arm_isa isa[restrict static 1])
 {
 	if (architecture_version >= 8) {
@@ -52,29 +53,26 @@ void cpuinfo_arm_linux_decode_isa_from_proc_cpuinfo(
 		isa->neon = true;
 
 		/*
-		 * NEON FP16 compute extension is not indicated in /proc/cpuinfo.
+		 * NEON FP16 compute extension and VQRDMLAH/VQRDMLSH instructions are not indicated in /proc/cpuinfo.
 		 * Use a MIDR-based heuristic to whitelist processors known to support it:
-		 * - Processors with Qualcomm-modified Cortex-A75 and Cortex-A55 cores
+		 * - Processors with Qualcomm-modified Cortex-A55 cores
+		 * - Processors with Qualcomm-modified Cortex-A75 cores
+		 * - Processors with Qualcomm-modified Cortex-A76 cores
+		 * - Kirin 980 processor
 		 */
 		switch (midr & (CPUINFO_ARM_MIDR_IMPLEMENTER_MASK | CPUINFO_ARM_MIDR_PART_MASK)) {
 			case UINT32_C(0x51008020): /* Kryo 385 Gold (Cortex-A75) */
 			case UINT32_C(0x51008030): /* Kryo 385 Silver (Cortex-A55) */
-			case UINT32_C(0x51008040): /* Qualcomm Cortex-A76 */
+			case UINT32_C(0x51008040): /* Kryo 485 Gold (Cortex-A76) */
 				isa->fp16arith = true;
-				break;
-		}
-
-		/*
-		 * NEON VQRDMLAH/VQRDMLSH instructions are not indicated in /proc/cpuinfo.
-		 * Use a MIDR-based heuristic to whitelist processors known to support it:
-		 * - Processors with Qualcomm-modified Cortex-A75 and Cortex-A55 cores
-		 */
-		switch (midr & (CPUINFO_ARM_MIDR_IMPLEMENTER_MASK | CPUINFO_ARM_MIDR_PART_MASK)) {
-			case UINT32_C(0x51008020): /* Kryo 385 Gold (Cortex-A75) */
-			case UINT32_C(0x51008030): /* Kryo 385 Silver (Cortex-A55) */
-			case UINT32_C(0x51008040): /* Qualcomm Cortex-A76 */
 				isa->rdm = true;
 				break;
+			default:
+				if (chipset->series == cpuinfo_arm_chipset_series_hisilicon_kirin && chipset->model == 980) {
+					isa->fp16arith = true;
+					isa->rdm = true;
+				}
+				break;
 		}
 	} else {
 		/* ARMv7 or lower: use feature flags to detect optional features */
diff --git a/src/arm/linux/aarch64-isa.c b/src/arm/linux/aarch64-isa.c
index 697a047..462aee5 100644
--- a/src/arm/linux/aarch64-isa.c
+++ b/src/arm/linux/aarch64-isa.c
@@ -41,16 +41,28 @@ void cpuinfo_arm64_linux_decode_isa_from_proc_cpuinfo(
 	} else if (features & CPUINFO_ARM_LINUX_FEATURE_ASIMDHP) {
 		cpuinfo_log_warning("FP16 arithmetics disabled: detected support only for SIMD operations");
 	}
-	/* Qualcomm Kryo 385 may have buggy kernel configuration that doesn't report VQRDMLAH/VQRDMLSH instructions */
+	/*
+	 * Many phones ship with an old kernel configuration that doesn't report
+	 * SQRDMLAH/SQRDMLSH/UQRDMLAH/UQRDMLSH instructions.
+	 * Use a MIDR-based heuristic to whitelist processors known to support it:
+	 * - Processors with Qualcomm-modified Cortex-A55 cores
+	 * - Processors with Qualcomm-modified Cortex-A75 cores
+	 * - Processors with Qualcomm-modified Cortex-A76 cores
+	 * - Kirin 980 processor
+	 */
 	switch (midr & (CPUINFO_ARM_MIDR_IMPLEMENTER_MASK | CPUINFO_ARM_MIDR_PART_MASK)) {
 		case UINT32_C(0x51008020): /* Kryo 385 Gold (Cortex-A75) */
 		case UINT32_C(0x51008030): /* Kryo 385 Silver (Cortex-A55) */
+		case UINT32_C(0x51008040): /* Kryo 485 Gold (Cortex-A76) */
 			isa->rdm = true;
 			break;
 		default:
 			if (features & CPUINFO_ARM_LINUX_FEATURE_ASIMDRDM) {
 				isa->rdm = true;
 			}
+			if (chipset->series == cpuinfo_arm_chipset_series_hisilicon_kirin && chipset->model == 980) {
+				isa->rdm = true;
+			}
 			break;
 	}
 	if (features & CPUINFO_ARM_LINUX_FEATURE_JSCVT) {
diff --git a/src/arm/linux/api.h b/src/arm/linux/api.h
index 36e3200..73d56df 100644
--- a/src/arm/linux/api.h
+++ b/src/arm/linux/api.h
@@ -261,6 +261,7 @@ CPUINFO_INTERNAL bool cpuinfo_arm_linux_parse_proc_cpuinfo(
 		uint32_t midr,
 		uint32_t architecture_version,
 		uint32_t architecture_flags,
+		const struct cpuinfo_arm_chipset chipset[restrict static 1],
 		struct cpuinfo_arm_isa isa[restrict static 1]);
 #elif CPUINFO_ARCH_ARM64
 	CPUINFO_INTERNAL uint32_t cpuinfo_arm_linux_hwcap_from_getauxval(void);
diff --git a/src/arm/linux/init.c b/src/arm/linux/init.c
index 23dc762..a297f63 100644
--- a/src/arm/linux/init.c
+++ b/src/arm/linux/init.c
@@ -273,7 +273,7 @@ void cpuinfo_arm_linux_init(void) {
 		cpuinfo_arm_linux_decode_isa_from_proc_cpuinfo(
 			isa_features, isa_features2,
 			last_midr, last_architecture_version, last_architecture_flags,
-			&cpuinfo_isa);
+			&chipset, &cpuinfo_isa);
 	#elif CPUINFO_ARCH_ARM64
 		/* getauxval is always available on ARM64 Android */
 		const uint32_t isa_features = cpuinfo_arm_linux_hwcap_from_getauxval();