diff options
| author | Miguel Sánchez de León Peque <peque@neosit.es> | 2019-04-09 01:46:15 +0300 |
|---|---|---|
| committer | Karl Palsson <karlp@tweak.net.au> | 2019-06-02 13:39:18 +0300 |
| commit | 1d68c299e8804d47f407a2f9f3c1274d3c892273 (patch) | |
| tree | fe664b60215436a2264e7fb48de8c98f17e185d3 | |
| parent | ca6dcfbea137bd2145b4a7fbf24379f565f8280d (diff) | |
stm32f4: add HSI clock configurations
| -rw-r--r-- | include/libopencm3/stm32/f4/rcc.h | 1 | ||||
| -rw-r--r-- | lib/stm32/f4/rcc.c | 88 |
2 files changed, 89 insertions, 0 deletions
diff --git a/include/libopencm3/stm32/f4/rcc.h b/include/libopencm3/stm32/f4/rcc.h index ff6b1c48..e6d660f1 100644 --- a/include/libopencm3/stm32/f4/rcc.h +++ b/include/libopencm3/stm32/f4/rcc.h @@ -795,6 +795,7 @@ struct rcc_clock_scale { uint32_t apb2_frequency; }; +extern const struct rcc_clock_scale rcc_hsi_configs[RCC_CLOCK_3V3_END]; extern const struct rcc_clock_scale rcc_hse_8mhz_3v3[RCC_CLOCK_3V3_END]; extern const struct rcc_clock_scale rcc_hse_12mhz_3v3[RCC_CLOCK_3V3_END]; extern const struct rcc_clock_scale rcc_hse_16mhz_3v3[RCC_CLOCK_3V3_END]; diff --git a/lib/stm32/f4/rcc.c b/lib/stm32/f4/rcc.c index aecbea69..515693e4 100644 --- a/lib/stm32/f4/rcc.c +++ b/lib/stm32/f4/rcc.c @@ -49,6 +49,94 @@ uint32_t rcc_ahb_frequency = 16000000; uint32_t rcc_apb1_frequency = 16000000; uint32_t rcc_apb2_frequency = 16000000; +const struct rcc_clock_scale rcc_hsi_configs[RCC_CLOCK_3V3_END] = { + { /* 48MHz */ + .pllm = 16, + .plln = 96, + .pllp = 2, + .pllq = 2, + .pllr = 0, + .pll_source = RCC_CFGR_PLLSRC_HSI_CLK, + .hpre = RCC_CFGR_HPRE_DIV_NONE, + .ppre1 = RCC_CFGR_PPRE_DIV_4, + .ppre2 = RCC_CFGR_PPRE_DIV_2, + .voltage_scale = PWR_SCALE1, + .flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN | + FLASH_ACR_LATENCY_1WS, + .ahb_frequency = 48000000, + .apb1_frequency = 12000000, + .apb2_frequency = 24000000, + }, + { /* 84MHz */ + .pllm = 16, + .plln = 336, + .pllp = 4, + .pllq = 7, + .pllr = 0, + .pll_source = RCC_CFGR_PLLSRC_HSI_CLK, + .hpre = RCC_CFGR_HPRE_DIV_NONE, + .ppre1 = RCC_CFGR_PPRE_DIV_2, + .ppre2 = RCC_CFGR_PPRE_DIV_NONE, + .voltage_scale = PWR_SCALE1, + .flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN | + FLASH_ACR_LATENCY_2WS, + .ahb_frequency = 84000000, + .apb1_frequency = 42000000, + .apb2_frequency = 84000000, + }, + { /* 120MHz */ + .pllm = 16, + .plln = 240, + .pllp = 2, + .pllq = 5, + .pllr = 0, + .pll_source = RCC_CFGR_PLLSRC_HSI_CLK, + .hpre = RCC_CFGR_HPRE_DIV_NONE, + .ppre1 = RCC_CFGR_PPRE_DIV_4, + .ppre2 = RCC_CFGR_PPRE_DIV_2, + .voltage_scale = PWR_SCALE1, + .flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN | + FLASH_ACR_LATENCY_3WS, + .ahb_frequency = 120000000, + .apb1_frequency = 30000000, + .apb2_frequency = 60000000, + }, + { /* 168MHz */ + .pllm = 16, + .plln = 336, + .pllp = 2, + .pllq = 7, + .pllr = 0, + .pll_source = RCC_CFGR_PLLSRC_HSI_CLK, + .hpre = RCC_CFGR_HPRE_DIV_NONE, + .ppre1 = RCC_CFGR_PPRE_DIV_4, + .ppre2 = RCC_CFGR_PPRE_DIV_2, + .voltage_scale = PWR_SCALE1, + .flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN | + FLASH_ACR_LATENCY_5WS, + .ahb_frequency = 168000000, + .apb1_frequency = 42000000, + .apb2_frequency = 84000000, + }, + { /* 180MHz */ + .pllm = 16, + .plln = 360, + .pllp = 2, + .pllq = 8, + .pllr = 0, + .pll_source = RCC_CFGR_PLLSRC_HSI_CLK, + .hpre = RCC_CFGR_HPRE_DIV_NONE, + .ppre1 = RCC_CFGR_PPRE_DIV_4, + .ppre2 = RCC_CFGR_PPRE_DIV_2, + .voltage_scale = PWR_SCALE1, + .flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN | + FLASH_ACR_LATENCY_5WS, + .ahb_frequency = 180000000, + .apb1_frequency = 45000000, + .apb2_frequency = 90000000, + }, +}; + const struct rcc_clock_scale rcc_hse_8mhz_3v3[RCC_CLOCK_3V3_END] = { { /* 48MHz */ .pllm = 8, |