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| author | Karl Palsson <karlp@etactica.com> | 2019-06-26 15:31:25 +0300 |
|---|---|---|
| committer | Karl Palsson <karlp@etactica.com> | 2019-06-27 17:53:09 +0300 |
| commit | 38d88c6113f2098b79b2fca1e671863260335779 (patch) | |
| tree | a504bb8772d765d38a51196237341ce8306da092 | |
| parent | 06ee2009e812805ac828b7f2cbe31e00cee1cafb (diff) | |
doc: stm32f0: rcc: add missing groups for pll factors and sources
| -rw-r--r-- | include/libopencm3/stm32/f0/rcc.h | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/include/libopencm3/stm32/f0/rcc.h b/include/libopencm3/stm32/f0/rcc.h index 82e03eb1..3bd4f58f 100644 --- a/include/libopencm3/stm32/f0/rcc.h +++ b/include/libopencm3/stm32/f0/rcc.h @@ -108,6 +108,9 @@ Control</b> #define RCC_CFGR_PLLMUL_SHIFT 18 #define RCC_CFGR_PLLMUL (0x0F << RCC_CFGR_PLLMUL_SHIFT) +/** @defgroup rcc_cfgr_pmf PLLMUL: PLL multiplication factor + * @{ + */ #define RCC_CFGR_PLLMUL_MUL2 (0x00 << RCC_CFGR_PLLMUL_SHIFT) #define RCC_CFGR_PLLMUL_MUL3 (0x01 << RCC_CFGR_PLLMUL_SHIFT) #define RCC_CFGR_PLLMUL_MUL4 (0x02 << RCC_CFGR_PLLMUL_SHIFT) @@ -123,14 +126,23 @@ Control</b> #define RCC_CFGR_PLLMUL_MUL14 (0x0C << RCC_CFGR_PLLMUL_SHIFT) #define RCC_CFGR_PLLMUL_MUL15 (0x0D << RCC_CFGR_PLLMUL_SHIFT) #define RCC_CFGR_PLLMUL_MUL16 (0x0E << RCC_CFGR_PLLMUL_SHIFT) +/**@}*/ #define RCC_CFGR_PLLXTPRE (1<<17) +/** @defgroup rcc_cfgr_hsepre PLLXTPRE: HSE divider for PLL source + * @{ + */ #define RCC_CFGR_PLLXTPRE_HSE_CLK 0x0 #define RCC_CFGR_PLLXTPRE_HSE_CLK_DIV2 0x1 +/**@}*/ #define RCC_CFGR_PLLSRC (1<<16) +/** @defgroup rcc_cfgr_pcs PLLSRC: PLL Clock source + * @{ + */ #define RCC_CFGR_PLLSRC_HSI_CLK_DIV2 0x0 #define RCC_CFGR_PLLSRC_HSE_CLK 0x1 +/**@}*/ #define RCC_CFGR_PLLSRC0 (1<<15) #define RCC_CFGR_ADCPRE (1<<14) |