diff options
| author | Karl Palsson <karlp@tweak.net.au> | 2019-06-13 01:24:52 +0300 |
|---|---|---|
| committer | Karl Palsson <karlp@tweak.net.au> | 2019-06-13 01:56:38 +0300 |
| commit | 5ba8d94b81f192156e54ba7073ba092b28653821 (patch) | |
| tree | 26cf2fd5421bea7a56f8c6d9e3ba781165ab7492 | |
| parent | e6e1c239e466cd3774aa95074ebdeb5affe8d0fd (diff) | |
doc: stm32l4: rcc: add groupings for periph resets
As we did with f2, use a parent grouping to contain the different sets
of APB1 fields.
| -rw-r--r-- | include/libopencm3/stm32/l4/rcc.h | 41 |
1 files changed, 30 insertions, 11 deletions
diff --git a/include/libopencm3/stm32/l4/rcc.h b/include/libopencm3/stm32/l4/rcc.h index ad7fe8a1..98ec575e 100644 --- a/include/libopencm3/stm32/l4/rcc.h +++ b/include/libopencm3/stm32/l4/rcc.h @@ -320,16 +320,19 @@ Twelve frequency ranges are available: 100 kHz, 200 kHz, 400 kHz, 800 kHz, #define RCC_CICR_LSERDYC (1 << 1) #define RCC_CICR_LSIRDYC (1 << 0) -/* --- RCC_AHB1RSTR values ------------------------------------------------- */ - +/** @defgroup rcc_ahbrstr_rst RCC_AHBxRSTR reset values (full set) +@{*/ +/** @defgroup rcc_ahb1rstr_rst RCC_AHB1RSTR reset values +@{*/ #define RCC_AHB1RSTR_TSCRST (1 << 16) #define RCC_AHB1RSTR_CRCRST (1 << 12) #define RCC_AHB1RSTR_FLASHRST (1 << 8) #define RCC_AHB1RSTR_DMA2RST (1 << 1) #define RCC_AHB1RSTR_DMA1RST (1 << 0) +/**@}*/ -/* --- RCC_AHB2RSTR values ------------------------------------------------- */ - +/** @defgroup rcc_ahb2rstr_rst RCC_AHB2RSTR reset values +@{*/ #define RCC_AHB2RSTR_RNGRST (1 << 18) #define RCC_AHB2RSTR_AESRST (1 << 16) #define RCC_AHB2RSTR_ADCRST (1 << 13) @@ -343,13 +346,19 @@ Twelve frequency ranges are available: 100 kHz, 200 kHz, 400 kHz, 800 kHz, #define RCC_AHB2RSTR_GPIOBRST (1 << 1) #define RCC_AHB2RSTR_GPIOARST (1 << 0) -/* --- RCC_AHB3RSTR values ------------------------------------------------- */ +/**@}*/ +/** @defgroup rcc_ahb3rstr_rst RCC_AHB3RSTR reset values +@{*/ #define RCC_AHB3RSTR_QSPIRST (1 << 8) #define RCC_AHB3RSTR_FMCRST (1 << 0) +/**@}*/ +/**@}*/ -/* --- RCC_APB1RSTR1 values ------------------------------------------------- */ - +/** @defgroup rcc_apb1rstr_rst RCC_APB1RSTRx reset values (full set) +@{*/ +/** @defgroup rcc_apb1rstr1_rst RCC_APB1RSTR1 reset values +@{*/ #define RCC_APB1RSTR1_LPTIM1RST (1 << 31) #define RCC_APB1RSTR1_OPAMPRST (1 << 30) #define RCC_APB1RSTR1_DAC1RST (1 << 29) @@ -371,15 +380,18 @@ Twelve frequency ranges are available: 100 kHz, 200 kHz, 400 kHz, 800 kHz, #define RCC_APB1RSTR1_TIM4RST (1 << 2) #define RCC_APB1RSTR1_TIM3RST (1 << 1) #define RCC_APB1RSTR1_TIM2RST (1 << 0) +/**@}*/ -/* --- RCC_APB1RSTR2 values ------------------------------------------------- */ - +/** @defgroup rcc_apb1rstr2_rst RCC_APB1RSTR2 reset values +@{*/ #define RCC_APB1RSTR2_LPTIM2RST (1 << 5) #define RCC_APB1RSTR2_SWPMI1RST (1 << 2) #define RCC_APB1RSTR2_LPUART1RST (1 << 0) +/**@}*/ +/**@}*/ -/* --- RCC_APB2RSTR values ------------------------------------------------- */ - +/** @defgroup rcc_apb2rstr_rst RCC_APB2RSTR reset values +@{*/ #define RCC_APB2RSTR_DFSDMRST (1 << 24) #define RCC_APB2RSTR_SAI2RST (1 << 22) #define RCC_APB2RSTR_SAI1RST (1 << 21) @@ -393,9 +405,12 @@ Twelve frequency ranges are available: 100 kHz, 200 kHz, 400 kHz, 800 kHz, #define RCC_APB2RSTR_SDMMC1RST (1 << 10) /* Suspect FW_RST at bit 7 to match APB2_ENR ... */ #define RCC_APB2RSTR_SYSCFGRST (1 << 0) +/**@}*/ /* --- RCC_AHB1ENR values --------------------------------------------------- */ +/** @defgroup rcc_ahbenr_en RCC_AHBxENR enable values (full set) + *@{*/ /** @defgroup rcc_ahb1enr_en RCC_AHB1ENR enable values @ingroup STM32L4xx_rcc_defines @@ -437,9 +452,12 @@ Twelve frequency ranges are available: 100 kHz, 200 kHz, 400 kHz, 800 kHz, #define RCC_AHB3ENR_FMCEN (1 << 0) /*@}*/ +/**@}*/ /* --- RCC_APB1ENR1 values -------------------------------------------------- */ +/** @defgroup rcc_apb1enr_en RCC_APB1ENRx enable values (full set) + *@{*/ /** @defgroup rcc_apb1enr1_en RCC_APB1ENR1 enable values @ingroup STM32L4xx_rcc_defines @@ -477,6 +495,7 @@ Twelve frequency ranges are available: 100 kHz, 200 kHz, 400 kHz, 800 kHz, #define RCC_APB1ENR2_SWPMI1EN (1 << 2) #define RCC_APB1ENR2_LPUART1EN (1 << 0) /*@}*/ +/*@}*/ /* --- RCC_APB2ENR values -------------------------------------------------- */ |