doc: cm3: nvic: convert existing docs to doxygen

Make it visible

1 files changed, 29 insertions, 20 deletions

diff --git a/include/libopencm3/cm3/nvic.h b/include/libopencm3/cm3/nvic.h
index f698854d..0bd51340 100644
--- a/include/libopencm3/cm3/nvic.h
+++ b/include/libopencm3/cm3/nvic.h
@@ -40,35 +40,41 @@
 #include <libopencm3/cm3/common.h>
 #include <libopencm3/cm3/memorymap.h>
 
-/* --- NVIC Registers ------------------------------------------------------ */
+/** @defgroup nvic_registers NVIC Registers
+ * @{
+ */
 
-/* ISER: Interrupt Set Enable Registers */
-/* Note: 8 32bit Registers */
-/* Note: Single register on CM0 */
+/** ISER: Interrupt Set Enable Registers
+ * @note 8 32bit Registers
+ * @note Single register on CM0
+ */
 #define NVIC_ISER(iser_id)		MMIO32(NVIC_BASE + 0x00 + \
 						((iser_id) * 4))
 
 /* NVIC_BASE + 0x020 (0xE000 E120 - 0xE000 E17F): Reserved */
 
-/* ICER: Interrupt Clear Enable Registers */
-/* Note: 8 32bit Registers */
-/* Note: Single register on CM0 */
+/** ICER: Interrupt Clear Enable Registers
+ * @note 8 32bit Registers
+ * @note Single register on CM0
+ */
 #define NVIC_ICER(icer_id)		MMIO32(NVIC_BASE + 0x80 + \
 						((icer_id) * 4))
 
 /* NVIC_BASE + 0x0A0 (0xE000 E1A0 - 0xE000 E1FF): Reserved */
 
-/* ISPR: Interrupt Set Pending Registers */
-/* Note: 8 32bit Registers */
-/* Note: Single register on CM0 */
+/** ISPR: Interrupt Set Pending Registers
+ * @note 8 32bit Registers
+ * @note Single register on CM0
+ */
 #define NVIC_ISPR(ispr_id)		MMIO32(NVIC_BASE + 0x100 + \
 						((ispr_id) * 4))
 
 /* NVIC_BASE + 0x120 (0xE000 E220 - 0xE000 E27F): Reserved */
 
-/* ICPR: Interrupt Clear Pending Registers */
-/* Note: 8 32bit Registers */
-/* Note: Single register on CM0 */
+/** ICPR: Interrupt Clear Pending Registers
+ * @note 8 32bit Registers
+ * @note Single register on CM0
+ */
 #define NVIC_ICPR(icpr_id)		MMIO32(NVIC_BASE + 0x180 + \
 						((icpr_id) * 4))
 
@@ -76,25 +82,28 @@
 
 /* Those defined only on ARMv7 and above */
 #if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
-/* IABR: Interrupt Active Bit Register */
-/* Note: 8 32bit Registers */
+/** IABR: Interrupt Active Bit Register
+ * @note 8 32bit Registers */
 #define NVIC_IABR(iabr_id)		MMIO32(NVIC_BASE + 0x200 + \
 						((iabr_id) * 4))
 #endif
 
 /* NVIC_BASE + 0x220 (0xE000 E320 - 0xE000 E3FF): Reserved */
 
-/* IPR: Interrupt Priority Registers */
-/* Note: 240 8bit Registers */
-/* Note: 32 8bit Registers on CM0 */
+/** IPR: Interrupt Priority Registers
+ * @note 240 8bit Registers
+ * @@note 32 8bit Registers on CM0
+ */
 #define NVIC_IPR(ipr_id)		MMIO8(NVIC_BASE + 0x300 + \
 						(ipr_id))
 
 #if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
-/* STIR: Software Trigger Interrupt Register */
+/** STIR: Software Trigger Interrupt Register */
 #define NVIC_STIR			MMIO32(STIR_BASE)
 #endif
 
+/**@}*/
+
 /* --- IRQ channel numbers-------------------------------------------------- */
 
 /* Cortex M0, M3 and M4 System Interrupts */
@@ -126,7 +135,7 @@ IRQ numbers -3 and -6 to -9 are reserved
 #define NVIC_SYSTICK_IRQ		-1
 /**@}*/
 
-/* Note: User interrupts are family specific and are defined in a family
+/* @note User interrupts are family specific and are defined in a family
  * specific header file in the corresponding subfolder.
  */