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| author | Guillaume Revaillot <revaillot@archos.com> | 2019-06-19 11:44:46 +0300 |
|---|---|---|
| committer | Guillaume Revaillot <revaillot@archos.com> | 2019-07-02 19:27:43 +0300 |
| commit | 689e326f5f1051528928b069611fa7779b677754 (patch) | |
| tree | 3e4493ec945505d68e78bdeaff6d7253b671e4b2 | |
| parent | 689496540887d98054c415ed4465a67c4bb69955 (diff) | |
stm32f4: lptim1 sits at 0x40002400 on stm32f410, update memorymap
| -rw-r--r-- | include/libopencm3/stm32/f4/memorymap.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/include/libopencm3/stm32/f4/memorymap.h b/include/libopencm3/stm32/f4/memorymap.h index fc2c59df..759e477f 100644 --- a/include/libopencm3/stm32/f4/memorymap.h +++ b/include/libopencm3/stm32/f4/memorymap.h @@ -44,7 +44,7 @@ #define TIM12_BASE (PERIPH_BASE_APB1 + 0x1800) #define TIM13_BASE (PERIPH_BASE_APB1 + 0x1c00) #define TIM14_BASE (PERIPH_BASE_APB1 + 0x2000) -/* PERIPH_BASE_APB1 + 0x2400 (0x4000 2400 - 0x4000 27FF): Reserved */ +#define LPTIM1_BASE (PERIPH_BASE_APB1 + 0x2400) #define RTC_BASE (PERIPH_BASE_APB1 + 0x2800) #define WWDG_BASE (PERIPH_BASE_APB1 + 0x2c00) #define IWDG_BASE (PERIPH_BASE_APB1 + 0x3000) |