diff options
| author | Karl Palsson <karlp@etactica.com> | 2018-09-24 13:35:16 +0300 |
|---|---|---|
| committer | Karl Palsson <karlp@etactica.com> | 2018-09-24 13:35:16 +0300 |
| commit | 6b0fd864a1f9ff444c1dcc412d5e25965f6b60c1 (patch) | |
| tree | 9c1ef983eca7c3278ad3086b52d0804062cb8f44 | |
| parent | 0d7f1f77087a95748f1ad2d96ce58888e93dcab4 (diff) | |
stm32f7: fix RCC_APB1 defns for USART7/USART8
The reset and low power definitions for USART7/USART8 were correct, but
not the primary enable registers.
Fixes: https://github.com/libopencm3/libopencm3/issues/969
| -rw-r--r-- | include/libopencm3/stm32/f7/rcc.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/include/libopencm3/stm32/f7/rcc.h b/include/libopencm3/stm32/f7/rcc.h index 066818a9..2bb3e76f 100644 --- a/include/libopencm3/stm32/f7/rcc.h +++ b/include/libopencm3/stm32/f7/rcc.h @@ -708,8 +708,8 @@ enum rcc_periph_clken { RCC_CEC = _REG_BIT(0x40, 27), RCC_PWR = _REG_BIT(0x40, 28), RCC_DAC = _REG_BIT(0x40, 29), - RCC_SPI7 = _REG_BIT(0x40, 30), - RCC_SPI8 = _REG_BIT(0x40, 31), + RCC_USART7 = _REG_BIT(0x40, 30), + RCC_USART8 = _REG_BIT(0x40, 31), /* APB2 peripherals */ RCC_TIM1 = _REG_BIT(0x44, 0), |