Merge branch 'feature/usb_ulpi' into 'master'

Feature/usb ulpi

See merge request thirdpin_team/libopencm3!1

8 files changed, 230 insertions, 9 deletions

diff --git a/include/libopencm3/usb/dwc/otg_common.h b/include/libopencm3/usb/dwc/otg_common.h
index 8a703713..e85184c7 100644
--- a/include/libopencm3/usb/dwc/otg_common.h
+++ b/include/libopencm3/usb/dwc/otg_common.h
@@ -248,7 +248,9 @@
 #define OTG_DCTL_RWUSIG		(1 << 0)
 
 /* OTG device configuration register (OTG_DCFG) */
-#define OTG_DCFG_DSPD		0x0003
+#define OTG_DCFG_DSPD_MASK  (0b11 << 0)
+#define OTG_DCFG_DSPD_FS_INT 0x0003 
+#define OTG_DCFG_DSPD 		OTG_DCFG_DSPD_FS_INT
 #define OTG_DCFG_NZLSOHSK	0x0004
 #define OTG_DCFG_DAD		0x07F0
 #define OTG_DCFG_PFIVL		0x1800
diff --git a/include/libopencm3/usb/dwc/otg_hs.h b/include/libopencm3/usb/dwc/otg_hs.h
index 7b5124cd..b85d7c61 100644
--- a/include/libopencm3/usb/dwc/otg_hs.h
+++ b/include/libopencm3/usb/dwc/otg_hs.h
@@ -141,7 +141,7 @@
 #define OTG_DIEPEACHMSK1_INEPNMM	(1 << 5)
 #define OTG_DIEPEACHMSK1_ITTXFEMSK	(1 << 4)
 #define OTG_DIEPEACHMSK1_TOM		(1 << 3)
-/* Bit 2 - Reserved */
+/* Bit 2 - Reserved */	
 #define OTG_DIEPEACHMSK1_EPDM		(1 << 1)
 #define OTG_DIEPEACHMSK1_XFRCM		(1 << 0)
 
@@ -170,4 +170,29 @@
 #define OTG_HCSPLT_HUBADDR_MASK		(0x7f << 7)
 #define OTG_HCSPLT_PORTADDR_MASK	(0x7f << 0)
 
+/* OTG USB configuration register (OTG_GUSBCFG) */
+#define OTG_GUSBCFG_ULPIIPD         (1 << 25)
+#define OTG_GUSBCFG_PTCI            (1 << 24)
+#define OTG_GUSBCFG_PCCI            (1 << 23)
+#define OTG_GUSBCFG_TSDPS           (1 << 22)
+#define OTG_GUSBCFG_ULPIEVBUSI      (1 << 21)
+#define OTG_GUSBCFG_ULPIEVBUSD      (1 << 20)
+#define OTG_GUSBCFG_ULPICSM         (1 << 19)
+#define OTG_GUSBCFG_ULPIAR          (1 << 18)
+#define OTG_GUSBCFG_ULPIFSLS        (1 << 17)
+#define OTG_GUSBCFG_PHYLPCS         (1 << 15)
+
+/* OTG device configuration register (OTG_DCFG) */
+#define OTG_DCFG_DSPD_HS_EXT (0x0 << 0) 
+#define OTG_DCFG_DSPD_FS_EXT (0x1 << 0) 
+
+/* OTG AHB configuration register (OTG_GAHBCFG) */
+#define OTG_GAHBCFG_HBSTLEN_MASK    (0xf << 1)
+#define OTG_GAHBCFG_HBSTLEN_SINGLE  (0b0000 << 1)
+#define OTG_GAHBCFG_HBSTLEN_INCR    (0b0001 << 1)
+#define OTG_GAHBCFG_HBSTLEN_INCR4   (0b0011 << 1)
+#define OTG_GAHBCFG_HBSTLEN_INCR8   (0b0101 << 1)
+#define OTG_GAHBCFG_HBSTLEN_INCR16  (0b0111 << 1)
+#define OTG_GAHBCFG_DMAEN           (1 << 5)
+
 #endif
diff --git a/include/libopencm3/usb/usbd.h b/include/libopencm3/usb/usbd.h
index b0ba701d..3decd762 100644
--- a/include/libopencm3/usb/usbd.h
+++ b/include/libopencm3/usb/usbd.h
@@ -55,9 +55,13 @@ typedef struct _usbd_device usbd_device;
 extern const usbd_driver st_usbfs_v1_usb_driver;
 extern const usbd_driver stm32f107_usb_driver;
 extern const usbd_driver stm32f207_usb_driver;
+extern const usbd_driver stm32_dwc_usb_driver;
+extern const usbd_driver stm32_dwc_usb_driver_ulpi;
 extern const usbd_driver st_usbfs_v2_usb_driver;
 #define otgfs_usb_driver stm32f107_usb_driver
 #define otghs_usb_driver stm32f207_usb_driver
+#define otghs_usb_driver_dwc stm32_dwc_usb_driver
+#define otghs_usb_driver_dwc_ulpi stm32_dwc_usb_driver_ulpi
 extern const usbd_driver efm32lg_usb_driver;
 extern const usbd_driver efm32hg_usb_driver;
 extern const usbd_driver lm4f_usb_driver;
diff --git a/lib/stm32/f2/Makefile b/lib/stm32/f2/Makefile
index 0d329513..4b143e58 100644
--- a/lib/stm32/f2/Makefile
+++ b/lib/stm32/f2/Makefile
@@ -50,7 +50,7 @@ OBJS		+= flash_common_idcache.o
 OBJS		+= rng_common_v1.o
 OBJS            += spi_common_all.o spi_common_v1.o spi_common_v1_frf.o
 
-OBJS            += usb.o usb_standard.o usb_control.o usb_dwc_common.o \
+OBJS            += usb.o usb_standard.o usb_control.o usb_dwc.o usb_dwc_common.o \
                    usb_f107.o usb_f207.o usb_msc.o
 
 OBJS		+= sdio_common_all.o 
diff --git a/lib/stm32/f4/Makefile b/lib/stm32/f4/Makefile
index 566cd3d3..91ccf4b9 100644
--- a/lib/stm32/f4/Makefile
+++ b/lib/stm32/f4/Makefile
@@ -57,7 +57,7 @@ OBJS		+= spi_common_all.o spi_common_v1.o spi_common_v1_frf.o
 
 OBJS		+= sdio_common_all.o 
 
-OBJS            += usb.o usb_standard.o usb_control.o usb_dwc_common.o \
+OBJS            += usb.o usb_standard.o usb_control.o usb_dwc.o usb_dwc_common.o \
 		   usb_f107.o usb_f207.o usb_msc.o
 
 OBJS		+= mac.o phy.o mac_stm32fxx7.o phy_ksz80x1.o fmc.o
diff --git a/lib/usb/usb_dwc.c b/lib/usb/usb_dwc.c
new file mode 100644
index 00000000..dc9b0d6e
--- /dev/null
+++ b/lib/usb/usb_dwc.c
@@ -0,0 +1,188 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2011 Gareth McMullin <gareth@blacksphere.co.nz>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <string.h>
+#include <libopencm3/cm3/common.h>
+#include <libopencm3/stm32/tools.h>
+#include <libopencm3/stm32/rcc.h>
+#include <libopencm3/usb/usbd.h>
+#include <libopencm3/usb/dwc/otg_hs.h>
+#include "usb_private.h"
+#include "usb_dwc_common.h"
+#include "libopencm3/stm32/memorymap.h"
+
+/* Receive FIFO size in 32-bit words. */
+#define RX_FIFO_SIZE 512
+
+static usbd_device *stm32_dwc_usbd_init(void);
+static usbd_device *stm32_dwc_ulpi_usbd_init(void);
+
+/*---------------------------------------------------------------------------*/
+/** @brief Issue Pipeline Stall
+
+Issue a pipeline stall to make sure all write operations completed.
+
+After performing a data write operation and before using peripheral,
+the software can issue a DSB instruction to guarantee the 
+completion of a previous data write operation.
+
+*/
+
+static inline void pipeline_stall(void);
+
+static struct _usbd_device usbd_dev;
+
+const struct _usbd_driver stm32_dwc_usb_driver = {
+	.init = stm32_dwc_usbd_init,
+	.set_address = dwc_set_address,
+	.ep_setup = dwc_ep_setup,
+	.ep_reset = dwc_endpoints_reset,
+	.ep_stall_set = dwc_ep_stall_set,
+	.ep_stall_get = dwc_ep_stall_get,
+	.ep_nak_set = dwc_ep_nak_set,
+	.ep_write_packet = dwc_ep_write_packet,
+	.ep_read_packet = dwc_ep_read_packet,
+	.poll = dwc_poll,
+	.disconnect = dwc_disconnect,
+	.base_address = USB_OTG_HS_BASE,
+	.set_address_before_status = 1,
+	.rx_fifo_size = RX_FIFO_SIZE,
+};
+
+const struct _usbd_driver stm32_dwc_usb_driver_ulpi = {
+	.init = stm32_dwc_ulpi_usbd_init,
+	.set_address = dwc_set_address,
+	.ep_setup = dwc_ep_setup,
+	.ep_reset = dwc_endpoints_reset,
+	.ep_stall_set = dwc_ep_stall_set,
+	.ep_stall_get = dwc_ep_stall_get,
+	.ep_nak_set = dwc_ep_nak_set,
+	.ep_write_packet = dwc_ep_write_packet,
+	.ep_read_packet = dwc_ep_read_packet,
+	.poll = dwc_poll,
+	.disconnect = dwc_disconnect,
+	.base_address = USB_OTG_HS_BASE,
+	.set_address_before_status = 1,
+	.rx_fifo_size = RX_FIFO_SIZE,
+};
+
+/** Initialize the USB device controller hardware of the STM32. */
+static usbd_device *stm32_dwc_usbd_init(void)
+{
+	rcc_periph_clock_enable(RCC_OTGHS);
+	OTG_HS_GINTSTS = OTG_GINTSTS_MMIS;
+
+	OTG_HS_GUSBCFG |= OTG_GUSBCFG_PHYSEL;
+	/* Enable VBUS sensing in device mode and power down the PHY. */
+	OTG_HS_GCCFG |= OTG_GCCFG_VBUSBSEN | OTG_GCCFG_PWRDWN;
+
+	/* Wait for AHB idle. */
+	while (!(OTG_HS_GRSTCTL & OTG_GRSTCTL_AHBIDL));
+	/* Do core soft reset. */
+	OTG_HS_GRSTCTL |= OTG_GRSTCTL_CSRST;
+	while (OTG_HS_GRSTCTL & OTG_GRSTCTL_CSRST);
+
+	/* Force peripheral only mode. */
+	OTG_HS_GUSBCFG |= OTG_GUSBCFG_FDMOD | OTG_GUSBCFG_TRDT_MASK;
+
+	/* Full speed internal embedded PHY device. */
+	OTG_HS_DCFG |= OTG_DCFG_DSPD;
+
+	/* Restart the PHY clock. */
+	OTG_HS_PCGCCTL = 0;
+
+	OTG_HS_GRXFSIZ = stm32_dwc_usb_driver.rx_fifo_size;
+	usbd_dev.fifo_mem_top = stm32_dwc_usb_driver.rx_fifo_size;
+
+	/* Unmask interrupts for TX and RX. */
+	OTG_HS_GAHBCFG |= OTG_GAHBCFG_GINT;
+	OTG_HS_GINTMSK = OTG_GINTMSK_ENUMDNEM |
+			 OTG_GINTMSK_RXFLVLM |
+			 OTG_GINTMSK_IEPINT |
+			 OTG_GINTMSK_USBSUSPM |
+			 OTG_GINTMSK_WUIM;
+	OTG_HS_DAINTMSK = 0xF;
+	OTG_HS_DIEPMSK = OTG_DIEPMSK_XFRCM;
+
+	return &usbd_dev;
+}
+
+/** Initialize the USB device controller hardware of the STM32. ULPI variant */
+static usbd_device *stm32_dwc_ulpi_usbd_init(void)
+{
+	rcc_periph_clock_enable(RCC_OTGHS);
+	pipeline_stall()
+    rcc_periph_clock_enable(RCC_OTGHSULPI);
+	pipeline_stall()
+
+	/* Wait for AHB idle. */
+	while (!(OTG_HS_GRSTCTL & OTG_GRSTCTL_AHBIDL));
+	/* Do core soft reset. */
+	OTG_HS_GRSTCTL |= OTG_GRSTCTL_CSRST;
+	while (OTG_HS_GRSTCTL & OTG_GRSTCTL_CSRST);
+
+	/* Force peripheral only mode. */
+	OTG_HS_GUSBCFG |= OTG_GUSBCFG_FDMOD;
+	/* Full speed external ULPI PHY device. */
+	OTG_HS_DCFG |= OTG_DCFG_DSPD_HS_EXT;
+
+	/* Restart the PHY clock. */
+	OTG_HS_PCGCCTL = 0U;
+
+	OTG_HS_GRXFSIZ = stm32_dwc_usb_driver_ulpi.rx_fifo_size;
+	usbd_dev.fifo_mem_top = stm32_dwc_usb_driver_ulpi.rx_fifo_size;
+
+    /* Flush the FIFOs */
+    OTG_HS_GRSTCTL = (OTG_GRSTCTL_TXFFLSH | (0x10U << 6));
+    while ((OTG_HS_GRSTCTL & OTG_GRSTCTL_TXFFLSH) == OTG_GRSTCTL_TXFFLSH)
+        ;
+
+    OTG_HS_GRSTCTL = OTG_GRSTCTL_RXFFLSH;
+    while ((OTG_HS_GRSTCTL & OTG_GRSTCTL_RXFFLSH) == OTG_GRSTCTL_RXFFLSH)
+        ;
+
+    /* Clear all pending Device Interrupts */
+	OTG_HS_DIEPMSK = 0U;
+	OTG_HS_DOEPMSK = 0U;
+	OTG_HS_DAINTMSK = 0U;
+
+	/* Disable all interrupts. */
+	OTG_HS_GINTMSK = 0U;
+
+	/* Clear any pending interrupts */
+	OTG_HS_GINTSTS = 0xBFFFFFFFU;
+
+	/* Unmask interrupts for TX and RX. */
+	OTG_HS_GAHBCFG |= OTG_GAHBCFG_GINT;
+	OTG_HS_GINTMSK = OTG_GINTMSK_ENUMDNEM |
+			 OTG_GINTMSK_RXFLVLM |
+			 OTG_GINTMSK_IEPINT |
+			 OTG_GINTMSK_USBSUSPM |
+			 OTG_GINTMSK_WUIM;
+
+	OTG_HS_DAINTMSK = 0xFU;
+	OTG_HS_DIEPMSK = OTG_DIEPMSK_XFRCM;
+
+	return &usbd_dev;
+}
+
+static inline void pipeline_stall(void)
+{
+	__asm__ volatile("dsb":::"memory");
+}
diff --git a/lib/usb/usb_dwc_common.c b/lib/usb/usb_dwc_common.c
index 162bfd7c..ae80db40 100644
--- a/lib/usb/usb_dwc_common.c
+++ b/lib/usb/usb_dwc_common.c
@@ -119,7 +119,7 @@ void dwc_endpoints_reset(usbd_device *usbd_dev)
 	usbd_dev->fifo_mem_top = usbd_dev->fifo_mem_top_ep0;
 
 	/* Disable any currently active endpoints */
-	for (i = 1; i < 4; i++) {
+	for (i = 1; i < ENDPOINT_COUNT; i++) {
 		if (REBASE(OTG_DOEPCTL(i)) & OTG_DOEPCTL0_EPENA) {
 			REBASE(OTG_DOEPCTL(i)) |= OTG_DOEPCTL0_EPDIS;
 		}
@@ -339,7 +339,7 @@ void dwc_poll(usbd_device *usbd_dev)
 	 * There is no global interrupt flag for transmit complete.
 	 * The XFRC bit must be checked in each OTG_DIEPINT(x).
 	 */
-	for (i = 0; i < 4; i++) { /* Iterate over endpoints. */
+	for (i = 0; i < ENDPOINT_COUNT; i++) { /* Iterate over endpoints. */
 		if (REBASE(OTG_DIEPINT(i)) & OTG_DIEPINTX_XFRC) {
 			/* Transfer complete. */
 			if (usbd_dev->user_callback_ctr[i]
diff --git a/lib/usb/usb_private.h b/lib/usb/usb_private.h
index 3aa3f9ee..8e1a091c 100644
--- a/lib/usb/usb_private.h
+++ b/lib/usb/usb_private.h
@@ -41,6 +41,8 @@ LGPL License Terms @ref lgpl_license
 #define MAX_USER_CONTROL_CALLBACK	4
 #define MAX_USER_SET_CONFIG_CALLBACK	4
 
+#define ENDPOINT_COUNT 8
+
 #define MIN(a, b) ((a) < (b) ? (a) : (b))
 
 /** Internal collection of device information. */
@@ -83,7 +85,7 @@ struct _usbd_device {
 		uint8_t type_mask;
 	} user_control_callback[MAX_USER_CONTROL_CALLBACK];
 
-	usbd_endpoint_callback user_callback_ctr[8][3];
+	usbd_endpoint_callback user_callback_ctr[ENDPOINT_COUNT][3];
 
 	/* User callback function for some standard USB function hooks */
 	usbd_set_config_callback user_callback_set_config[MAX_USER_SET_CONFIG_CALLBACK];
@@ -96,12 +98,12 @@ struct _usbd_device {
 
 	uint16_t fifo_mem_top;
 	uint16_t fifo_mem_top_ep0;
-	uint8_t force_nak[4];
+	uint8_t force_nak[ENDPOINT_COUNT];
 	/*
 	 * We keep a backup copy of the out endpoint size registers to restore
 	 * them after a transaction.
 	 */
-	uint32_t doeptsiz[4];
+	uint32_t doeptsiz[ENDPOINT_COUNT];
 	/*
 	 * Received packet size for each endpoint. This is assigned in
 	 * stm32f107_poll() which reads the packet status push register GRXSTSP