diff options
| author | Guillaume Revaillot <revaillot@archos.com> | 2019-02-05 17:33:55 +0300 |
|---|---|---|
| committer | Karl Palsson <karlp@tweak.net.au> | 2019-06-04 01:29:45 +0300 |
| commit | a65285653376717390cff0e0377a732835b782b1 (patch) | |
| tree | 259111686fe84d9f3dce37e058e32f0ae5cab138 | |
| parent | 8668f9198b48dfd6bdba55baa834c52f20710884 (diff) | |
stm32l0: rcc: add rcc_set_peripheral_clk_sel(periph, sel)
| -rw-r--r-- | include/libopencm3/stm32/l0/rcc.h | 2 | ||||
| -rw-r--r-- | lib/stm32/l0/rcc.c | 50 |
2 files changed, 52 insertions, 0 deletions
diff --git a/include/libopencm3/stm32/l0/rcc.h b/include/libopencm3/stm32/l0/rcc.h index 593137e1..a9d7af09 100644 --- a/include/libopencm3/stm32/l0/rcc.h +++ b/include/libopencm3/stm32/l0/rcc.h @@ -695,6 +695,8 @@ void rcc_clock_setup_pll(const struct rcc_clock_scale *clock); void rcc_set_msi_range(uint32_t msi_range); +void rcc_set_peripheral_clk_sel(uint32_t periph, uint32_t sel); + void rcc_set_lptim1_sel(uint32_t lptim1_sel); void rcc_set_lpuart1_sel(uint32_t lpupart1_sel); void rcc_set_usart1_sel(uint32_t usart1_sel); diff --git a/lib/stm32/l0/rcc.c b/lib/stm32/l0/rcc.c index 7605e6ae..4f902f87 100644 --- a/lib/stm32/l0/rcc.c +++ b/lib/stm32/l0/rcc.c @@ -435,6 +435,7 @@ void rcc_set_usart1_sel(uint32_t usart1_sel) RCC_CCIPR &= ~(RCC_CCIPR_USART1SEL_MASK << RCC_CCIPR_USART1SEL_SHIFT); RCC_CCIPR |= (usart1_sel << RCC_CCIPR_USART1SEL_SHIFT); } + /*---------------------------------------------------------------------------*/ /** @brief Set the USART2 clock source * @@ -446,6 +447,55 @@ void rcc_set_usart2_sel(uint32_t usart2_sel) RCC_CCIPR |= (usart2_sel << RCC_CCIPR_USART2SEL_SHIFT); } +/*---------------------------------------------------------------------------*/ +/** @brief Set the peripheral clock source +* + * @param sel periphral clock source + */ +void rcc_set_peripheral_clk_sel(uint32_t periph, uint32_t sel) +{ + uint8_t shift; + uint32_t mask; + + switch (periph) { + case LPTIM1_BASE: + shift = RCC_CCIPR_LPTIM1SEL_SHIFT; + mask = RCC_CCIPR_LPTIM1SEL_MASK; + break; + + case I2C3_BASE: + shift = RCC_CCIPR_I2C3SEL_SHIFT; + mask = RCC_CCIPR_I2C3SEL_MASK; + break; + + case I2C1_BASE: + shift = RCC_CCIPR_I2C1SEL_SHIFT; + mask = RCC_CCIPR_I2C1SEL_MASK; + break; + + case LPUART1_BASE: + shift = RCC_CCIPR_LPUART1SEL_SHIFT; + mask = RCC_CCIPR_LPUART1SEL_MASK; + break; + + case USART2_BASE: + shift = RCC_CCIPR_USART2SEL_SHIFT; + mask = RCC_CCIPR_USART2SEL_MASK; + break; + + case USART1_BASE: + shift = RCC_CCIPR_USART1SEL_SHIFT; + mask = RCC_CCIPR_USART1SEL_MASK; + break; + + default: + return; + } + + uint32_t reg32 = RCC_CCIPR & ~(mask << shift); + RCC_CCIPR = reg32 | (sel << shift); +} + /** * Set up sysclock with PLL from HSI16 * @param clock full struct with desired parameters |