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| author | Guillaume Revaillot <revaillot@archos.com> | 2019-07-03 18:19:48 +0300 |
|---|---|---|
| committer | Guillaume Revaillot <revaillot@archos.com> | 2019-07-05 12:43:11 +0300 |
| commit | f99e7118732f5749f9de2c56fccb0c5ac05fdf00 (patch) | |
| tree | afa5d8859bb659ca4c76fec284b4045bf807598d | |
| parent | 811aebf09600642ac3076192bf35eafc7370582b (diff) | |
stm32g0: lptim: add additional cr bits and cfgr2 reg.
| -rw-r--r-- | include/libopencm3/stm32/g0/lptimer.h | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/include/libopencm3/stm32/g0/lptimer.h b/include/libopencm3/stm32/g0/lptimer.h index 183f9b4e..e3606d7c 100644 --- a/include/libopencm3/stm32/g0/lptimer.h +++ b/include/libopencm3/stm32/g0/lptimer.h @@ -39,6 +39,29 @@ #define LPTIM2 LPTIM2_BASE /**@}*/ +/** LPTIM_CFGR2 LPTIM configuration register 2 */ +#define LPTIM_CFGR2(tim_base) MMIO32((tim_base) + 0x24) + +/** @addtogroup lptim_cr +@{*/ +/** COUNTRST Counter reset **/ +#define LPTIM_CR_COUNTRST (1 << 3) +/** RSTARE Reset after read enable **/ +#define LPTIM_CR_RSTARE (1 << 4) +/**@}*/ + +/** @defgroup lptim_cfgr2 LPTIM_CFGR2 Configuration Register 2 +@{*/ + +#define LPTIM_CFGR2_IN2SEL_SHIFT 4 +#define LPTIM_CFGR2_IN2SEL_MASK 0x03 + +#define LPTIM_CFGR2_IN1SEL_SHIFT 0 +#define LPTIM_CFGR2_IN1SEL_MASK 0x03 + +/**@}*/ + + BEGIN_DECLS END_DECLS |